Commit 92a05b10 authored by Daniel Krebs's avatar Daniel Krebs
Browse files

SubVI for NI9503-FPGA created.

parent c5ff4555
[ProjectWindow_Data]
ProjectExplorer.ClassicPosition[String] = "36,-1270,1018,-884"
ProjectExplorer.ClassicPosition[String] = "33,-1269,1015,-883"
......@@ -403,6 +403,11 @@ AddOutputFilter chunkFilter
<Property Name="configString.name" Type="Str">40 MHz Onboard ClockResourceName=40 MHz Onboard Clock;TopSignalConnect=Clk40;ClockSignalName=Clk40;MinFreq=40000000.000000;MaxFreq=40000000.000000;VariableFreq=0;NomFreq=40000000.000000;PeakPeriodJitter=250.000000;MinDutyCycle=50.000000;MaxDutyCycle=50.000000;Accuracy=100.000000;RunTime=0;SpreadSpectrum=0;GenericDataHash=D41D8CD98F00B204E9800998ECF8427EChassis Temperatureresource=/Chassis Temperature;0;ReadMethodType=i16cRIO-9068/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSCRIO_9068FPGA_TARGET_FAMILYZYNQTARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End]Mod2/Phase A Currentresource=/crio_Mod2/Phase A Current;0;ReadMethodType=I16Mod2/Phase A Negresource=/crio_Mod2/Phase A Neg;0;WriteMethodType=boolMod2/Phase A Posresource=/crio_Mod2/Phase A Pos;0;WriteMethodType=boolMod2/Phase B Currentresource=/crio_Mod2/Phase B Current;0;ReadMethodType=I16Mod2/Phase B Negresource=/crio_Mod2/Phase B Neg;0;WriteMethodType=boolMod2/Phase B Posresource=/crio_Mod2/Phase B Pos;0;WriteMethodType=boolMod2/User LEDresource=/crio_Mod2/User LED;0;WriteMethodType=boolMod2/Vsup Voltageresource=/crio_Mod2/Vsup Voltage;0;ReadMethodType=u16Mod2[crioConfig.Begin]crio.Calibration=1,crio.Location=Slot 2,crio.Type=NI 9503[crioConfig.End]Mod8/Phase A Currentresource=/crio_Mod8/Phase A Current;0;ReadMethodType=I16Mod8/Phase A Negresource=/crio_Mod8/Phase A Neg;0;WriteMethodType=boolMod8/Phase A Posresource=/crio_Mod8/Phase A Pos;0;WriteMethodType=boolMod8/Phase B Currentresource=/crio_Mod8/Phase B Current;0;ReadMethodType=I16Mod8/Phase B Negresource=/crio_Mod8/Phase B Neg;0;WriteMethodType=boolMod8/Phase B Posresource=/crio_Mod8/Phase B Pos;0;WriteMethodType=boolMod8/User LEDresource=/crio_Mod8/User LED;0;WriteMethodType=boolMod8/Vsup Voltageresource=/crio_Mod8/Vsup Voltage;0;ReadMethodType=u16Mod8[crioConfig.Begin]crio.Calibration=1,crio.Location=Slot 8,crio.Type=NI 9503[crioConfig.End]Scan Clockresource=/Scan Clock;0;ReadMethodType=boolSleepresource=/Sleep;0;ReadMethodType=bool;WriteMethodType=boolSystem Resetresource=/System Reset;0;ReadMethodType=bool;WriteMethodType=boolUSER FPGA LEDresource=/USER FPGA LED;0;ReadMethodType=u8;WriteMethodType=u8</Property>
<Property Name="NI.LV.FPGA.InterfaceBitfile" Type="Str">C:\User\Krebs\LVP\Detlab\GDP-NI9503-new-attempt\FPGA Bitfiles\GDP-NI9503-Stepp_FPGATarget_GDP-NI9503-Stepp_uqLuDwvaz8Q.lvbitx</Property>
</Item>
<Item Name="GDP-NI9503-SubVI.vi" Type="VI" URL="../GDP-NI9503-SubVI.vi">
<Property Name="configString.guid" Type="Str">{1FAB2187-5FDF-4D80-B75E-07A610C9CB17}resource=/crio_Mod8/Phase B Pos;0;WriteMethodType=bool{4EFD86C0-792F-4B97-892E-778BA295D8C6}resource=/crio_Mod2/Phase B Neg;0;WriteMethodType=bool{524A6CF9-2631-4890-B853-FD3A46A1CE46}[crioConfig.Begin]crio.Calibration=1,crio.Location=Slot 2,crio.Type=NI 9503[crioConfig.End]{53F32106-4D81-471E-9300-07B9D924A859}resource=/Scan Clock;0;ReadMethodType=bool{5A5BC916-492C-4E93-890E-945655CDB66D}resource=/System Reset;0;ReadMethodType=bool;WriteMethodType=bool{63AE5859-9011-477E-8E4F-375473740DAF}ResourceName=40 MHz Onboard Clock;TopSignalConnect=Clk40;ClockSignalName=Clk40;MinFreq=40000000.000000;MaxFreq=40000000.000000;VariableFreq=0;NomFreq=40000000.000000;PeakPeriodJitter=250.000000;MinDutyCycle=50.000000;MaxDutyCycle=50.000000;Accuracy=100.000000;RunTime=0;SpreadSpectrum=0;GenericDataHash=D41D8CD98F00B204E9800998ECF8427E{74B52144-4566-4772-9E96-53028B4CE236}resource=/Sleep;0;ReadMethodType=bool;WriteMethodType=bool{95D32FE8-36C5-4D40-B324-F096B4029803}resource=/crio_Mod8/Vsup Voltage;0;ReadMethodType=u16{9B5A7F85-954E-408C-BC24-777780D8F867}[crioConfig.Begin]crio.Calibration=1,crio.Location=Slot 8,crio.Type=NI 9503[crioConfig.End]{A38D886E-4528-4AEA-BA31-1827EC369A7A}resource=/crio_Mod8/Phase A Neg;0;WriteMethodType=bool{A62615B2-7518-44A2-9FE1-8418CB3DF33C}resource=/Chassis Temperature;0;ReadMethodType=i16{BE455928-A900-4A6A-B47D-32189D6A18BE}resource=/crio_Mod2/Phase A Neg;0;WriteMethodType=bool{C08DF885-E8A2-4D7A-8B48-F46326296823}resource=/USER FPGA LED;0;ReadMethodType=u8;WriteMethodType=u8{C6822F06-6CE0-4F32-8887-4459EB5391F7}resource=/crio_Mod8/Phase A Current;0;ReadMethodType=I16{C6B48F5D-81A8-4283-8C29-D61856AB18CC}resource=/crio_Mod8/Phase B Neg;0;WriteMethodType=bool{CD2B096F-CED9-4826-A525-9803675EADCC}resource=/crio_Mod8/Phase B Current;0;ReadMethodType=I16{D70F0CFE-9C64-4768-829B-6E9F82A88D86}resource=/crio_Mod2/Phase A Pos;0;WriteMethodType=bool{E06FAC0A-4766-45EB-AE42-E1D6E3A54671}resource=/crio_Mod2/Phase A Current;0;ReadMethodType=I16{E29FB16B-CC07-4C68-B1C3-FC7A229A934D}resource=/crio_Mod8/Phase A Pos;0;WriteMethodType=bool{E6020BB2-8458-4AC0-9F15-F5C6B7E278BA}resource=/crio_Mod2/Phase B Pos;0;WriteMethodType=bool{EB35AC4C-6D00-44F6-BE27-3AA6267C6D98}resource=/crio_Mod8/User LED;0;WriteMethodType=bool{ED1B8DEF-EDC6-487B-BD5D-72A2E1C899AE}resource=/crio_Mod2/User LED;0;WriteMethodType=bool{F4010AA5-036B-4EA5-AECA-7C9362442B84}resource=/crio_Mod2/Phase B Current;0;ReadMethodType=I16{F5223F1B-1403-4D14-9F5A-C1D669C73C36}resource=/crio_Mod2/Vsup Voltage;0;ReadMethodType=u16cRIO-9068/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSCRIO_9068FPGA_TARGET_FAMILYZYNQTARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End]</Property>
<Property Name="configString.name" Type="Str">40 MHz Onboard ClockResourceName=40 MHz Onboard Clock;TopSignalConnect=Clk40;ClockSignalName=Clk40;MinFreq=40000000.000000;MaxFreq=40000000.000000;VariableFreq=0;NomFreq=40000000.000000;PeakPeriodJitter=250.000000;MinDutyCycle=50.000000;MaxDutyCycle=50.000000;Accuracy=100.000000;RunTime=0;SpreadSpectrum=0;GenericDataHash=D41D8CD98F00B204E9800998ECF8427EChassis Temperatureresource=/Chassis Temperature;0;ReadMethodType=i16cRIO-9068/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSCRIO_9068FPGA_TARGET_FAMILYZYNQTARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End]Mod2/Phase A Currentresource=/crio_Mod2/Phase A Current;0;ReadMethodType=I16Mod2/Phase A Negresource=/crio_Mod2/Phase A Neg;0;WriteMethodType=boolMod2/Phase A Posresource=/crio_Mod2/Phase A Pos;0;WriteMethodType=boolMod2/Phase B Currentresource=/crio_Mod2/Phase B Current;0;ReadMethodType=I16Mod2/Phase B Negresource=/crio_Mod2/Phase B Neg;0;WriteMethodType=boolMod2/Phase B Posresource=/crio_Mod2/Phase B Pos;0;WriteMethodType=boolMod2/User LEDresource=/crio_Mod2/User LED;0;WriteMethodType=boolMod2/Vsup Voltageresource=/crio_Mod2/Vsup Voltage;0;ReadMethodType=u16Mod2[crioConfig.Begin]crio.Calibration=1,crio.Location=Slot 2,crio.Type=NI 9503[crioConfig.End]Mod8/Phase A Currentresource=/crio_Mod8/Phase A Current;0;ReadMethodType=I16Mod8/Phase A Negresource=/crio_Mod8/Phase A Neg;0;WriteMethodType=boolMod8/Phase A Posresource=/crio_Mod8/Phase A Pos;0;WriteMethodType=boolMod8/Phase B Currentresource=/crio_Mod8/Phase B Current;0;ReadMethodType=I16Mod8/Phase B Negresource=/crio_Mod8/Phase B Neg;0;WriteMethodType=boolMod8/Phase B Posresource=/crio_Mod8/Phase B Pos;0;WriteMethodType=boolMod8/User LEDresource=/crio_Mod8/User LED;0;WriteMethodType=boolMod8/Vsup Voltageresource=/crio_Mod8/Vsup Voltage;0;ReadMethodType=u16Mod8[crioConfig.Begin]crio.Calibration=1,crio.Location=Slot 8,crio.Type=NI 9503[crioConfig.End]Scan Clockresource=/Scan Clock;0;ReadMethodType=boolSleepresource=/Sleep;0;ReadMethodType=bool;WriteMethodType=boolSystem Resetresource=/System Reset;0;ReadMethodType=bool;WriteMethodType=boolUSER FPGA LEDresource=/USER FPGA LED;0;ReadMethodType=u8;WriteMethodType=u8</Property>
<Property Name="NI.LV.FPGA.InterfaceBitfile" Type="Str">C:\User\Krebs\LVP\Detlab\GDP-NI9503-new-attempt\FPGA Bitfiles\GDP-NI9503-Stepp_FPGATarget_GDP-NI9503-SubVI_CgeMcb2OXXA.lvbitx</Property>
</Item>
<Item Name="IP Builder" Type="IP Builder Target">
<Item Name="Dependencies" Type="Dependencies"/>
<Item Name="Build Specifications" Type="Build"/>
......@@ -439,6 +444,44 @@ AddOutputFilter chunkFilter
</Item>
</Item>
<Item Name="Build Specifications" Type="Build">
<Item Name="GDP-NI9503-Reentrancy-Test" Type="{F4C5E96F-7410-48A5-BB87-3559BC9B167F}">
<Property Name="AllowEnableRemoval" Type="Bool">false</Property>
<Property Name="BuildSpecDecription" Type="Str"></Property>
<Property Name="BuildSpecName" Type="Str">GDP-NI9503-Reentrancy-Test</Property>
<Property Name="Comp.BitfileName" Type="Str">GDP-NI9503-Stepp_FPGATarget_GDP-NI9503-Reent_zOR3lXI2CoA.lvbitx</Property>
<Property Name="Comp.CustomXilinxParameters" Type="Str"></Property>
<Property Name="Comp.MaxFanout" Type="Int">-1</Property>
<Property Name="Comp.RandomSeed" Type="Bool">false</Property>
<Property Name="Comp.Version.Build" Type="Int">0</Property>
<Property Name="Comp.Version.Fix" Type="Int">0</Property>
<Property Name="Comp.Version.Major" Type="Int">1</Property>
<Property Name="Comp.Version.Minor" Type="Int">0</Property>
<Property Name="Comp.VersionAutoIncrement" Type="Bool">false</Property>
<Property Name="Comp.Vivado.EnableMultiThreading" Type="Bool">true</Property>
<Property Name="Comp.Vivado.OptDirective" Type="Str"></Property>
<Property Name="Comp.Vivado.PhysOptDirective" Type="Str"></Property>
<Property Name="Comp.Vivado.PlaceDirective" Type="Str"></Property>
<Property Name="Comp.Vivado.RouteDirective" Type="Str"></Property>
<Property Name="Comp.Vivado.RunPowerOpt" Type="Bool">false</Property>
<Property Name="Comp.Vivado.Strategy" Type="Str">Default</Property>
<Property Name="Comp.Xilinx.DesignStrategy" Type="Str">balanced</Property>
<Property Name="Comp.Xilinx.MapEffort" Type="Str">default(noTiming)</Property>
<Property Name="Comp.Xilinx.ParEffort" Type="Str">standard</Property>
<Property Name="Comp.Xilinx.SynthEffort" Type="Str">normal</Property>
<Property Name="Comp.Xilinx.SynthGoal" Type="Str">speed</Property>
<Property Name="Comp.Xilinx.UseRecommended" Type="Bool">true</Property>
<Property Name="DefaultBuildSpec" Type="Bool">true</Property>
<Property Name="DestinationDirectory" Type="Path">FPGA Bitfiles</Property>
<Property Name="NI.LV.FPGA.LastCompiledBitfilePath" Type="Path">/C/User/Krebs/LVP/Detlab/GDP-NI9503-new-attempt/FPGA Bitfiles/GDP-NI9503-Stepp_FPGATarget_GDP-NI9503-Reent_zOR3lXI2CoA.lvbitx</Property>
<Property Name="NI.LV.FPGA.LastCompiledBitfilePathRelativeToProject" Type="Path">FPGA Bitfiles/GDP-NI9503-Stepp_FPGATarget_GDP-NI9503-Reent_zOR3lXI2CoA.lvbitx</Property>
<Property Name="ProjectPath" Type="Path">/C/User/Krebs/LVP/Detlab/GDP-NI9503-new-attempt/GDP-NI9503-Stepper-Drive.lvproj</Property>
<Property Name="RelativePath" Type="Bool">true</Property>
<Property Name="RunWhenLoaded" Type="Bool">false</Property>
<Property Name="SupportDownload" Type="Bool">true</Property>
<Property Name="SupportResourceEstimation" Type="Bool">false</Property>
<Property Name="TargetName" Type="Str">FPGA Target</Property>
<Property Name="TopLevelVI" Type="Ref"></Property>
</Item>
<Item Name="GDP-NI9503-Stepper-Drive-FPGA" Type="{F4C5E96F-7410-48A5-BB87-3559BC9B167F}">
<Property Name="AllowEnableRemoval" Type="Bool">false</Property>
<Property Name="BuildSpecDecription" Type="Str"></Property>
......@@ -477,6 +520,44 @@ AddOutputFilter chunkFilter
<Property Name="TargetName" Type="Str">FPGA Target</Property>
<Property Name="TopLevelVI" Type="Ref">/RT CompactRIO Target/Chassis/FPGA Target/GDP-NI9503-Stepper-Drive-FPGA.vi</Property>
</Item>
<Item Name="GDP-NI9503-SubVI" Type="{F4C5E96F-7410-48A5-BB87-3559BC9B167F}">
<Property Name="AllowEnableRemoval" Type="Bool">false</Property>
<Property Name="BuildSpecDecription" Type="Str"></Property>
<Property Name="BuildSpecName" Type="Str">GDP-NI9503-SubVI</Property>
<Property Name="Comp.BitfileName" Type="Str">GDP-NI9503-Stepp_FPGATarget_GDP-NI9503-SubVI_CgeMcb2OXXA.lvbitx</Property>
<Property Name="Comp.CustomXilinxParameters" Type="Str"></Property>
<Property Name="Comp.MaxFanout" Type="Int">-1</Property>
<Property Name="Comp.RandomSeed" Type="Bool">false</Property>
<Property Name="Comp.Version.Build" Type="Int">0</Property>
<Property Name="Comp.Version.Fix" Type="Int">0</Property>
<Property Name="Comp.Version.Major" Type="Int">1</Property>
<Property Name="Comp.Version.Minor" Type="Int">0</Property>
<Property Name="Comp.VersionAutoIncrement" Type="Bool">false</Property>
<Property Name="Comp.Vivado.EnableMultiThreading" Type="Bool">true</Property>
<Property Name="Comp.Vivado.OptDirective" Type="Str"></Property>
<Property Name="Comp.Vivado.PhysOptDirective" Type="Str"></Property>
<Property Name="Comp.Vivado.PlaceDirective" Type="Str"></Property>
<Property Name="Comp.Vivado.RouteDirective" Type="Str"></Property>
<Property Name="Comp.Vivado.RunPowerOpt" Type="Bool">false</Property>
<Property Name="Comp.Vivado.Strategy" Type="Str">Default</Property>
<Property Name="Comp.Xilinx.DesignStrategy" Type="Str">balanced</Property>
<Property Name="Comp.Xilinx.MapEffort" Type="Str">default(noTiming)</Property>
<Property Name="Comp.Xilinx.ParEffort" Type="Str">standard</Property>
<Property Name="Comp.Xilinx.SynthEffort" Type="Str">normal</Property>
<Property Name="Comp.Xilinx.SynthGoal" Type="Str">speed</Property>
<Property Name="Comp.Xilinx.UseRecommended" Type="Bool">true</Property>
<Property Name="DefaultBuildSpec" Type="Bool">true</Property>
<Property Name="DestinationDirectory" Type="Path">FPGA Bitfiles</Property>
<Property Name="NI.LV.FPGA.LastCompiledBitfilePath" Type="Path">/C/User/Krebs/LVP/Detlab/GDP-NI9503-new-attempt/FPGA Bitfiles/GDP-NI9503-Stepp_FPGATarget_GDP-NI9503-SubVI_CgeMcb2OXXA.lvbitx</Property>
<Property Name="NI.LV.FPGA.LastCompiledBitfilePathRelativeToProject" Type="Path">FPGA Bitfiles/GDP-NI9503-Stepp_FPGATarget_GDP-NI9503-SubVI_CgeMcb2OXXA.lvbitx</Property>
<Property Name="ProjectPath" Type="Path">/C/User/Krebs/LVP/Detlab/GDP-NI9503-new-attempt/GDP-NI9503-Stepper-Drive.lvproj</Property>
<Property Name="RelativePath" Type="Bool">true</Property>
<Property Name="RunWhenLoaded" Type="Bool">false</Property>
<Property Name="SupportDownload" Type="Bool">true</Property>
<Property Name="SupportResourceEstimation" Type="Bool">false</Property>
<Property Name="TargetName" Type="Str">FPGA Target</Property>
<Property Name="TopLevelVI" Type="Ref">/RT CompactRIO Target/Chassis/FPGA Target/GDP-NI9503-SubVI.vi</Property>
</Item>
</Item>
</Item>
</Item>
......
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