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<?xml version='1.0' encoding='UTF-8'?>
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<Project Type="Project" LVVersion="19008000">
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	<Property Name="CCSymbols" Type="Str">DSCGetVarList,PSP;WebpubLaunchBrowser,None;DSCSecurity,False;</Property>
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	<Property Name="NI.LV.All.SourceOnly" Type="Bool">true</Property>
	<Property Name="NI.Project.Description" Type="Str">This LabVIEW project "UTCS.lvproj" is used to develop the Unified TASCA Control System Project and is based on LVOOP, NI Actor Framework and CS++.

Related documents and information
=================================
- README.txt
- EUPL v.1.1 - Lizenz.pdf
- Contact: H.Brand@gsi.de
- Download, bug reports... : https://git.gsi.de/EE-LV/CSPP/TASCA/UTCS
- Documentation:
  - Refer to Documantation Folder
  - Project-Wikis: https://wiki.gsi.de/foswiki/bin/view/Tasca/UTCSP, https://github.com/HB-GSI/CSPP/wiki
  - NI Actor Framework: https://decibel.ni.com/content/groups/actor-framework-2011?view=overview

Author: H.Brand@gsi.de

Copyright 2017  GSI Helmholtzzentrum für Schwerionenforschung GmbH

Planckstr.1, 64291 Darmstadt, Germany

Lizenziert unter der EUPL, Version 1.1 oder - sobald diese von der Europäischen Kommission genehmigt wurden - Folgeversionen der EUPL ("Lizenz"); Sie dürfen dieses Werk ausschließlich gemäß dieser Lizenz nutzen.

Eine Kopie der Lizenz finden Sie hier: http://www.osor.eu/eupl

Sofern nicht durch anwendbare Rechtsvorschriften gefordert oder in schriftlicher Form vereinbart, wird die unter der Lizenz verbreitete Software "so wie sie ist", OHNE JEGLICHE GEWÄHRLEISTUNG ODER BEDINGUNGEN - ausdrücklich oder stillschweigend - verbreitet.

Die sprachspezifischen Genehmigungen und Beschränkungen unter der Lizenz sind dem Lizenztext zu entnehmen.</Property>
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Recompile FPGA 2018062100 with moved IOs.    
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Update submodules; adopt to CSPP_Core modifications; add Watchdog to MainGUI.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Add Interval measurement; Use Range at leading edge of macro pulse (FPGA stuff not yet finished.)    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Add Interlock SecKey.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Reorganize projects virtual structure a bit and set new version number of exe to 0.2.0.0.    
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Prepare for build with Pyrometerintegration and target wheel interlock.    
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Update submodule CSPP Utilities.PVScaler Msg    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Update submodules; adopt to CSPP_Core modifications; add Watchdog to MainGUI.    
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Update submodules; Compile FPGA for PXI-7842R    
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Recompile FPGA 2018062100 with moved IOs.    
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Update submodules; Compile FPGA for PXI-7842R    
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Merge branch 'master' into LV2019    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Add Watchdog PV-Monitoring and BMIL-FPGA-SW-Watchdog.    
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Recompile FPGA Version 2018062001.    
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Merge master with HBDev, UTCS Release 0.1.0.0.  
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Add Interval measurement; Use Range at leading edge of macro pulse (FPGA stuff not yet finished.)    
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Recompile FPGA Version 2018062001.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Prepare for build with Pyrometerintegration and target wheel interlock.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Add pressure Unit.vi, Msgs etc. and extend GUi (+cosmetics).    
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Merge branch 'master' into LV2019    
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Adjust SV.libs    
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Add Watchdog PV-Monitoring and BMIL-FPGA-SW-Watchdog.    
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Add Interval measurement; Use Range at leading edge of macro pulse (FPGA stuff not yet finished.)    
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Add Interval measurement; Use Range at leading edge of macro pulse (FPGA stuff not yet finished.)    
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Recompile FPGA 2018062100 with moved IOs.    
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Prepare for build with Pyrometerintegration and target wheel interlock.    
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Open and save.    
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Merge branch 'master' into LV2019    
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Add IGA140 Pyrometer    
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Reorganize projects virtual structure a bit and set new version number of exe to 0.2.0.0.    
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Update submodule CSPP Utilities.PVScaler Msg    
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Add Interlock SecKey.    
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Update submodules; Compile FPGA for PXI-7842R    
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Adjust SV.libs    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Prepare for build with Pyrometerintegration and target wheel interlock.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Recompile FPGA Version 2018062001.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Add targetwheel interlock; sparate code from some VIs; update some submodules.    
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Add Interval measurement; Use Range at leading edge of macro pulse (FPGA stuff not yet finished.)    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Recompile FPGA Version 2018062001.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Add Interval measurement; Use Range at leading edge of macro pulse (FPGA stuff not yet finished.)    
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Recompile FPGA Version 2018062001.    
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Add Interval measurement; Use Range at leading edge of macro pulse (FPGA stuff not yet finished.)    
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Recompile FPGA Version 2018062001.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Update submodules; adopt to CSPP_Core modifications; add Watchdog to MainGUI.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Add targetwheel interlock; sparate code from some VIs; update some submodules.    
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Merge branch 'master' into LV2019    
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Prepare for build with Pyrometerintegration and target wheel interlock.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Recompile FPGA Version 2018062001.    
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Adjust SV.libs    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Recompile FPGA Version 2018062001.    
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Add Interval measurement; Use Range at leading edge of macro pulse (FPGA stuff not yet finished.)    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Prepare for build with Pyrometerintegration and target wheel interlock.    
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Prepare for build with Pyrometerintegration and target wheel interlock.    
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Reorganize projects virtual structure a bit and set new version number of exe to 0.2.0.0.    
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Open and save.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Adjust SV.libs    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Prepare for build with Pyrometerintegration and target wheel interlock.    
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Add targetwheel interlock; sparate code from some VIs; update some submodules.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Update submodule CSPP Utilities.PVScaler Msg    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Update submodules; adopt to CSPP_Core modifications; add Watchdog to MainGUI.    
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Add Interval measurement; Use Range at leading edge of macro pulse (FPGA stuff not yet finished.)    
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Add targetwheel interlock; sparate code from some VIs; update some submodules.    
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Prepare for build with Pyrometerintegration and target wheel interlock.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Update submodule CSPP Utilities.PVScaler Msg    
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Add Interval measurement; Use Range at leading edge of macro pulse (FPGA stuff not yet finished.)    
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Update submodule CSPP Utilities.PVScaler Msg    
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Update submodule CSPP Utilities.PVScaler Msg    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Add pressure Unit.vi, Msgs etc. and extend GUi (+cosmetics).    
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Recompile FPGA 2018062100 with moved IOs.    
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Add Interval measurement; Use Range at leading edge of macro pulse (FPGA stuff not yet finished.)    
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Recompile FPGA 2018062100 with moved IOs.    
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Update submodule CSPP Utilities.PVScaler Msg    
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Add Interval measurement; Use Range at leading edge of macro pulse (FPGA stuff not yet finished.)    
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Open and save.    
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Update submodules: Add publishing of local ActorList and distributed monitoring.    
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Adjust SV.libs    
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Merge master with HBDev, UTCS Release 0.1.0.0.  
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Recompile FPGA Version 2018062001.    
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845 
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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Merge master with HBDev, UTCS Release 0.1.0.0.  
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Recompile FPGA Version 2018062001.    
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849 
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Merge master with HBDev, UTCS Release 0.1.0.0.  
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Open and save.    
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Merge master with HBDev, UTCS Release 0.1.0.0.  
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Modfiy SV alarm conditions; modify upper entry limit for quadrupole currents.    
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854 
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Merge master with HBDev, UTCS Release 0.1.0.0.  
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Add Interval measurement; Use Range at leading edge of macro pulse (FPGA stuff not yet finished.)    
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865