Commit 181ebf35 authored by Holger Brand's avatar Holger Brand
Browse files

Fix Dipole_IMin (wrong FPGA element was selected); make naming in Initialize...

Fix Dipole_IMin (wrong FPGA element was selected); make naming in Initialize Attributes and ini-file consitent.
parent 15656128
......@@ -403,7 +403,7 @@ UTCS_BMIL:UTCS_BCIL.Enable-MP-Generation=False
UTCS_BMIL:UTCS_BCIL.MP-Width=5.0E-3
UTCS_BMIL:UTCS_BCIL.MP-Frequency=50.
UTCS_BMIL:UTCS_BCIL.Enable-IL-Dipole-F=True
UTCS_BMIL:UTCS_BCIL.Enable-IL-Dipole_V=True
UTCS_BMIL:UTCS_BCIL.Enable-IL-Dipole-V=True
UTCS_BMIL:UTCS_BCIL.Enable-IL-Q=True
UTCS_BMIL:UTCS_BCIL.Enable-IL-RatTrap=True
UTCS_BMIL:UTCS_BCIL.Enable-IL-Pyrometer=True
......@@ -421,7 +421,7 @@ UTCS_BMIL:UTCS_BCIL.MaxFileTime=3600
UTCS_BMIL:UTCS_BCIL.Dipole-I2F-Gain=0.4559
UTCS_BMIL:UTCS_BCIL.Dipole-I2F-Offset=9.441
UTCS_BMIL:UTCS_BCIL.Dipole-F2I-Gain=2.1746
UTCS_BMIL:UTCS_BCIL.Dipole-F2I_Offset=-15.128
UTCS_BMIL:UTCS_BCIL.Dipole-F2I-Offset=-15.128
UTCS_BMIL:UTCS_BCIL.Dipole-IMax=0
UTCS_BMIL:UTCS_BCIL.Dipole-IMin=0
UTCS_BMIL:UTCS_BCIL.Dipole-I2V-Calibration="0.0,0.013333"
......
......@@ -403,7 +403,7 @@ UTCS_BMIL:UTCS_BCIL.Enable-MP-Generation=False
UTCS_BMIL:UTCS_BCIL.MP-Width=5.0E-3
UTCS_BMIL:UTCS_BCIL.MP-Frequency=50.
UTCS_BMIL:UTCS_BCIL.Enable-IL-Dipole-F=True
UTCS_BMIL:UTCS_BCIL.Enable-IL-Dipole_V=True
UTCS_BMIL:UTCS_BCIL.Enable-IL-Dipole-V=True
UTCS_BMIL:UTCS_BCIL.Enable-IL-Q=True
UTCS_BMIL:UTCS_BCIL.Enable-IL-RatTrap=True
UTCS_BMIL:UTCS_BCIL.Enable-IL-Pyrometer=True
......@@ -421,7 +421,7 @@ UTCS_BMIL:UTCS_BCIL.MaxFileTime=3600
UTCS_BMIL:UTCS_BCIL.Dipole-I2F-Gain=0.4559
UTCS_BMIL:UTCS_BCIL.Dipole-I2F-Offset=9.441
UTCS_BMIL:UTCS_BCIL.Dipole-F2I-Gain=2.1746
UTCS_BMIL:UTCS_BCIL.Dipole-F2I_Offset=-15.128
UTCS_BMIL:UTCS_BCIL.Dipole-F2I-Offset=-15.128
UTCS_BMIL:UTCS_BCIL.Dipole-IMax=0
UTCS_BMIL:UTCS_BCIL.Dipole-IMin=0
UTCS_BMIL:UTCS_BCIL.Dipole-I2V-Calibration="0.0,0.013333"
......
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