Commits · 4c80b7503797e73b71f2da48fa4f1ecbe482760f · EE-LV / CSPP / TASCA / UTCS

27 Jan, 2020 1 commit
- Build app & installer · 4c80b750
  Holger Brand authored Jan 27, 2020
  
  4c80b750
21 Jan, 2020 1 commit
- Fix Dipole_IMin (wrong FPGA element was selected); make naming in Initialize... · 181ebf35
  Holger Brand authored Jan 21, 2020
```
Fix Dipole_IMin (wrong FPGA element was selected); make naming in Initialize Attributes and ini-file consitent.
```
  181ebf35
16 Jan, 2020 1 commit
- Add dipole current measurement via analog signal in FPGA and UTCS. · c33b6ac3
  Holger Brand authored Jan 16, 2020
  
  c33b6ac3
29 Apr, 2019 1 commit
- Add Watchdog PV-Monitoring and BMIL-FPGA-SW-Watchdog. · 28150802
  Holger Brand authored Apr 29, 2019
  
  28150802
24 Apr, 2019 1 commit
- Rename VI with respect to modifications in CSPP_Core. · 1ae13964
  Holger Brand authored Apr 24, 2019
  
  1ae13964