Commits · 63a3fea9ffa600744a6b8f59e8421cd30e70749d · EE-LV / CSPP / TASCA / UTCS

25 Oct, 2017 1 commit
- Add MKS647C GUI actor., update CSPP_Core · 63a3fea9
  Holger Brand authored Oct 25, 2017
  
  63a3fea9
11 Oct, 2017 1 commit
- Update submodules · 6cb6cd32
  Holger Brand authored Oct 11, 2017
  
  6cb6cd32
10 Oct, 2017 1 commit
- Modifications during commissioning of MKS647C. · 677c60f8
  Holger Brand authored Oct 10, 2017
  
  677c60f8
22 Sep, 2017 1 commit
- Saving BMIL-Data to TDMS works. · 196cd44a
  Holger Brand authored Sep 22, 2017
  
  196cd44a
18 Sep, 2017 1 commit
- Add Submodule BNT_TDMS; update CSPP_DSC · 2276c6a8
  Holger Brand authored Sep 18, 2017
  
  2276c6a8
14 Sep, 2017 1 commit
- Add DMA transfer to host, Ad Z-scaling · a9bcb663
  Holger Brand authored Sep 14, 2017
  
  a9bcb663
12 Sep, 2017 2 commits
- Improve PVProxy · 9e45c43d
  Holger Brand authored Sep 12, 2017
  
  9e45c43d
- Add configuration parameters; Add enable trafor signal generation. add and... · 1989c716
  Holger Brand authored Sep 12, 2017
```
Add configuration parameters; Add enable trafor signal generation. add and rename some more actions and corresponding Msg classes.
```
  1989c716
08 Sep, 2017 1 commit
- Add MacroPulse Length interlock; convert MP-Extrema to Unit:s. · 663312e0
  Holger Brand authored Sep 08, 2017
  
  663312e0
07 Sep, 2017 3 commits
- Add Magnet & Pyrometer Interlocks · 2de58c26
  Holger Brand authored Sep 07, 2017
  
  2de58c26
- Scale current to A and Det-Rate to Hz in FPGA. · 9dd90ef1
  Holger Brand authored Sep 07, 2017
  
  9dd90ef1
- FPGA-VI work fine. Add Host DMA-Start/Stop - no DMA readout yet. · 44f7f6de
  Holger Brand authored Sep 07, 2017
  
  44f7f6de
06 Sep, 2017 1 commit
- Add Trafo-Signal generation. Scale to C and A. · 8cd392b6
  Holger Brand authored Sep 06, 2017
  
  8cd392b6
05 Sep, 2017 1 commit
- Recreate some Msgs; Actor is now really stopping. Update CSPP_Core · 2544a864
  Holger Brand authored Sep 05, 2017
  
  2544a864
04 Sep, 2017 1 commit
- Add missing Msgs for FPGA commands. · 5b3d09e6
  Holger Brand authored Sep 04, 2017
  
  5b3d09e6
01 Sep, 2017 3 commits
- Add some MP Msgs · f401180b
  Holger Brand authored Sep 01, 2017
  
  f401180b
- Update submodule · da3495db
  Holger Brand authored Sep 01, 2017
  
  da3495db
- Switch to CSPP master branches in submodules · bcd7a83e
  Holger Brand authored Sep 01, 2017
  
  bcd7a83e
31 Aug, 2017 3 commits
- Switch back to master branch · d4ea55db
  Holger Brand authored Aug 31, 2017
  
  d4ea55db
- Change remotes to ssh access. · 4dfe2159
  Holger Brand authored Aug 31, 2017
  
  4dfe2159
- Add UTCS Beam Monitor & Interlock class as interface for FPGA; polling implemented; no actions. · 8d7927a2
  Holger Brand authored Aug 31, 2017
  
  8d7927a2
15 Aug, 2017 1 commit
- Cosmetics · 5118c90b
  Holger Brand authored Aug 15, 2017
  
  5118c90b
11 Aug, 2017 2 commits
- Add FPGA Actor class · 3e91e1b3
  Holger Brand authored Aug 11, 2017
  
  3e91e1b3
- Add Detector Rate, recompile; Remove PXI-7811R: It's too small. · 8dd657e1
  Holger Brand authored Aug 11, 2017
  
  8dd657e1
10 Aug, 2017 3 commits
- Rename some FPGA-IOs on sbRIO; recompile all. · 95624f17
  Holger Brand authored Aug 10, 2017
  
  95624f17
- Add Fan-Outs and PXI-FPGA Targets and recompile. · 06545c73
  Holger Brand authored Aug 10, 2017
  
  06545c73
- Use U64 Counter istead of Sgl. · eb667ecb
  Holger Brand authored Aug 10, 2017
  
  eb667ecb
09 Aug, 2017 2 commits
- Add Test VI to check Sgl precision sum. · 13e6043f
  Holger Brand authored Aug 09, 2017
  
  13e6043f
- FPGA-VI ready for test with real signals. · 40714af1
  Holger Brand authored Aug 09, 2017
  
  40714af1
07 Aug, 2017 1 commit
- Trafo charge & current measurement seems to work. · f6f7a182
  Holger Brand authored Aug 07, 2017
  
  f6f7a182
04 Aug, 2017 3 commits
- Prepare Charge & Current measurement. · b8ad081e
  Holger Brand authored Aug 04, 2017
  
  b8ad081e
- Exchange Cases in U32 Extrema.vi; recompile. · e16bfeb6
  Holger Brand authored Aug 04, 2017
  
  e16bfeb6
- Add sbRIO and FPGA-VI to generate and measure Marco Pulse. · d1fb0a97
  Holger Brand authored Aug 04, 2017
  
  d1fb0a97
03 Aug, 2017 1 commit
- Update submodules · 5f77b6b4
  Holger Brand authored Aug 03, 2017
  
  5f77b6b4
01 Aug, 2017 1 commit
- Save automatic changes · 0c61a773
  Holger Brand authored Aug 01, 2017
  
  0c61a773
31 Jul, 2017 1 commit
- Repair after renaming CSPP. · 46b04b1f
  Holger Brand authored Jul 31, 2017
  
  46b04b1f
21 Jul, 2017 1 commit
- Mass compile; separate object code from VI. · 57f46478
  Holger Brand authored Jul 21, 2017
  
  57f46478
20 Jul, 2017 2 commits
- Mass complie with LV2017 and build UTCS_COMPACT.exe 0.1.0.0 · 94dbad4b
  Holger Brand authored Jul 20, 2017
  
  94dbad4b
- Relocate submodule URLs (github -> git.gsi.de) · 20204c40
  Holger Brand authored Jul 20, 2017
  
  20204c40
10 Jul, 2017 1 commit
- Relocate submodule URL · 765b37a6
  Holger Brand authored Jul 10, 2017
  
  765b37a6