Commits · 929a465d8613c27c88325f2d3f8247e0bae1b0c0 · EE-LV / CSPP / TASCA / UTCS

11 Feb, 2020 1 commit
- Rebuild App & Installer · 929a465d
  Holger Brand authored Feb 11, 2020
  
  929a465d
07 Feb, 2020 2 commits
- Update submodules and repair with respect to changes in CSPP_Core · 041e1e50
  Holger Brand authored Feb 07, 2020
  
  041e1e50
- Rebuild App & Installer · b66e0885
  Holger Brand authored Feb 07, 2020
  
  b66e0885
06 Feb, 2020 1 commit
- Update submodules; Modify VI descriptions; add Ni Web-Server confiburation. · da0e705b
  Holger Brand authored Feb 06, 2020
  
  da0e705b
27 Jan, 2020 5 commits
- Scale Dipole IMax / IMin accordingly · c27110cc
  Holger Brand authored Jan 27, 2020
  
  c27110cc
- Scale FPGA AI_0 to volt before scaling to ampere. · a11dbf02
  Holger Brand authored Jan 27, 2020
  
  a11dbf02
- FPGA AI_0 used for dipole current measurement need to be scaled for raw value... · 435d5288
  Holger Brand authored Jan 27, 2020
```
FPGA AI_0 used for dipole current measurement need to be scaled for raw value to volt before scaling to ampere.
```
  435d5288
- Configuration with SV all multiple writer to avoid conflicts with OperationGUI for now. · 0490a335
  Holger Brand authored Jan 27, 2020
  
  0490a335
- Build app & installer · 4c80b750
  Holger Brand authored Jan 27, 2020
  
  4c80b750
22 Jan, 2020 1 commit
- Fix handling of Dipole-V mean interlock propagation. · db2505e5
  Holger Brand authored Jan 22, 2020
  
  db2505e5
21 Jan, 2020 1 commit
- Entry in ini file fixed. FPGA need more improvements. · 228359fa
  Jaeger authored Jan 21, 2020
  
  228359fa
20 Jan, 2020 2 commits
- Build app and installer · 15656128
  Holger Brand authored Jan 20, 2020
  
  15656128
- Adapt to modifications in CSPP_Core · 3e3252b5
  Holger Brand authored Jan 20, 2020
  
  3e3252b5
17 Jan, 2020 2 commits
- FPGA Bugfix: analog dipole current interlock goes to indicator. Interlock... · f7313f52
  Holger Brand authored Jan 17, 2020
```
FPGA Bugfix: analog dipole current interlock goes to indicator. Interlock enable is checked in SCTL.
Build application 1.2.0.9; take UTCS.ini from KCPC080.
```
  f7313f52
- Build app and installer · 9cecb07c
  Holger Brand authored Jan 17, 2020
  
  9cecb07c
16 Jan, 2020 2 commits
- Add DSCAlarmViewer filter options to ini-file; Start adjusting alarm priorities. · 16fc990c
  Holger Brand authored Jan 16, 2020
  
  16fc990c
- Add dipole current measurement via analog signal in FPGA and UTCS. · c33b6ac3
  Holger Brand authored Jan 16, 2020
  
  c33b6ac3
13 Jan, 2020 2 commits
- Improve error handling. Adapt error severity. · 4f25996f
  Holger Brand authored Jan 13, 2020
  
  4f25996f
- Send BMIL enqueuer to AlarmHandler when BMIL becomes relaunched. · f350760e
  Holger Brand authored Jan 13, 2020
  
  f350760e
10 Jan, 2020 2 commits
- Update SV.libs; UTCS_AlarmHandler: improve BMIL enqueuer handling. · c97538a1
  Holger Brand authored Jan 10, 2020
  
  c97538a1
- Add to UTCS_AlarmHandler: Settings, Enable DipoleCurrent alarm action. · 85f043dc
  Holger Brand authored Jan 10, 2020
  
  85f043dc
09 Jan, 2020 1 commit
- Update CSPP_Core: Prepare UTCS_AlarmHandler · 7b12dc1c
  Holger Brand authored Jan 09, 2020
  
  7b12dc1c
08 Jan, 2020 3 commits
- Build UTCS app and installer. · 1a380029
  Holger Brand authored Jan 08, 2020
  
  1a380029
- Update SV.libs · fbd48211
  Jaeger authored Jan 08, 2020
```
Signed-off-by: Jaeger <she_oper@gsi.de>
```
  fbd48211
- New FPGA works with watchdog handling. · 06f222db
  Jaeger authored Jan 08, 2020
```
Signed-off-by: Jaeger <she_oper@gsi.de>
```
  06f222db
07 Jan, 2020 3 commits
- RecompileBMIL-FPGA and check watchdog behavior. It works, but HW signignal... · 380ccb34
  Jaeger authored Jan 07, 2020
```
RecompileBMIL-FPGA and check watchdog behavior. It works, but HW signignal connection need to be checked!

Signed-off-by: Holger Brand <H.Brand@gsi.de>
```
  380ccb34
- Move items from dependencies to project. · 5eea3031
  Holger Brand authored Jan 07, 2020
  
  5eea3031
- Update CSPP submodules · 7b9deeb5
  Holger Brand authored Jan 07, 2020
  
  7b9deeb5
18 Dec, 2019 1 commit
- Update submodules; Compile FPGA for PXI-7842R · 9c7dceef
  Holger Brand authored Dec 18, 2019
  
  9c7dceef
18 Jul, 2019 1 commit
- Rebuild FPGA, application and installer now with ACC-Interface. · ba2d9f53
  Holger Brand authored Jul 18, 2019
  
  ba2d9f53
12 Jul, 2019 1 commit
- Rebuild UTCS · 3e790163
  Holger Brand authored Jul 12, 2019
  
  3e790163
23 May, 2019 1 commit
- Correct description of interlock reason.; rearrange project, rebuild app & installer. · 311b4f7b
  Holger Brand authored May 23, 2019
  
  311b4f7b
22 May, 2019 2 commits
- Adjust SV.libs · 24419379
  Holger Brand authored May 22, 2019
  
  24419379
- Update submodules. · 688661a1
  Holger Brand authored May 22, 2019
  
  688661a1
20 May, 2019 1 commit
- Update submodules · 79605924
  Holger Brand authored May 20, 2019
  
  79605924
29 Apr, 2019 1 commit
- Add Watchdog PV-Monitoring and BMIL-FPGA-SW-Watchdog. · 28150802
  Holger Brand authored Apr 29, 2019
  
  28150802
24 Apr, 2019 1 commit
- Add Handle WatchdogPollingStopped Msg; update submodules · 8364a3e8
  Holger Brand authored Apr 24, 2019
  
  8364a3e8
23 Apr, 2019 1 commit
- Update submodules; adopt to CSPP_Core modifications; add Watchdog to MainGUI. · 28a6f9e3
  Holger Brand authored Apr 23, 2019
  
  28a6f9e3
06 Mar, 2019 1 commit

Recompile FPGA with Counter input assigned to Connector1/DIO1 (Connector1/DIO0... · c5ac4015

Holger Brand authored Mar 06, 2019

Recompile FPGA with Counter input assigned to Connector1/DIO1 (Connector1/DIO0 is defect due to emergency power break)
Update description of interlock reason indicator in other VIs.

c5ac4015

05 Mar, 2019 1 commit
- Correct SV name in event case Enable-Targetwheel-IL · 6548230a
  Holger Brand authored Mar 05, 2019
  
  6548230a