Fix Dipole_IMin (wrong FPGA element was selected); make naming in Initialize Attributes and ini-file consitent.

FPGA Bugfix: analog dipole current interlock goes to indicator. Interlock enable is checked in SCTL.
Build application 1.2.0.9; take UTCS.ini from KCPC080.

Signed-off-by: Jaeger <she_oper@gsi.de>

Signed-off-by: Jaeger <she_oper@gsi.de>

RecompileBMIL-FPGA and check watchdog behavior. It works, but HW signignal connection need to be checked!

Signed-off-by: Holger Brand <H.Brand@gsi.de>

# Conflicts:
#	UTCS_HB.lvproj

Open with LV2019, but don't save. LV2019 support for PXI-7813R seems to be stopped due to ended support of Xilinx VIRTEX II in new version ofVivando Tools .