Commits · db2505e5f0f7e51295614ccc7387d2f1b92c6267 · EE-LV / CSPP / TASCA / UTCS

22 Jan, 2020 1 commit
- Fix handling of Dipole-V mean interlock propagation. · db2505e5
  Holger Brand authored Jan 22, 2020
  
  db2505e5
21 Jan, 2020 1 commit
- Entry in ini file fixed. FPGA need more improvements. · 228359fa
  Jaeger authored Jan 21, 2020
  
  228359fa
17 Jan, 2020 1 commit

FPGA Bugfix: analog dipole current interlock goes to indicator. Interlock... · f7313f52

Holger Brand authored Jan 17, 2020

FPGA Bugfix: analog dipole current interlock goes to indicator. Interlock enable is checked in SCTL.
Build application 1.2.0.9; take UTCS.ini from KCPC080.

f7313f52

16 Jan, 2020 1 commit
- Add dipole current measurement via analog signal in FPGA and UTCS. · c33b6ac3
  Holger Brand authored Jan 16, 2020
  
  c33b6ac3
08 Jan, 2020 1 commit
- New FPGA works with watchdog handling. · 06f222db
  Jaeger authored Jan 08, 2020
```
Signed-off-by: Jaeger <she_oper@gsi.de>
```
  06f222db
07 Jan, 2020 1 commit

RecompileBMIL-FPGA and check watchdog behavior. It works, but HW signignal... · 380ccb34

Jaeger authored Jan 07, 2020


RecompileBMIL-FPGA and check watchdog behavior. It works, but HW signignal connection need to be checked!

Signed-off-by: Holger Brand <H.Brand@gsi.de>

380ccb34

18 Dec, 2019 1 commit
- Update submodules; Compile FPGA for PXI-7842R · 9c7dceef
  Holger Brand authored Dec 18, 2019
  
  9c7dceef
18 Jul, 2019 1 commit
- Rebuild FPGA, application and installer now with ACC-Interface. · ba2d9f53
  Holger Brand authored Jul 18, 2019
  
  ba2d9f53