Commits · db2505e5f0f7e51295614ccc7387d2f1b92c6267 · EE-LV / CSPP / TASCA / UTCS

22 Jan, 2020 1 commit
- Fix handling of Dipole-V mean interlock propagation. · db2505e5
  Holger Brand authored Jan 22, 2020
  
  db2505e5
29 Apr, 2019 1 commit
- Add Watchdog PV-Monitoring and BMIL-FPGA-SW-Watchdog. · 28150802
  Holger Brand authored Apr 29, 2019
  
  28150802
20 Feb, 2019 1 commit
- Add targetwheel interlock; sparate code from some VIs; update some submodules. · 06f08761
  Holger Brand authored Feb 20, 2019
  
  06f08761
08 Nov, 2018 1 commit
- Repair error with new messages; updat submodules. · 7e34f6e4
  Holger Brand authored Nov 08, 2018
  
  7e34f6e4
06 Jul, 2018 1 commit
- Bugfix in FPGA for Interval mode (FPGA rebuild). Bugfixes in BeamControlGUI... · 68e4d6d4
  Helena May David authored Jul 06, 2018
```
Bugfix in FPGA for Interval mode (FPGA rebuild). Bugfixes in BeamControlGUI and GasGUI, and some general cosmetics.
```
  68e4d6d4
04 Jul, 2018 1 commit
- Add Interval measurement; Use Range at leading edge of macro pulse (FPGA stuff not yet finished.) · 7085824e
  Holger Brand authored Jul 04, 2018
  
  7085824e
20 Jun, 2018 1 commit
- Add Dipole Interlock to FPGA and BMIL actor. · 0f2a5cc1
  Holger Brand authored Jun 20, 2018
  
  0f2a5cc1
18 Jun, 2018 1 commit
- Use positive logic for Chopper/Interlock/Inhibt output sinals. Add Auxilliary Interlock inputs. · ea2231e3
  Holger Brand authored Jun 18, 2018
  
  ea2231e3
15 Jun, 2018 1 commit
- Assign FPGA high frequency signals in and out to a second line driver. Rebuild UTCS.exe. · cb2fa709
  Holger Brand authored Jun 15, 2018
  
  cb2fa709
10 Aug, 2017 1 commit
- Add Fan-Outs and PXI-FPGA Targets and recompile. · 06545c73
  Holger Brand authored Aug 10, 2017
  
  06545c73
09 Aug, 2017 1 commit
- FPGA-VI ready for test with real signals. · 40714af1
  Holger Brand authored Aug 09, 2017
  
  40714af1
04 Aug, 2017 1 commit
- Add sbRIO and FPGA-VI to generate and measure Marco Pulse. · d1fb0a97
  Holger Brand authored Aug 04, 2017
  
  d1fb0a97