Commits · db2505e5f0f7e51295614ccc7387d2f1b92c6267 · EE-LV / CSPP / TASCA / UTCS

22 Jan, 2020 1 commit
- Fix handling of Dipole-V mean interlock propagation. · db2505e5
  Holger Brand authored Jan 22, 2020
  
  db2505e5
17 Jan, 2020 1 commit

FPGA Bugfix: analog dipole current interlock goes to indicator. Interlock... · f7313f52

Holger Brand authored Jan 17, 2020

FPGA Bugfix: analog dipole current interlock goes to indicator. Interlock enable is checked in SCTL.
Build application 1.2.0.9; take UTCS.ini from KCPC080.

f7313f52

16 Jan, 2020 1 commit
- Add dipole current measurement via analog signal in FPGA and UTCS. · c33b6ac3
  Holger Brand authored Jan 16, 2020
  
  c33b6ac3
08 Jan, 2020 1 commit
- New FPGA works with watchdog handling. · 06f222db
  Jaeger authored Jan 08, 2020
```
Signed-off-by: Jaeger <she_oper@gsi.de>
```
  06f222db
18 Dec, 2019 2 commits
- Check FPGA Bitfile-Ref; prepare Acc-Interface on SHCPC005; add MU1-Dipole Power Supply SV. · bb2d9e07
  r.a.cantemir authored Dec 18, 2019
  
  bb2d9e07
- Update submodules; Compile FPGA for PXI-7842R · 9c7dceef
  Holger Brand authored Dec 18, 2019
  
  9c7dceef
18 Jul, 2019 1 commit
- Rebuild FPGA, application and installer now with ACC-Interface. · ba2d9f53
  Holger Brand authored Jul 18, 2019
  
  ba2d9f53
29 Apr, 2019 1 commit
- Add Watchdog PV-Monitoring and BMIL-FPGA-SW-Watchdog. · 28150802
  Holger Brand authored Apr 29, 2019
  
  28150802
20 Feb, 2019 1 commit
- Add targetwheel interlock; sparate code from some VIs; update some submodules. · 06f08761
  Holger Brand authored Feb 20, 2019
  
  06f08761
12 Nov, 2018 1 commit
- Rebuild with DAQmx bugfix. · 492fccd1
  Holger Brand authored Nov 12, 2018
  
  492fccd1
05 Jul, 2018 1 commit
- Save FPGA reference; some fixes in BeamControlGUI. Build UTCS.exe · 782ba7a5
  Holger Brand authored Jul 05, 2018
  
  782ba7a5
20 Jun, 2018 1 commit
- Add Dipole Interlock to FPGA and BMIL actor. · 0f2a5cc1
  Holger Brand authored Jun 20, 2018
  
  0f2a5cc1
15 Jun, 2018 1 commit
- Assign FPGA high frequency signals in and out to a second line driver. Rebuild UTCS.exe. · cb2fa709
  Holger Brand authored Jun 15, 2018
  
  cb2fa709
18 May, 2018 1 commit
- Close #1 · 5e70b4a2
  Holger Brand authored May 18, 2018
  
  5e70b4a2
25 Apr, 2018 1 commit
- Update submodules; Remove BMIL.HW-Reset, reordering of FPGA-IO. Recompile FPGA... · c10c3a12
  Holger Brand authored Apr 25, 2018
```
Update submodules; Remove BMIL.HW-Reset, reordering of FPGA-IO. Recompile FPGA and UTMS.exe Version 0.2.0.3.
```
  c10c3a12
11 Apr, 2018 1 commit
- Merge master with HBDev, UTCS Release 0.1.0.0. · 9e2477af
  Holger Brand authored Apr 11, 2018
  
  9e2477af
14 Sep, 2017 1 commit
- Add DMA transfer to host, Ad Z-scaling · a9bcb663
  Holger Brand authored Sep 14, 2017
  
  a9bcb663
31 Aug, 2017 1 commit
- Add UTCS Beam Monitor & Interlock class as interface for FPGA; polling implemented; no actions. · 8d7927a2
  Holger Brand authored Aug 31, 2017
  
  8d7927a2