- 22 Jan, 2020 1 commit
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Holger Brand authored
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- 17 Jan, 2020 1 commit
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Holger Brand authored
FPGA Bugfix: analog dipole current interlock goes to indicator. Interlock enable is checked in SCTL. Build application 1.2.0.9; take UTCS.ini from KCPC080.
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- 16 Jan, 2020 1 commit
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Holger Brand authored
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- 08 Jan, 2020 1 commit
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Jaeger authoredSigned-off-by:
Jaeger <she_oper@gsi.de>
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- 07 Jan, 2020 1 commit
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Jaeger authored
RecompileBMIL-FPGA and check watchdog behavior. It works, but HW signignal connection need to be checked! Signed-off-by:
Holger Brand <H.Brand@gsi.de>
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- 18 Dec, 2019 1 commit
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Holger Brand authored
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- 18 Jul, 2019 1 commit
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Holger Brand authored
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- 29 Apr, 2019 1 commit
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Holger Brand authored
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- 20 Feb, 2019 1 commit
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Holger Brand authored
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- 12 Nov, 2018 2 commits
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Holger Brand authored
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Holger Brand authored
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- 05 Jul, 2018 1 commit
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Holger Brand authored
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- 20 Jun, 2018 1 commit
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Holger Brand authored
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- 18 Jun, 2018 1 commit
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Holger Brand authored
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- 15 Jun, 2018 1 commit
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Holger Brand authored
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- 18 May, 2018 1 commit
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Holger Brand authored
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- 23 Apr, 2018 1 commit
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Holger Brand authored
Recompile FPGA and UTCS.exe.
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- 11 Apr, 2018 1 commit
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Holger Brand authored
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- 14 Sep, 2017 1 commit
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Holger Brand authored
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- 12 Sep, 2017 1 commit
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Holger Brand authored
Add configuration parameters; Add enable trafor signal generation. add and rename some more actions and corresponding Msg classes.
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- 07 Sep, 2017 1 commit
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Holger Brand authored
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- 01 Sep, 2017 1 commit
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Holger Brand authored
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- 31 Aug, 2017 1 commit
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Holger Brand authored
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