FPGA Bugfix: analog dipole current interlock goes to indicator. Interlock enable is checked in SCTL.
Build application 1.2.0.9; take UTCS.ini from KCPC080.

Signed-off-by: Jaeger <she_oper@gsi.de>

RecompileBMIL-FPGA and check watchdog behavior. It works, but HW signignal connection need to be checked!

Signed-off-by: Holger Brand <H.Brand@gsi.de>

error in error handling; DMA buffer size, and flushing.

Signed-off-by: Holger Brand <H.Brand@gsi.de>

Update submodules; Remove BMIL.HW-Reset, reordering of FPGA-IO. Recompile FPGA and UTMS.exe Version 0.2.0.3.

Recompile FPGA and UTCS.exe.

Add configuration parameters; Add enable trafor signal generation. add and rename some more actions and corresponding Msg classes.