201310 100 false 10000 0 9 true false 3 true true false 0 My Computer/VI Server My Computer/VI Server true true false {070A363D-3DE9-4E42-A02F-720235056645}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=bool{0F3E4FA3-4263-4B9E-AA88-72D550CD4F50}"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"{7F04A6AE-C488-4C06-8E88-EA50100E44B5}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool{E0A337A3-11B3-4B27-BCED-E59580ACF523}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=bool{F9ABC913-AFE8-4BFB-88D5-CCB3DB60A2E3}Multiplier=2,000000;Divisor=1,000000PCI-7811R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPCI_7811RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End] 80MHzMultiplier=2,000000;Divisor=1,000000isActiveArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=boolMCSData"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"PCI-7811R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPCI_7811RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End]signalInputArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=boolstartTriggerArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool PCI-7811R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPCI_7811RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA 6 3 PCI-7811R 40 MHz Onboard Clock true NeverArbitrate NeverArbitrate 1 1 Auto /Connector1/DIO0 {7F04A6AE-C488-4C06-8E88-EA50100E44B5} NeverArbitrate NeverArbitrate 1 1 Auto /Connector1/DIO1 {070A363D-3DE9-4E42-A02F-720235056645} NeverArbitrate NeverArbitrate 1 1 Auto /Connector1/DIO2 {E0A337A3-11B3-4B27-BCED-E59580ACF523} {9E92B135-8C07-4C8A-8075-F89E0DE37CA1} 100 Clk40 50 40000000 50 40000000 40000000 250 40 MHz Onboard Clock false Clk40 false true 5 {F9ABC913-AFE8-4BFB-88D5-CCB3DB60A2E3} Multiplier=2,000000;Divisor=1,000000 1 false 2 40000000 Clk40Derived2x1 true 5 {070A363D-3DE9-4E42-A02F-720235056645}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=bool{0F3E4FA3-4263-4B9E-AA88-72D550CD4F50}"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"{7F04A6AE-C488-4C06-8E88-EA50100E44B5}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool{E0A337A3-11B3-4B27-BCED-E59580ACF523}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=bool{F9ABC913-AFE8-4BFB-88D5-CCB3DB60A2E3}Multiplier=2,000000;Divisor=1,000000PCI-7811R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPCI_7811RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End] 80MHzMultiplier=2,000000;Divisor=1,000000isActiveArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=boolMCSData"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"PCI-7811R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPCI_7811RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End]signalInputArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=boolstartTriggerArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool {924D4307-8F0D-452F-9D08-E9907F1C4D43} {070A363D-3DE9-4E42-A02F-720235056645}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=bool{0F3E4FA3-4263-4B9E-AA88-72D550CD4F50}"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"{7F04A6AE-C488-4C06-8E88-EA50100E44B5}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool{E0A337A3-11B3-4B27-BCED-E59580ACF523}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=bool{F9ABC913-AFE8-4BFB-88D5-CCB3DB60A2E3}Multiplier=2,000000;Divisor=1,000000PCI-7811R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPCI_7811RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End] 80MHzMultiplier=2,000000;Divisor=1,000000isActiveArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=boolMCSData"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"PCI-7811R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPCI_7811RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End]signalInputArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=boolstartTriggerArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool C:\User\Brand\LVP\Driver\NI-FPGA-MCS\FPGA Bitfiles\NI-FPGA-MCS.lvproj_PCI7811R_target.main.vi.lvbitx 16383 1 2 0 7 false "ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE" true true ##'!!A!!!!U!$E!Q`````Q2/97VF!!!+1!=&2'6Q>'A!.1$R!!!!!!!!!!%92GFG<V^%982B6(FQ:5.P<H2S<WQO9X2M!".!!AJ%982B)&>J:(2I!!!R!0%!!!!!!!!!!2*';7:P8U2J=G6D>'FP<CZD>'Q!&5!$$5:*2E^%;8*F9X2J<WY!-!$R!!!!!!!!!!%42GFG<V^*4V.U=G&U:7>Z,G.U<!!51!%,35]A5X2S982F:XE!%E!Q`````QB73%2-4G&N:1!!1!$RPAH!FA!!!!%:2GFG<V^"=G*0=(2J<WZT5X2S;7ZH,G.U<!!?1$$`````%&*F971A18*C)%^Q>'FP<H-!!%!!]<Y*Q*9!!!!"'5:J:G^@18*C4X"U;7^O=V.U=GFO:SZD>'Q!(E!Q`````R&8=GFU:3""=G)A4X"U;7^O=Q!L!0%!!!!!!!!!!2"';7:P8UVF<62Z='5O9X2M!"&!!AB315UA>(FQ:1!!%%!(#U2.13"$;'&O<G6M!!R!)1:8=GFU:4]!!!J!)16-<W.B<!"&!0'`[U5V!!!!!1Z';7:P8V.U982F,G.U<!!N1&!!$!!!!!%!!A!$!!1!"1!'!!=!#!!*!!I!#QJ';7:P)&.U982F!!!"!!Q!!!!(45.42'&U91!!0`]!"!!!!!!"!!!!-5V$5U2B>'&@-41U-DAV.DAR.D9S.4)S.$EZ/4%Q.$)Q-$%Q.D%W/$AR-T)R-45S-4-!!!!44X"U;7VJ?G5A2G^S)&.J<G>M:1!!!!2/<WZF!!)!!!!!!1!!!!!! true 12 {0F3E4FA3-4263-4B9E-AA88-72D550CD4F50} 2 false 2 16383 1 1 16383 2 1000800000000001000940070003553332000100000000000000000000 false target.main NI-FPGA-MCS.lvproj_PCI7811R_target.main.vi.lvbitx -1 false 0 0 1 0 false balanced default(noTiming) standard normal speed true true FPGA Bitfiles /C/User/Brand/LVP/Driver/NI-FPGA-MCS/FPGA Bitfiles/NI-FPGA-MCS.lvproj_PCI7811R_target.main.vi.lvbitx FPGA Bitfiles/NI-FPGA-MCS.lvproj_PCI7811R_target.main.vi.lvbitx /F/LVSCC/LV2012/GPL/instr.lib/NI-FPGA-MCS/NI-FPGA-MCS.lvproj true false true false PCI7811R /My Computer/PCI7811R/target.main.vi false target.state NI-FPGA-MCS_PCI7811R_target.state_qKO9cqFKBM8.lvbitx -1 false 0 0 1 0 false balanced default(noTiming) standard normal speed true true FPGA Bitfiles /F/LVSCC/LV2012/GPL/instr.lib/NI-FPGA-MCS/NI-FPGA-MCS.lvproj true false true false PCI7811R /My Computer/PCI7811R/target.state.ctl {404DBE7C-CAC6-4FE9-9A89-DFA145BA97A0}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool{560E8DC4-7EA0-4F73-A678-B25333BE4782}Multiplier=2,000000;Divisor=1,000000{66DA5740-6176-44AE-B419-75202825834A}"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"{F03FCD98-7D80-45A3-9ABB-8184402E8CB6}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=bool{F4507F0E-40E4-4D01-BEF6-642A6AA80BF5}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=boolPCI-7813R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPCI_7813RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End] 80MHzMultiplier=2,000000;Divisor=1,000000isActiveArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=boolMCSData"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"PCI-7813R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPCI_7813RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End]signalInputArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=boolstartTriggerArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool PCI-7813R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPCI_7813RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA 6 3 PCI-7813R 40 MHz Onboard Clock true NeverArbitrate NeverArbitrate 1 1 Auto /Connector1/DIO0 {404DBE7C-CAC6-4FE9-9A89-DFA145BA97A0} NeverArbitrate NeverArbitrate 1 1 Auto /Connector1/DIO1 {F03FCD98-7D80-45A3-9ABB-8184402E8CB6} NeverArbitrate NeverArbitrate 1 1 Auto /Connector1/DIO2 {F4507F0E-40E4-4D01-BEF6-642A6AA80BF5} {8C62E6DF-924F-41BE-A4B7-3FD0E0A2E727} 100 Clk40 50 40000000 50 40000000 40000000 250 40 MHz Onboard Clock false Clk40 false true 5 {560E8DC4-7EA0-4F73-A678-B25333BE4782} Multiplier=2,000000;Divisor=1,000000 1 false 2 40000000 Clk40Derived2x1 true 5 {404DBE7C-CAC6-4FE9-9A89-DFA145BA97A0}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool{560E8DC4-7EA0-4F73-A678-B25333BE4782}Multiplier=2,000000;Divisor=1,000000{66DA5740-6176-44AE-B419-75202825834A}"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"{F03FCD98-7D80-45A3-9ABB-8184402E8CB6}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=bool{F4507F0E-40E4-4D01-BEF6-642A6AA80BF5}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=boolPCI-7813R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPCI_7813RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End] 80MHzMultiplier=2,000000;Divisor=1,000000isActiveArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=boolMCSData"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"PCI-7813R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPCI_7813RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End]signalInputArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=boolstartTriggerArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool {404DBE7C-CAC6-4FE9-9A89-DFA145BA97A0}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool{560E8DC4-7EA0-4F73-A678-B25333BE4782}Multiplier=2,000000;Divisor=1,000000{66DA5740-6176-44AE-B419-75202825834A}"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"{F03FCD98-7D80-45A3-9ABB-8184402E8CB6}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=bool{F4507F0E-40E4-4D01-BEF6-642A6AA80BF5}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=boolPCI-7813R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPCI_7813RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End] 80MHzMultiplier=2,000000;Divisor=1,000000isActiveArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=boolMCSData"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"PCI-7813R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPCI_7813RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End]signalInputArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=boolstartTriggerArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool C:\User\Brand\LVP\Driver\NI-FPGA-MCS\FPGA Bitfiles\NI-FPGA-MCS_PCI7813R_target.main_V2lU0odS++g.lvbitx 16383 1 2 0 7 false "ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE" true true ##'!!A!!!!U!$E!Q`````Q2/97VF!!!+1!=&2'6Q>'A!.1$R!!!!!!!!!!%92GFG<V^%982B6(FQ:5.P<H2S<WQO9X2M!".!!AJ%982B)&>J:(2I!!!R!0%!!!!!!!!!!2*';7:P8U2J=G6D>'FP<CZD>'Q!&5!$$5:*2E^%;8*F9X2J<WY!-!$R!!!!!!!!!!%42GFG<V^*4V.U=G&U:7>Z,G.U<!!51!%,35]A5X2S982F:XE!%E!Q`````QB73%2-4G&N:1!!1!$RPAH!FA!!!!%:2GFG<V^"=G*0=(2J<WZT5X2S;7ZH,G.U<!!?1$$`````%&*F971A18*C)%^Q>'FP<H-!!%!!]<Y*Q*9!!!!"'5:J:G^@18*C4X"U;7^O=V.U=GFO:SZD>'Q!(E!Q`````R&8=GFU:3""=G)A4X"U;7^O=Q!L!0%!!!!!!!!!!2"';7:P8UVF<62Z='5O9X2M!"&!!AB315UA>(FQ:1!!%%!(#U2.13"$;'&O<G6M!!R!)1:8=GFU:4]!!!J!)16-<W.B<!"&!0'`[U5V!!!!!1Z';7:P8V.U982F,G.U<!!N1&!!$!!!!!%!!A!$!!1!"1!'!!=!#!!*!!I!#QJ';7:P)&.U982F!!!"!!Q!!!!(45.42'&U91!!0`]!"!!!!!!"!!!!-5V$5U2B>'&@-41U-DAV.DAR.D9S.4)S.$EZ/4%Q.$)Q-$%Q.D%W/$AR-T)R-45S-4-!!!!44X"U;7VJ?G5A2G^S)&.J<G>M:1!!!!2/<WZF!!)!!!!!!1!!!!!! true 12 {66DA5740-6176-44AE-B419-75202825834A} 2 false 2 16383 1 1 16383 2 1000800000000001000940070003553332000100000000000000000000 false target.main NI-FPGA-MCS_PCI7813R_target.main_MEWtB1no--0.lvbitx -1 false 0 0 1 0 false balanced default(noTiming) standard normal speed true true FPGA Bitfiles /C/User/Brand/LVP/Driver/NI-FPGA-MCS/FPGA Bitfiles/NI-FPGA-MCS_PCI7813R_target.main_V2lU0odS++g.lvbitx FPGA Bitfiles/NI-FPGA-MCS_PCI7813R_target.main_V2lU0odS++g.lvbitx /F/LVSCC/LV2012/GPL/instr.lib/NI-FPGA-MCS/NI-FPGA-MCS.lvproj true false true false PCI7813R /My Computer/PCI7813R/target.main.vi false target.state NI-FPGA-MCS_PCI7813R_target.state_-vcoqdWTOpg.lvbitx -1 false 0 0 1 0 false balanced default(noTiming) standard normal speed true true FPGA Bitfiles /F/LVSCC/LV2012/GPL/instr.lib/NI-FPGA-MCS/NI-FPGA-MCS.lvproj true false true false PCI7813R /My Computer/PCI7813R/target.state.ctl {25484C75-ADBE-42D9-904E-580B65039C3A}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=bool{3D09D767-C4AA-4080-9D8F-2C62E252C3A5}"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"{912D9BD2-79DA-4E3C-A214-79C28E1CA2BE}Multiplier=2,000000;Divisor=1,000000{97470424-2ADC-4631-B255-A54817BA89F2}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool{B216BEAA-6744-40D5-9B72-9F3AE7687012}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=boolPXI-7811R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPXI_7811RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End] 80MHzMultiplier=2,000000;Divisor=1,000000isActiveArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=boolMCSData"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"PXI-7811R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPXI_7811RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End]signalInputArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=boolstartTriggerArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool PXI-7811R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPXI_7811RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA 6 3 PXI-7811R 40 MHz Onboard Clock true NeverArbitrate NeverArbitrate 1 1 Auto /Connector1/DIO0 {97470424-2ADC-4631-B255-A54817BA89F2} NeverArbitrate NeverArbitrate 1 1 Auto /Connector1/DIO1 {25484C75-ADBE-42D9-904E-580B65039C3A} NeverArbitrate NeverArbitrate 1 1 Auto /Connector1/DIO2 {B216BEAA-6744-40D5-9B72-9F3AE7687012} {2D6784C7-2006-4485-9ABA-3E401564AB0C} 100 Clk40 50 40000000 50 40000000 40000000 250 40 MHz Onboard Clock false Clk40 false true 5 {912D9BD2-79DA-4E3C-A214-79C28E1CA2BE} Multiplier=2,000000;Divisor=1,000000 1 false 2 40000000 Clk40Derived2x1 true 5 {25484C75-ADBE-42D9-904E-580B65039C3A}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=bool{3D09D767-C4AA-4080-9D8F-2C62E252C3A5}"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"{912D9BD2-79DA-4E3C-A214-79C28E1CA2BE}Multiplier=2,000000;Divisor=1,000000{97470424-2ADC-4631-B255-A54817BA89F2}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool{B216BEAA-6744-40D5-9B72-9F3AE7687012}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=boolPXI-7811R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPXI_7811RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End] 80MHzMultiplier=2,000000;Divisor=1,000000isActiveArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=boolMCSData"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"PXI-7811R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPXI_7811RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End]signalInputArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=boolstartTriggerArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool {25484C75-ADBE-42D9-904E-580B65039C3A}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=bool{3D09D767-C4AA-4080-9D8F-2C62E252C3A5}"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"{912D9BD2-79DA-4E3C-A214-79C28E1CA2BE}Multiplier=2,000000;Divisor=1,000000{97470424-2ADC-4631-B255-A54817BA89F2}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool{B216BEAA-6744-40D5-9B72-9F3AE7687012}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=boolPXI-7811R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPXI_7811RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End] 80MHzMultiplier=2,000000;Divisor=1,000000isActiveArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=boolMCSData"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"PXI-7811R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPXI_7811RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End]signalInputArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=boolstartTriggerArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool C:\User\Brand\LVP\Driver\NI-FPGA-MCS\FPGA Bitfiles\NI-FPGA-MCS_PXI7811R_target.main_Qljf8GXxVkc.lvbitx 16383 1 2 0 7 false "ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE" true true ##'!!A!!!!U!$E!Q`````Q2/97VF!!!+1!=&2'6Q>'A!.1$R!!!!!!!!!!%92GFG<V^%982B6(FQ:5.P<H2S<WQO9X2M!".!!AJ%982B)&>J:(2I!!!R!0%!!!!!!!!!!2*';7:P8U2J=G6D>'FP<CZD>'Q!&5!$$5:*2E^%;8*F9X2J<WY!-!$R!!!!!!!!!!%42GFG<V^*4V.U=G&U:7>Z,G.U<!!51!%,35]A5X2S982F:XE!%E!Q`````QB73%2-4G&N:1!!1!$RPAH!FA!!!!%:2GFG<V^"=G*0=(2J<WZT5X2S;7ZH,G.U<!!?1$$`````%&*F971A18*C)%^Q>'FP<H-!!%!!]<Y*Q*9!!!!"'5:J:G^@18*C4X"U;7^O=V.U=GFO:SZD>'Q!(E!Q`````R&8=GFU:3""=G)A4X"U;7^O=Q!L!0%!!!!!!!!!!2"';7:P8UVF<62Z='5O9X2M!"&!!AB315UA>(FQ:1!!%%!(#U2.13"$;'&O<G6M!!R!)1:8=GFU:4]!!!J!)16-<W.B<!"&!0'`[U5V!!!!!1Z';7:P8V.U982F,G.U<!!N1&!!$!!!!!%!!A!$!!1!"1!'!!=!#!!*!!I!#QJ';7:P)&.U982F!!!"!!Q!!!!(45.42'&U91!!0`]!"!!!!!!"!!!!-5V$5U2B>'&@-41U-DAV.DAR.D9S.4)S.$EZ/4%Q.$)Q-$%Q.D%W/$AR-T)R-45S-4-!!!!44X"U;7VJ?G5A2G^S)&.J<G>M:1!!!!2/<WZF!!)!!!!!!1!!!!!! true 12 {3D09D767-C4AA-4080-9D8F-2C62E252C3A5} 2 false 2 16383 1 1 16383 2 1000800000000001000940070003553332000100000000000000000000 false target.main NI-FPGA-MCS_PXI7811R_target.main_gRMwIVJzCsI.lvbitx -1 false 0 0 1 0 false balanced default(noTiming) standard normal speed true true FPGA Bitfiles /C/User/Brand/LVP/Driver/NI-FPGA-MCS/FPGA Bitfiles/NI-FPGA-MCS_PXI7811R_target.main_Qljf8GXxVkc.lvbitx FPGA Bitfiles/NI-FPGA-MCS_PXI7811R_target.main_Qljf8GXxVkc.lvbitx /F/LVSCC/LV2012/GPL/instr.lib/NI-FPGA-MCS/NI-FPGA-MCS.lvproj true false true false PXI7811R /My Computer/PXI7811R/target.main.vi false target.state NI-FPGA-MCS_PXI7811R_target.state_75-Erol8ZnU.lvbitx -1 false 0 0 1 0 false balanced default(noTiming) standard normal speed true true FPGA Bitfiles /F/LVSCC/LV2012/GPL/instr.lib/NI-FPGA-MCS/NI-FPGA-MCS.lvproj true false true false PXI7811R /My Computer/PXI7811R/target.state.ctl {027AE26E-7C1E-49C0-886D-8A02F0FDD774}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=bool{1341636D-ACF7-4AE1-87D4-1BFFC72FB897}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=bool{A03E57D5-0637-4033-8444-22BA5B273DEE}"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"{BF2D7C76-D470-4DFD-B019-0B8247EF7AE0}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool{D85E00B3-84F2-4CBE-98FF-A2E5CFF87297}Multiplier=2,000000;Divisor=1,000000PXI-7813R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPXI_7813RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End] 80MHzMultiplier=2,000000;Divisor=1,000000isActiveArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=boolMCSData"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"PXI-7813R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPXI_7813RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End]signalInputArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=boolstartTriggerArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool PXI-7813R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPXI_7813RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA 6 3 PXI-7813R 40 MHz Onboard Clock true NeverArbitrate NeverArbitrate 1 1 Auto /Connector1/DIO0 {BF2D7C76-D470-4DFD-B019-0B8247EF7AE0} NeverArbitrate NeverArbitrate 1 1 Auto /Connector1/DIO1 {1341636D-ACF7-4AE1-87D4-1BFFC72FB897} NeverArbitrate NeverArbitrate 1 1 Auto /Connector1/DIO2 {027AE26E-7C1E-49C0-886D-8A02F0FDD774} {99B520DB-E9BF-40B9-B110-2007E2157FA7} 100 Clk40 50 40000000 50 40000000 40000000 250 40 MHz Onboard Clock false Clk40 false true 5 {D85E00B3-84F2-4CBE-98FF-A2E5CFF87297} Multiplier=2,000000;Divisor=1,000000 1 false 2 40000000 Clk40Derived2x1 true 5 {027AE26E-7C1E-49C0-886D-8A02F0FDD774}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=bool{1341636D-ACF7-4AE1-87D4-1BFFC72FB897}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=bool{A03E57D5-0637-4033-8444-22BA5B273DEE}"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"{BF2D7C76-D470-4DFD-B019-0B8247EF7AE0}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool{D85E00B3-84F2-4CBE-98FF-A2E5CFF87297}Multiplier=2,000000;Divisor=1,000000PXI-7813R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPXI_7813RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End] 80MHzMultiplier=2,000000;Divisor=1,000000isActiveArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=boolMCSData"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"PXI-7813R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPXI_7813RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End]signalInputArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=boolstartTriggerArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool {027AE26E-7C1E-49C0-886D-8A02F0FDD774}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=bool{1341636D-ACF7-4AE1-87D4-1BFFC72FB897}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=bool{A03E57D5-0637-4033-8444-22BA5B273DEE}"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"{BF2D7C76-D470-4DFD-B019-0B8247EF7AE0}ArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool{D85E00B3-84F2-4CBE-98FF-A2E5CFF87297}Multiplier=2,000000;Divisor=1,000000PXI-7813R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPXI_7813RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End] 80MHzMultiplier=2,000000;Divisor=1,000000isActiveArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO2;0;ReadMethodType=bool;WriteMethodType=boolMCSData"ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE"PXI-7813R/Clk40/falsefalseFPGA_EXECUTION_MODEFPGA_TARGETFPGA_TARGET_CLASSPXI_7813RFPGA_TARGET_FAMILYVIRTEX2TARGET_TYPEFPGA/[rSeriesConfig.Begin][rSeriesConfig.End]signalInputArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO1;0;ReadMethodType=bool;WriteMethodType=boolstartTriggerArbitrationForOutputData=NeverArbitrate;ArbitrationForOutputEnable=NeverArbitrate;NumberOfSyncRegistersForOutputData=1;NumberOfSyncRegistersForOutputEnable=1;NumberOfSyncRegistersForReadInProject=Auto;resource=/Connector1/DIO0;0;ReadMethodType=bool;WriteMethodType=bool C:\User\Brand\LVP\Driver\NI-FPGA-MCS\FPGA Bitfiles\NI-FPGA-MCS_PXI7813R_target.main_BDp84IoS+N0.lvbitx 16383 1 2 0 7 false "ControlLogic=0;NumberOfElements=16383;Type=2;ReadArbs=Arbitrate if Multiple Requestors Only;ElementsPerRead=1;WriteArbs=Never Arbitrate;ElementsPerWrite=1;Implementation=2;MCSData;DataType=1000800000000001000940070003553332000100000000000000000000;DisableOnOverflowUnderflow=FALSE" true true ##'!!A!!!!U!$E!Q`````Q2/97VF!!!+1!=&2'6Q>'A!.1$R!!!!!!!!!!%92GFG<V^%982B6(FQ:5.P<H2S<WQO9X2M!".!!AJ%982B)&>J:(2I!!!R!0%!!!!!!!!!!2*';7:P8U2J=G6D>'FP<CZD>'Q!&5!$$5:*2E^%;8*F9X2J<WY!-!$R!!!!!!!!!!%42GFG<V^*4V.U=G&U:7>Z,G.U<!!51!%,35]A5X2S982F:XE!%E!Q`````QB73%2-4G&N:1!!1!$RPAH!FA!!!!%:2GFG<V^"=G*0=(2J<WZT5X2S;7ZH,G.U<!!?1$$`````%&*F971A18*C)%^Q>'FP<H-!!%!!]<Y*Q*9!!!!"'5:J:G^@18*C4X"U;7^O=V.U=GFO:SZD>'Q!(E!Q`````R&8=GFU:3""=G)A4X"U;7^O=Q!L!0%!!!!!!!!!!2"';7:P8UVF<62Z='5O9X2M!"&!!AB315UA>(FQ:1!!%%!(#U2.13"$;'&O<G6M!!R!)1:8=GFU:4]!!!J!)16-<W.B<!"&!0'`[U5V!!!!!1Z';7:P8V.U982F,G.U<!!N1&!!$!!!!!%!!A!$!!1!"1!'!!=!#!!*!!I!#QJ';7:P)&.U982F!!!"!!Q!!!!(45.42'&U91!!0`]!"!!!!!!"!!!!-5V$5U2B>'&@-D1R/4-S.4%S-DAX.D9W-T=T.D%U.4%S-T)S-T%Y.4)Q-$AT-4AW.T!!!!!44X"U;7VJ?G5A2G^S)&.J<G>M:1!!!!2/<WZF!!)!!!!!!1!!!!!! true 12 {A03E57D5-0637-4033-8444-22BA5B273DEE} 2 false 2 16383 1 1 16383 2 1000800000000001000940070003553332000100000000000000000000 false target.main NI-FPGA-MCS_PXI7813R_target.main_L2pCBeM87V8.lvbitx -1 false 0 0 1 0 false balanced default(noTiming) standard normal speed true true FPGA Bitfiles /C/User/Brand/LVP/Driver/NI-FPGA-MCS/FPGA Bitfiles/NI-FPGA-MCS_PXI7813R_target.main_BDp84IoS+N0.lvbitx FPGA Bitfiles/NI-FPGA-MCS_PXI7813R_target.main_BDp84IoS+N0.lvbitx /F/LVSCC/LV2012/GPL/instr.lib/NI-FPGA-MCS/NI-FPGA-MCS.lvproj true false true false PXI7813R /My Computer/PXI7813R/target.main.vi false target.state NI-FPGA-MCS_PXI7813R_target.state_L5Idm66zIh8.lvbitx -1 false 0 0 1 0 false balanced default(noTiming) standard normal speed true true FPGA Bitfiles /F/LVSCC/LV2012/GPL/instr.lib/NI-FPGA-MCS/NI-FPGA-MCS.lvproj true false true false PXI7813R /My Computer/PXI7813R/target.state.ctl true {05F27247-CA34-40E4-8CDE-85D197C19853} {E6B183A5-B9FF-4E75-8ABE-66C9A830F22D} 8002 {07D56188-8B7B-4E1D-8E9A-E50E99F11FCE} applicationExample2 true true true ../builds/NI_AB_PROJECTNAME/applicationExample2 relativeToCommon true {756EF4DF-18A6-46EB-BA1A-633759304465} 1 applicationExample2.exe ../builds/NI_AB_PROJECTNAME/applicationExample2/applicationExample2.exe App Support Directory ../builds/NI_AB_PROJECTNAME/applicationExample2/data Destination Directory ../builds/NI_AB_PROJECTNAME/applicationExample2 3 true true true {75982FA4-6501-4FA8-983D-5AFB86B13BA6} Container 0 /My Computer/SimpleTest Container 0 /My Computer/driver/NI-FPGA-MCS_Driver.lvlib/public/data Container 0 /My Computer/driver/NI-FPGA-MCS_Driver.lvlib/public/utility Container 0 /My Computer/driver/NI-FPGA-MCS_Driver.lvlib/private Container 0 /My Computer/driver/NI-FPGA-MCS_Driver.lvlib/applicationExample2.vi TopLevel VI 0 /My Computer/typedefs Container 0 /My Computer/driver Container 0 /My Computer/driver/NI-FPGA-MCS_Driver.lvlib true Library 0 /My Computer/driver/NI-FPGA-MCS_Driver.lvlib/typedefs Container 0 /My Computer/driver/NI-FPGA-MCS_Driver.lvlib/public Container 0 /My Computer/driver/NI-FPGA-MCS_Driver.lvlib/public/initialization Container 0 /My Computer/driver/NI-FPGA-MCS_Driver.lvlib/public/configuration Container 0 /My Computer/driver/NI-FPGA-MCS_Driver.lvlib/public/actionStatus Container 14 GSI Darmstadt applicationExample2 Copyright © 2008 GSI Darmstadt applicationExample2 {4D05A22E-62CE-4AC4-9BAC-942178965207} applicationExample2.exe