diff --git a/src/optic_ports.rs b/src/optic_ports.rs index b19aaec2f68f060673068267b060c09335b00eae..cc711552d30c1ff5fbe5dea7d349e6bb1f9f0055 100644 --- a/src/optic_ports.rs +++ b/src/optic_ports.rs @@ -1,5 +1,5 @@ use crate::error::OpossumError; -use std::collections::HashSet; +use std::{collections::HashSet, fmt::Display}; /// Structure defining the optical ports (input / output terminals) of an [`OpticNode`](crate::optic_node::OpticNode). #[derive(Default, Debug, Clone)] @@ -57,6 +57,34 @@ impl OpticPorts { } } +impl Display for OpticPorts { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + writeln!(f, "inputs:").unwrap(); + if !&self.inputs.is_empty() { + let mut ports=self.inputs(); + ports.sort(); + for port in ports { + writeln!(f, " <{}>", port).unwrap(); + } + } else { + writeln!(f, " None").unwrap(); + } + writeln!(f, "output:").unwrap(); + if !&self.outputs.is_empty() { + let mut ports=self.outputs(); + ports.sort(); + for port in ports { + writeln!(f, " <{}>", port).unwrap(); + } + } else { + writeln!(f, " None").unwrap(); + } + if self.inverted { + writeln!(f, "ports are inverted").unwrap(); + } + Ok(()) + } +} #[cfg(test)] mod test { use crate::optic_ports::OpticPorts; @@ -151,4 +179,28 @@ mod test { ports.set_inverted(true); assert_eq!(ports.inverted(), true); } + #[test] + fn display_empty() { + let ports = OpticPorts::new(); + assert_eq!(ports.to_string(), "inputs:\n None\noutput:\n None\n".to_owned()); + } + #[test] + fn display_entries() { + let mut ports = OpticPorts::new(); + ports.add_input("test1").unwrap(); + ports.add_input("test2").unwrap(); + ports.add_output("test3").unwrap(); + ports.add_output("test4").unwrap(); + assert_eq!(ports.to_string(), "inputs:\n <test1>\n <test2>\noutput:\n <test3>\n <test4>\n".to_owned()); + } + #[test] + fn display_entries_inverted() { + let mut ports = OpticPorts::new(); + ports.add_input("test1").unwrap(); + ports.add_input("test2").unwrap(); + ports.add_output("test3").unwrap(); + ports.add_output("test4").unwrap(); + ports.set_inverted(true); + assert_eq!(ports.to_string(), "inputs:\n <test3>\n <test4>\noutput:\n <test1>\n <test2>\nports are inverted\n".to_owned()); + } }