From 403b2bca4a4767dcca401eab5c399b4990c60300 Mon Sep 17 00:00:00 2001
From: aschwinn <al.schwinn@gsi.de>
Date: Fri, 22 Sep 2017 16:42:02 +0200
Subject: [PATCH] #1 - Add support for direct IO communication, like CERN
already does - fixed remaining codegen bugs
---
.../xml/fesa/fesa_3_0_0/generateSourceCode.py | 9 ++++----
silecs-codegen/src/xml/genparam.py | 2 +-
silecs-codegen/src/xml/genplcsrc.py | 8 +++----
silecs-codegen/src/xml/model/Class/Block.py | 3 +++
silecs-codegen/src/xml/model/Class/Class.py | 22 +++++++++++++++++--
.../src/xml/model/Deploy/Controller.py | 2 +-
6 files changed, 34 insertions(+), 12 deletions(-)
diff --git a/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateSourceCode.py b/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateSourceCode.py
index 019408f..a5af449 100644
--- a/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateSourceCode.py
+++ b/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateSourceCode.py
@@ -48,14 +48,14 @@ def genHSource(className, silecsRoot, fesaRoot, sourcePath,logTopics):
designClass = DesignClass.getDesignClassFromRootNode(silecsRoot)
source = fesaTemplates.genHTop(className)
- for block in designClass.getDesignBlocks():
+ for block in designClass.getDesignFesaBlocks():
if block.isWritable():
serverActionName = findBlockServerSetActionName(fesaRoot,block.getFesaName())
source += fesaTemplates.genHTopBlock(className, serverActionName)
source += fesaTemplates.genHTop2(className)
- for block in designClass.getDesignBlocks():
+ for block in designClass.getDesignFesaBlocks():
if block.isAcquisition():
source += fesaTemplates.genHBlock('RO', block.name,block.getFesaName() )
elif block.isCommand():
@@ -65,7 +65,7 @@ def genHSource(className, silecsRoot, fesaRoot, sourcePath,logTopics):
source += fesaTemplates.genHBottom(className)
- for block in designClass.getDesignBlocks():
+ for block in designClass.getDesignFesaBlocks():
source += fesaTemplates.genHDeclBlocks(block.name)
source += fesaTemplates.genHClosing(className)
@@ -93,7 +93,8 @@ def genHSource(className, silecsRoot, fesaRoot, sourcePath,logTopics):
def genCppSource(className, silecsRoot, fesaRoot, sourcePath,logTopics):
designClass = DesignClass.getDesignClassFromRootNode(silecsRoot)
finalSource = fesaTemplates.genCTop(className)
- blockList = designClass.getDesignBlocks()
+ blockList = designClass.getDesignFesaBlocks()
+
for block in blockList:
finalSource += fesaTemplates.genCGlobal(className, block.name)
diff --git a/silecs-codegen/src/xml/genparam.py b/silecs-codegen/src/xml/genparam.py
index 236fc5f..5b8fb47 100644
--- a/silecs-codegen/src/xml/genparam.py
+++ b/silecs-codegen/src/xml/genparam.py
@@ -65,7 +65,7 @@ def computeChecksumController( workspacePath, deploy, controller, silecsVersion,
def computeChecksumClass(designDOM, CRC32, logTopics={'errorlog': True}):
designClass = DesignClass.getDesignClassFromRootNode(designDOM)
- for block in designClass.getDesignBlocks():
+ for block in designClass.getDesignMemoryBlocks():
CRC32 = zlib.crc32(trim(block.name),CRC32)& 0xffffffff
for register in block.getDesignRegisters():
CRC32 = zlib.crc32(trim(register.name),CRC32)& 0xffffffff
diff --git a/silecs-codegen/src/xml/genplcsrc.py b/silecs-codegen/src/xml/genplcsrc.py
index 925ad16..2ccc9d4 100644
--- a/silecs-codegen/src/xml/genplcsrc.py
+++ b/silecs-codegen/src/xml/genplcsrc.py
@@ -184,7 +184,7 @@ def generateSiemensSources(param, sourceFolderPath ,logTopics):
# Generate the Data-Blocks: one DB per Device instance
for deviceIndex, deviceDOM in enumerate(deviceDOMList):
blockList = ''
- for block in paramClass.getParamBlocks():
+ for block in paramClass.getParamMemoryBlocks():
blockList += s7template.stlBlock(paramClass.name, block.name)
deviceLabel = deviceDOM.prop('label')
stlString += s7template.generateBlock(param.owner, paramClass.name, paramClass.version, param.controller.system, DBnumber, deviceLabel, blockList, (deviceIndex == 0),param.controller.protocol)
@@ -193,7 +193,7 @@ def generateSiemensSources(param, sourceFolderPath ,logTopics):
else: # BLOCK_MODE
# Generate the Data-Blocks: one DB per Block of registers
- for blockIndex, block in enumerate(paramClass.getParamBlocks()):
+ for blockIndex, block in enumerate(paramClass.getParamMemoryBlocks()):
deviceList = ''
for deviceDOM in deviceDOMList:
deviceLabel = deviceDOM.prop('label')
@@ -318,7 +318,7 @@ def generateDIGISources(param,sourceFolderPath,logTopics):
if param.controller.protocol == 'DEVICE_MODE':
# Generate the List of block in the class
blockList =''
- for block in paramClass.getParamBlocks():
+ for block in paramClass.getParamMemoryBlocks():
blockList += DIGITemplate.cDeviceModeBlockInstantiation(paramClass.name, block.name)
deviceList = ''
@@ -328,7 +328,7 @@ def generateDIGISources(param,sourceFolderPath,logTopics):
deviceList = deviceList[:-2] # remove last comma space
classList += DIGITemplate.cDeviceModeClass_deviceList(blockList, deviceList)
else: # BLOCK_MODE
- for block in paramClass.getParamBlocks():
+ for block in paramClass.getParamMemoryBlocks():
# DeviceList
deviceList = ''
for deviceDOM in paramClass.getDeviceInstanceNodes():
diff --git a/silecs-codegen/src/xml/model/Class/Block.py b/silecs-codegen/src/xml/model/Class/Block.py
index df93b6f..6435f3e 100644
--- a/silecs-codegen/src/xml/model/Class/Block.py
+++ b/silecs-codegen/src/xml/model/Class/Block.py
@@ -114,6 +114,9 @@ class ParamBlock(Block):
def initWithDesignBlock(self, designBlock):
newNode = libxml2.newNode(designBlock.xmlNode.get_name())
newNode.newProp("name", designBlock.name)
+ if designBlock.xmlNode.hasProp("ioType"):
+ newNode.newProp("ioType", designBlock.xmlNode.prop("ioType"))
+ print newNode.get_name()
super(ParamBlock, self).__init__(newNode)
newNode.newProp("size", str(self.size))
newNode.newProp("address", str(self.address))
diff --git a/silecs-codegen/src/xml/model/Class/Class.py b/silecs-codegen/src/xml/model/Class/Class.py
index e0f678c..14061cb 100644
--- a/silecs-codegen/src/xml/model/Class/Class.py
+++ b/silecs-codegen/src/xml/model/Class/Class.py
@@ -31,6 +31,12 @@ class Class(object):
return iecommon.capitalizeString(self.name)
def getBlockNodes(self):
+ return self.getIOBlockNodes() + self.getMemoryBlockNodes()
+
+ def getIOBlockNodes(self):
+ return self.xmlNode.xpathEval("*[name()='Acquisition-IO-Block' or name()='Setting-IO-Block']")
+
+ def getMemoryBlockNodes(self):
return self.xmlNode.xpathEval("*[name()='Acquisition-Block' or name()='Setting-Block' or name()='Command-Block']")
class ParamClass(Class):
@@ -79,8 +85,7 @@ class ParamClass(Class):
for blockNode in self.getMemoryBlockNodes():
paramBlock = ParamBlock()
paramBlock.initWithParamBlockNode(blockNode)
- if paramBlock.isMEMBlock():
- paramMemBlocks.append(paramBlock)
+ paramMemBlocks.append(paramBlock)
return paramMemBlocks
def getDeviceInstanceNodes(self):
@@ -96,12 +101,25 @@ class DesignClass(Class):
def getFesaName(self):
return self.fesaPropertyName
+ def getDesignFesaBlocks(self):
+ designFesaBlocks = []
+ for block in self.getDesignBlocks():
+ if block.generateFesaProperty:
+ designFesaBlocks.append(block)
+ return designFesaBlocks
+
def getDesignBlocks(self):
designBlocks = []
for blockNode in self.getBlockNodes():
designBlocks.append(DesignBlock(blockNode))
return designBlocks
+ def getDesignMemoryBlocks(self):
+ designBlocks = []
+ for blockNode in self.getMemoryBlockNodes():
+ designBlocks.append(DesignBlock(blockNode))
+ return designBlocks
+
@staticmethod
def getDesignClassFromRootNode(silecsRoot):
classNodes = silecsRoot.xpathEval('/SILECS-Design/SILECS-Class')
diff --git a/silecs-codegen/src/xml/model/Deploy/Controller.py b/silecs-codegen/src/xml/model/Deploy/Controller.py
index 2dedd2a..ce74085 100644
--- a/silecs-codegen/src/xml/model/Deploy/Controller.py
+++ b/silecs-codegen/src/xml/model/Deploy/Controller.py
@@ -326,7 +326,7 @@ class SiemensController(Controller):
# Compute the base-address of the next class in the SIEMENS PLC IO area
# DEVICE or BLOCK mode use the same data size: next base address should be the same
# 'used-IO' info is expressed in bytes
- def computeIONextBaseAddress(mapping, nbDev):
+ def computeIONextBaseAddress(self, mapping, nbDev):
byteSize = nbDev * mapping.deviceDataSize
self.memSize += byteSize # global size of the plc configuration
startAddr = mapping.classBaseAddress # first byte address used for this class
--
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