From 4e61f2f208fb64cf729ab715dd880add2a7c0348 Mon Sep 17 00:00:00 2001
From: aschwinn <al.schwinn@gsi.de>
Date: Tue, 6 Jun 2017 12:16:06 +0200
Subject: [PATCH] Bug 1407 - Remove Plugin specific design validation Rules
---
.../src/xml/fesa/fesa_3_0_0/fesaTemplates.py | 142 ++++------
.../xml/fesa/fesa_3_0_0/generateFesaDesign.py | 67 ++---
.../xml/fesa/fesa_3_0_0/generateSourceCode.py | 267 ++++--------------
silecs-codegen/src/xml/genduwrapper.py | 19 +-
silecs-codegen/src/xml/genparam.py | 61 ++--
silecs-codegen/src/xml/genplcsrc.py | 173 +++++-------
silecs-codegen/src/xml/iecommon.py | 45 ++-
.../src/xml/migration/0_10_0to1_0_0.py | 26 --
.../src/xml/migration/1_0_Xto1_1_0.py | 40 +++
.../migration1_0_Xto1_1_0/__init__.py | 0
.../migration1_0_Xto1_1_0/migrators.py | 66 +++++
.../migration1_0_Xto1_1_0/testMigration.py | 70 +++++
.../src/xml/migration/migrationBase.py | 26 ++
silecs-codegen/src/xml/migration/runTests.py | 2 +
silecs-codegen/src/xml/model/Register.py | 103 +++++++
silecs-codegen/src/xml/model/__init__.py | 0
silecs-codegen/src/xml/runTests.py | 3 +-
.../src/xml/test/AllTypes.silecsdesign | 250 +++++++++++-----
.../src/xml/test/AllTypesFESA.silecsdesign | 248 +++++++++++-----
.../xml/test/fesa/generateFesaDesignTest.py | 8 +-
.../xml/test/generated_correct/AllTypes.cpp | 46 +--
.../client/Beckhoff_BC9020.silecsparam | 222 +++++++++++----
.../client/Beckhoff_CX9020.silecsparam | 222 +++++++++++----
.../client/Rabbit_BlockMode.silecsparam | 222 +++++++++++----
.../client/Rabbit_DeviceMode.silecsparam | 222 +++++++++++----
.../client/Schneider_M340.silecsparam | 222 +++++++++++----
.../Schneider_PremiumQuantum.silecsparam | 222 +++++++++++----
.../client/Siemens_Step7Block.silecsparam | 222 +++++++++++----
.../client/Siemens_Step7Device.silecsparam | 222 +++++++++++----
.../client/Siemens_TiaBlock.silecsparam | 222 +++++++++++----
.../client/Siemens_TiaDevice.silecsparam | 222 +++++++++++----
silecs-codegen/src/xml/xmltemplate.py | 16 +-
silecs-model/src/xml/DesignSchema.xsd | 132 +++------
33 files changed, 2679 insertions(+), 1351 deletions(-)
create mode 100644 silecs-codegen/src/xml/migration/1_0_Xto1_1_0.py
create mode 100644 silecs-codegen/src/xml/migration/migration1_0_Xto1_1_0/__init__.py
create mode 100644 silecs-codegen/src/xml/migration/migration1_0_Xto1_1_0/migrators.py
create mode 100644 silecs-codegen/src/xml/migration/migration1_0_Xto1_1_0/testMigration.py
create mode 100644 silecs-codegen/src/xml/model/Register.py
create mode 100644 silecs-codegen/src/xml/model/__init__.py
diff --git a/silecs-codegen/src/xml/fesa/fesa_3_0_0/fesaTemplates.py b/silecs-codegen/src/xml/fesa/fesa_3_0_0/fesaTemplates.py
index ed8adab..1c74d2f 100644
--- a/silecs-codegen/src/xml/fesa/fesa_3_0_0/fesaTemplates.py
+++ b/silecs-codegen/src/xml/fesa/fesa_3_0_0/fesaTemplates.py
@@ -620,12 +620,8 @@ cSetStringArrayRegData = """
"""
cSetScalarRegData = """
- (data.is${fieldName_upper}Available()) ? pPLCDevice->getRegister("${regName}")->setVal${regType}( data.${fieldName}.get()) :
- pPLCDevice->getRegister("${regName}")->setVal${regType}( pDevice->${fieldName}.get(pContext));"""
-
-cSetScalarURegData = """
- (data.is${fieldName_upper}Available()) ? pPLCDevice->getRegister("${regName}")->setVal${regType}( (${lowerType})data.${fieldName}.get()) :
- pPLCDevice->getRegister("${regName}")->setVal${regType}( (${lowerType})pDevice->${fieldName}.get(pContext));"""
+ (data.is${fieldName_upper}Available()) ? pPLCDevice->getRegister("${regName}")->setVal${regType}( (${fesaType})data.${fieldName}.get()) :
+ pPLCDevice->getRegister("${regName}")->setVal${regType}( (${fesaType})pDevice->${fieldName}.get(pContext));"""
cSetArrayRegData = """
pRegister = pPLCDevice->getRegister("${regName}");
@@ -633,23 +629,7 @@ cSetArrayRegData = """
(data.is${fieldName_upper}Available()) ? pRegister->setVal${regType}Array( data.${fieldName}.get(fesaDim1), dim1) :
pRegister->setVal${regType}Array( pDevice->${fieldName}.get(fesaDim1, pContext), dim1);
"""
-
-cSetUnsignedArrayRegData = """
- pRegister = pPLCDevice->getRegister("${regName}");
- dim1 = pRegister->getDimension1();
- (data.is${fieldName_upper}Available()) ? pRegister->setVal${regType}Array( data.${fieldName}.get(fesaDim1), dim1) :
- pRegister->setVal${regType}Array( pDevice->${fieldName}.get(fesaDim1, pContext), dim1);
- """
-
cSetArray2DRegData = """
- pRegister = pPLCDevice->getRegister("${regName}");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (_upper}Available()) ? pRegister->setVal${regType}Array2D(data.${fieldName}.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setVal${regType}Array2D(pDevice->${fieldName}.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-"""
-
-cSetUnsignedArray2DRegData = """
pRegister = pPLCDevice->getRegister("${regName}");
dim1 = pRegister->getDimension1();
dim2 = pRegister->getDimension2();
@@ -764,26 +744,26 @@ def genCGetPLC(className, blockName):
def genCPart4(className):
return cPart4.replace('${className}', className)
-def genCGetStringReg(regName, fieldName):
- return cGetStringReg.replace('${regName}', regName).replace('${fieldName}', fieldName)
+def genCGetStringReg(register):
+ return cGetStringReg.replace('${regName}', register.name).replace('${fieldName}', register.getFesaName())
-def genCGetStringArrayReg(regName, fieldName):
- return cGetStringArrayReg.replace('${regName}', regName).replace('${fieldName}', fieldName)
+def genCGetStringArrayReg(register):
+ return cGetStringArrayReg.replace('${regName}', register.name).replace('${fieldName}', register.getFesaName())
-def genCGetScalarReg(regName, fieldName, regType):
- return cGetScalarReg.replace('${regName}', regName).replace('${regType}', regType).replace('${fieldName}', fieldName)
+def genCGetScalarReg(register):
+ return cGetScalarReg.replace('${regName}', register.name).replace('${regType}', iecommon.getSilecsDataTypeUpperCase(register.format)).replace('${fieldName}', register.getFesaName())
-def genCGetArrayReg(regName, fieldName, regType):
- return cGetArrayReg.replace('${regName}', regName).replace('${regType}', regType).replace('${fieldName}', fieldName)
+def genCGetArrayReg(register):
+ if iecommon.isUnsignedType(register.format):
+ return cGetUnsignedArrayReg.replace('${regName}', register.name).replace('${regType}', iecommon.getSilecsDataTypeUpperCase(register.format)).replace('${fieldName}', register.getFesaName()).replace('${fesaType}', iecommon.registerFormatType2FesaType(register.format))
+ else:
+ return cGetArrayReg.replace('${regName}', register.name).replace('${regType}', iecommon.getSilecsDataTypeUpperCase(register.format)).replace('${fieldName}', register.getFesaName())
-def genCGetArray2DReg(regName, fieldName, regType):
- return cGetArray2DReg.replace('${regName}', regName).replace('${regType}', regType).replace('${fieldName}', fieldName)
-
-def genCGetUnsignedArrayReg(regName, fieldName, fesaType, regType):
- return cGetUnsignedArrayReg.replace('${regName}', regName).replace('${regType}', regType).replace('${fieldName}', fieldName)
-
-def genCGetUnsignedArray2DReg(regName, fieldName, fesaType, regType):
- return cGetUnsignedArray2DReg.replace('${regName}', regName).replace('${regType}', regType).replace('${fesaType]', fesaType).replace('${fieldName}', fieldName)
+def genCGetArray2DReg(register):
+ if iecommon.isUnsignedType(register.format):
+ return cGetUnsignedArray2DReg.replace('${regName}', register.name).replace('${regType}', iecommon.getSilecsDataTypeUpperCase(register.format)).replace('${fesaType]', iecommon.registerFormatType2FesaType(register.format)).replace('${fieldName}', register.getFesaName())
+ else:
+ return cGetArray2DReg.replace('${regName}', register.name).replace('${regType}', iecommon.getSilecsDataTypeUpperCase(register.format)).replace('${fieldName}', register.getFesaName())
def genCCommonSet(blockName,className):
return cCommonSet.replace('${className}', className).replace('${blockName}', blockName)
@@ -791,53 +771,45 @@ def genCCommonSet(blockName,className):
def genCDatatypeSet(blockName,propName,className):
return cDatatypeSet.replace('${className}', className).replace('${blockName}', blockName).replace('${propName}', propName)
-def genCSetStringReg(regName, fieldName):
- return cSetStringReg.replace('${regName}', regName).replace('${fieldName}', fieldName)
-
-def genCSetStringArrayReg(regName, fieldName):
- return cSetStringArrayReg.replace('${regName}', regName).replace('${fieldName}', fieldName)
-
-def genCSetScalarReg(regName, fieldName, regType):
- return cSetScalarReg.replace('${regName}', regName).replace('${regType}', regType).replace('${fieldName}', fieldName)
-
-def genCSetScalarUReg(regName, fieldName, regType, lowerType):
- return cSetScalarUReg.replace('${regName}', regName).replace('${regType}', regType).replace('${lowerType}', lowerType).replace('${fieldName}', fieldName)
-
-def genCSetArrayReg(regName, fieldName, regType):
- return cSetArrayReg.replace('${regName}', regName).replace('${regType}', regType).replace('${fieldName}', fieldName)
-
-def genCSetUnsignedArrayReg(regName, fieldName, regType):
- return cSetUnsignedArrayReg.replace('${regName}', regName).replace('${regType}', regType).replace('${fieldName}', fieldName)
-
-def genCSetArray2DReg(regName, fieldName, regType):
- return cSetArray2DReg.replace('${regName}', regName).replace('${regType}', regType).replace('${fieldName}', fieldName)
-
-def genCSetUnsignedArray2DReg(regName, fieldName, regType):
- return cSetUnsignedArray2DReg.replace('${regName}', regName).replace('${regType}', regType).replace('${fieldName}', fieldName)
-
-def genCSetStringRegData(regName, fieldName):
- return cSetStringRegData.replace('${regName}', regName).replace('${fieldName_upper}', iecommon.capitalizeString(fieldName)).replace('${fieldName}', fieldName)
-
-def genCSetStringArrayRegData(regName, fieldName):
- return cSetStringArrayRegData.replace('${regName}', regName).replace('${fieldName_upper}', iecommon.capitalizeString(fieldName)).replace('${fieldName}', fieldName)
-
-def genCSetScalarRegData(regName, fieldName, regType):
- return cSetScalarRegData.replace('${regName}', regName).replace('${fieldName_upper}', iecommon.capitalizeString(fieldName)).replace('${regType}', regType).replace('${fieldName}', fieldName)
-
-def genCSetScalarURegData(regName, fieldName, regType, lowerType):
- return cSetScalarURegData.replace('${regName}', regName).replace('${fieldName_upper}', iecommon.capitalizeString(fieldName)).replace('${regType}', regType).replace('${lowerType}', lowerType).replace('${fieldName}', fieldName)
-
-def genCSetUnsignedArrayRegData(regName, fieldName, regType):
- return cSetUnsignedArrayRegData.replace('${regName}', regName).replace('${fieldName_upper}', iecommon.capitalizeString(fieldName)).replace('${regType}', regType).replace('${fieldName}', fieldName)
-
-def genCSetUnsignedArray2DRegData(regName, fieldName, fesaType, regType):
- return cSetUnsignedArray2DRegData.replace('${regName}', regName).replace('${fieldName_upper}', iecommon.capitalizeString(fieldName)).replace('${regType}', regType).replace('${fieldName}', fieldName)
-
-def genCSetArrayRegData(regName, fieldName, regType):
- return cSetArrayRegData.replace('${regName}', regName).replace('${fieldName_upper}', iecommon.capitalizeString(fieldName)).replace('${regType}', regType).replace('${fieldName}', fieldName)
-
-def genCSetArray2DRegData(regName, fieldName, fesaType, regType):
- return cSetArray2DRegData.replace('${regName}', regName).replace('${fieldName_upper}', iecommon.capitalizeString(fieldName)).replace('${regType}', regType).replace('${fieldName}', fieldName)
+def genCSetStringReg(register):
+ return cSetStringReg.replace('${regName}', register.name).replace('${fieldName}', register.getFesaName())
+
+def genCSetStringArrayReg(register):
+ return cSetStringArrayReg.replace('${regName}', register.name).replace('${fieldName}', register.getFesaName())
+
+def genCSetScalarReg(register):
+ if iecommon.isUnsignedType(register.format):
+ return cSetScalarUReg.replace('${regName}', register.name).replace('${regType}', iecommon.getSilecsDataTypeUpperCase(register.format)).replace('${lowerType}', lowerType).replace('${fieldName}', register.getFesaName())
+ else:
+ return cSetScalarReg.replace('${regName}', register.name).replace('${regType}', iecommon.getSilecsDataTypeUpperCase(register.format)).replace('${fieldName}', register.getFesaName())
+
+
+def genCSetArrayReg(register):
+ if iecommon.isUnsignedType(register.format):
+ return cSetUnsignedArrayReg.replace('${regName}', register.name).replace('${regType}', iecommon.getSilecsDataTypeUpperCase(register.format)).replace('${fieldName}', register.getFesaName())
+ else:
+ return cSetArrayReg.replace('${regName}', register.name).replace('${regType}', iecommon.getSilecsDataTypeUpperCase(register.format)).replace('${fieldName}', register.getFesaName())
+
+def genCSetArray2DReg(register):
+ if iecommon.isUnsignedType(register.format):
+ return cSetUnsignedArray2DReg.replace('${regName}', register.name).replace('${regType}', iecommon.getSilecsDataTypeUpperCase(register.format)).replace('${fieldName}', register.getFesaName())
+ else:
+ return cSetArray2DReg.replace('${regName}', register.name).replace('${regType}', iecommon.getSilecsDataTypeUpperCase(register.format)).replace('${fieldName}', register.getFesaName())
+
+def genCSetStringRegData(register):
+ return cSetStringRegData.replace('${regName}', register.name).replace('${fieldName_upper}', iecommon.capitalizeString(register.getFesaName())).replace('${fieldName}', register.getFesaName())
+
+def genCSetStringArrayRegData(register):
+ return cSetStringArrayRegData.replace('${regName}', register.name).replace('${fieldName_upper}', iecommon.capitalizeString(register.getFesaName())).replace('${fieldName}', register.getFesaName())
+
+def genCSetScalarRegData(register):
+ return cSetScalarRegData.replace('${regName}', register.name).replace('${fieldName_upper}', iecommon.capitalizeString(register.getFesaName())).replace('${regType}', iecommon.getSilecsDataTypeUpperCase(register.format)).replace('${fesaType}', iecommon.registerFormatType2FesaType(register.format)).replace('${fieldName}', register.getFesaName())
+
+def genCSetArrayRegData(register):
+ return cSetArrayRegData.replace('${regName}', register.name).replace('${fieldName_upper}', iecommon.capitalizeString(register.getFesaName())).replace('${regType}', iecommon.getSilecsDataTypeUpperCase(register.format)).replace('${fieldName}', register.getFesaName())
+
+def genCSetArray2DRegData(register):
+ return cSetArray2DRegData.replace('${regName}', register.name).replace('${fieldName_upper}', iecommon.capitalizeString(register.getFesaName())).replace('${regType}', iecommon.getSilecsDataTypeUpperCase(register.format)).replace('${fieldName}', register.getFesaName())
def genMakeDesign(centralMakefilePath):
return makeDesign.replace('${centralMakefilePath}', centralMakefilePath)
diff --git a/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateFesaDesign.py b/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateFesaDesign.py
index 83af3b7..3afc5b0 100644
--- a/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateFesaDesign.py
+++ b/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateFesaDesign.py
@@ -32,6 +32,7 @@ import iefiles
from iecommon import *
from fesaGeneral import *
+from model.Register import DesignRegister
import libxml2
@@ -49,72 +50,60 @@ class FESADesignGenerator3_0_0(object):
return True
return False
-
- def getSilecsStringLength(self,register):
- strlen = '64'# check if custom length exists for string, otherwise use default length (64)
- if(register.hasProp('string-len')):
- strlen = str(register.prop('string-len'))
- return strlen
-
def getOrCreateStringArrayType(self,fieldNode,register):
array2DNode = getOrCreateChildElement(fieldNode,'array2D')
- fillAttributes(array2DNode, {'type': iecommon.getFesaDataType(register.prop('format'))})
+ fillAttributes(array2DNode, {'type': iecommon.getFesaDataType(register.format)})
dim1Node = getOrCreateChildElement(array2DNode,'dim1')
dim2Node = getOrCreateChildElement(array2DNode,'dim2')
- dim1Node.setContent(register.prop('array-dim1')) # first dimension is the dimension of the array
- dim2Node.setContent(self.getSilecsStringLength(register)) # first dimension is the dimension of the array
+ dim1Node.setContent(str(register.dim1)) # first dimension is the dimension of the array
+ dim2Node.setContent(str(register.stringLength))
return array2DNode
def getOrCreateStringType(self,fieldNode,register):
stringNode = getOrCreateChildElement(fieldNode,'array')
- fillAttributes(stringNode, {'type': iecommon.getFesaDataType(register.prop('format'))})
+ fillAttributes(stringNode, {'type': iecommon.getFesaDataType(register.format)})
dimNode = getOrCreateChildElement(stringNode,'dim')
- dimNode.setContent(self.getSilecsStringLength(register)) # first dimension is the dimension of the array
+ dimNode.setContent(str(register.stringLength)) # first dimension is the dimension of the array
return stringNode
def getOrCreate2DArrayType(self,fieldNode,register):
array2DNode = getOrCreateChildElement(fieldNode,'array2D')
- fillAttributes(array2DNode, {'type': iecommon.getFesaDataType(register.prop('format'))})
+ fillAttributes(array2DNode, {'type': iecommon.getFesaDataType(register.format)})
dim1Node = getOrCreateChildElement(array2DNode,'dim1')
dim2Node = getOrCreateChildElement(array2DNode,'dim2')
- dim1Node.setContent(register.prop('array-dim1'))
- dim2Node.setContent(register.prop('array-dim2'))
+ dim1Node.setContent(str(register.dim1))
+ dim2Node.setContent(str(register.dim2))
return array2DNode
def getOrCreateArrayType(self,fieldNode,register):
arrayNode = getOrCreateChildElement(fieldNode,'array')
- fillAttributes(arrayNode, {'type': iecommon.getFesaDataType(register.prop('format'))})
+ fillAttributes(arrayNode, {'type': iecommon.getFesaDataType(register.format)})
dimNode = getOrCreateChildElement(arrayNode,'dim')
- dimNode.setContent(register.prop('array-dim1'))
+ dimNode.setContent(str(register.dim1))
return arrayNode
- def getOrCreateScalarType(self,fieldNode,scalarType):
+ def getOrCreateScalarType(self,fieldNode,register):
scalarNode = getOrCreateChildElement(fieldNode,'scalar')
- fillAttributes(scalarNode, {'type': iecommon.getFesaDataType(scalarType)})
+ fillAttributes(scalarNode, {'type': iecommon.getFesaDataType(register.format)})
return scalarNode
- def getOrCreateStringTypeBase(self,fieldNode,register):
- if(register.prop('array-dim2')) and int(register.prop('array-dim2')) > 1:
- iecommon.logError('ERROR: In register '+register.prop('name')+' - 2D array of strings not supported in FESA.', True, {'errorlog': True})
- return null
- elif (register.prop('array-dim1')) and int(register.prop('array-dim1')) > 1:
- return self.getOrCreateStringArrayType(fieldNode,register)
- else:
- return self.getOrCreateStringType(fieldNode,register)
-
- def getOrCreateBaseType(self,fieldNode,register):
- if (register.prop('array-dim2')) and int(register.prop('array-dim2')) > 1:
- return self.getOrCreate2DArrayType(fieldNode,register)
- elif (register.prop('array-dim1')) and int(register.prop('array-dim1')) > 1:
+ def getOrCreateType(self,fieldNode,registerNode):
+ register = DesignRegister(registerNode)
+ if register.valueType == "scalar":
+ return self.getOrCreateScalarType(fieldNode,register)
+ elif register.valueType == "array":
return self.getOrCreateArrayType(fieldNode,register)
+ elif register.valueType == "array2D":
+ return self.getOrCreate2DArrayType(fieldNode,register)
+ elif register.valueType == "string":
+ return self.getOrCreateStringType(fieldNode,register)
+ elif register.valueType == "stringArray":
+ return self.getOrCreateStringArrayType(fieldNode,register)
+ elif register.valueType == "stringArray2D":
+ iecommon.logError('ERROR: In register '+register.name+' - 2D array of strings not supported in FESA.', True, {'errorlog': True})
else:
- return self.getOrCreateScalarType(fieldNode,register.prop('format'))
-
- def getOrCreateType(self,fieldNode,register):
- if(register.prop('format') == 'string'):
- return self.getOrCreateStringTypeBase(fieldNode,register)
- else:
- return self.getOrCreateBaseType(fieldNode,register)
+ iecommon.logError('ERROR: Unknown data-type:' + register.valueType, True, {'errorlog': True})
+ return None
def getOrCreateFieldRef(self,valueItemNode,FieldNameRef):
fieldRefNode = getOrCreateNamedChildElement(valueItemNode,'data-field-ref',FieldNameRef,'field-name-ref')
diff --git a/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateSourceCode.py b/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateSourceCode.py
index e01ebcd..4698210 100644
--- a/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateSourceCode.py
+++ b/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateSourceCode.py
@@ -30,6 +30,7 @@ import iefiles
from iecommon import *
from fesaGeneral import *
+from model.Register import *
import libxml2
def findBlockServerSetActionName(fesaRoot, blockName):
@@ -86,7 +87,8 @@ def genHSource(className, silecsRoot, fesaRoot, sourcePath,logTopics):
# Generates the C++ source file containing general
# methods to synchronise the FESA fields and related PLC
# registers of the FESA server
-#-------------------------------------------------------------------------
+#-------------------------------------------------------------------------
+
def genCppSource(className, silecsRoot, fesaRoot, sourcePath,logTopics):
finalSource = fesaTemplates.genCTop(className)
blockList = silecsRoot.xpathEval('//Block')
@@ -101,8 +103,7 @@ def genCppSource(className, silecsRoot, fesaRoot, sourcePath,logTopics):
finalSource += fesaTemplates.genCPart2(className)
for block in blockList:
- regList = block.xpathEval('Register')
- if (block.prop('mode') == 'WRITE-ONLY' or block.prop('mode') == 'READ-WRITE') and regList[0].prop('synchro') == 'SLAVE':
+ if (block.prop('mode') == 'WRITE-ONLY' or block.prop('mode') == 'READ-WRITE'):
# just set the fields if block is WO or RW and register synchronisation is SLAVE
# WARNING: In order to have multiplexed FESA fields, the corresponding SILECS registers' synchro mode must be 'NONE'
finalSource += fesaTemplates.genCSetPLC(className, block.prop('name'))
@@ -110,8 +111,8 @@ def genCppSource(className, silecsRoot, fesaRoot, sourcePath,logTopics):
finalSource += fesaTemplates.genCPart3(className)
for block in blockList:
- regList = block.xpathEval('Register')
- if (block.prop('mode') == 'READ-ONLY' or block.prop('mode') == 'READ-WRITE') and regList[0].prop('synchro') == 'MASTER':
+
+ if (block.prop('mode') == 'READ-ONLY' or block.prop('mode') == 'READ-WRITE'):
# just get the fields if block is RO or RW and register synchronisation is MASTER
# WARNING: In order to have multiplexed FESA fields, the corresponding SILECS registers' synchro mode must be 'NONE'
finalSource += fesaTemplates.genCGetPLC(className, block.prop('name'))
@@ -119,216 +120,72 @@ def genCppSource(className, silecsRoot, fesaRoot, sourcePath,logTopics):
finalSource += fesaTemplates.genCPart4(className)
for block in blockList:
-
- source = '' #compute one source at a time
- flagReg = False
- flagDim1 = False
- flagDim2 = False
-
if block.prop('mode') != 'WRITE-ONLY':
finalSource += fesaTemplates.genCCommonGet(block.prop('name'),className)
-
- regList = block.xpathEval('Register')
- source += fesaTemplates.cRecv
-
- for reg in regList:
- type = reg.prop('format')
- if type == 'string': # string register
- flagReg = True
- if (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # string array
- flagDim1 = True
- source += fesaTemplates.genCGetStringArrayReg(reg.prop('name'), getFesaName(reg))
- else: # simple string
- source += fesaTemplates.genCGetStringReg(reg.prop('name'), getFesaName(reg))
-
- else: # not string register
- # uppercasing of type
- fesaType = iecommon.getFesaDataType(type)
- type = iecommon.getSilecsDataType(type)
- if type[0] == 'u':
- type = type[:2].upper() + type[2:] # first two characters if unsigned
-
- if reg.prop('array-dim2') and int(reg.prop('array-dim2')) > 1: # 2D array
- flagReg = True
- flagDim2 = True
- flagDim1 = True
- source += fesaTemplates.genCGetUnsignedArray2DReg(reg.prop('name'), getFesaName(reg), fesaType, type)
- elif (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # array
- flagReg = True
- flagDim1 = True
- source += fesaTemplates.genCGetUnsignedArrayReg(reg.prop('name'), getFesaName(reg), fesaType, type)
- else: # scalar
- source += fesaTemplates.genCGetScalarReg(reg.prop('name'), getFesaName(reg), type)
-
- elif type[0] == 'd': # date type
- if reg.prop('array-dim2') and int(reg.prop('array-dim2')) > 1:
- flagReg = True
- flagDim2 = True
- flagDim1 = True
- source += fesaTemplates.genCGetArray2DReg(reg.prop('name'), getFesaName(reg), 'Date')
- elif (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # array
- flagReg = True
- flagDim1 = True
- source += fesaTemplates.genCGetArrayReg(reg.prop('name'), getFesaName(reg), 'Date')
- else: # scalar
- source += fesaTemplates.genCGetScalarReg(reg.prop('name'), getFesaName(reg), 'Date')
-
- else:
- type = type[:1].upper() + type[1:] # only first character if not unsigned
- if reg.prop('array-dim2') and int(reg.prop('array-dim2')) > 1: # 2D array
- flagReg = True
- flagDim2 = True
- flagDim1 = True
- source += fesaTemplates.genCGetArray2DReg(reg.prop('name'), getFesaName(reg), type)
- elif (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # array
- flagReg = True
- flagDim1 = True
- source += fesaTemplates.genCGetArrayReg(reg.prop('name'), getFesaName(reg), type)
- else: # scalar
- source += fesaTemplates.genCGetScalarReg(reg.prop('name'), getFesaName(reg), type)
-
- source += '\n\t}' # closing bracket for block
-
- #Add data declatation on top if needed and append the final source
- if flagReg == True:
finalSource += fesaTemplates.cRegVar
- if flagDim1 == True:
finalSource += fesaTemplates.cGetArrayVar
- if flagDim2 == True:
finalSource += fesaTemplates.cGetArray2DVar
-
- finalSource += '\n' + source
-
- source = '' #compute one source at a time
- flagReg = False
- flagDim1 = False
- flagDim2 = False
+ finalSource += '\n'
+ finalSource += fesaTemplates.cRecv
+ for registerNode in block.xpathEval('Register'):
+ register = DesignRegister(registerNode)
+ if register.valueType == 'string':
+ finalSource += fesaTemplates.genCGetStringReg(register)
+ elif register.valueType == 'stringArray':
+ finalSource += fesaTemplates.genCGetStringArrayReg(register)
+ elif register.valueType == 'stringArray2D':
+ iecommon.logError('ERROR: In register '+register.name+' - 2D array of strings not supported in FESA.', True, {'errorlog': True})
+ elif register.valueType == 'scalar':
+ finalSource += fesaTemplates.genCGetScalarReg(register)
+ elif register.valueType == 'array':
+ finalSource += fesaTemplates.genCGetArrayReg(register)
+ elif register.valueType == 'array2D':
+ finalSource += fesaTemplates.genCGetArray2DReg(register)
+ finalSource += '\n }\n'
if block.prop('mode') != 'READ-ONLY':
finalSource += fesaTemplates.genCCommonSet(block.prop('name'),className)
-
- regList = block.xpathEval('Register')
-
- for reg in regList:
- type = reg.prop('format')
- if type == 'string':
- flagReg = True
- if (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # string array
- flagDim1 = True
- source += fesaTemplates.genCSetStringArrayReg(reg.prop('name'), getFesaName(reg))
- else: # simple string
- source += fesaTemplates.genCSetStringReg(reg.prop('name'), getFesaName(reg))
-
- else: # not string register
- # uppercasing of type
- type = iecommon.getSilecsDataType(type)
- lowerType = type+'_t' # store lowercase type for unsigned registers (fesa type)
- if type[0] == 'u': # unsigned type
- type = type[:2].upper() + type[2:] # first two characters if unsigned
-
- if reg.prop('array-dim2') and int(reg.prop('array-dim2')) > 1: # 2D array
- flagReg = True
- flagDim2 = True
- flagDim1 = True
- source += fesaTemplates.genCSetUnsignedArray2DReg(reg.prop('name'), getFesaName(reg), type)
- elif (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # array
- flagReg = True
- flagDim1 = True
- source += fesaTemplates.genCSetUnsignedArrayReg(reg.prop('name'), getFesaName(reg), type)
- else: # scalar
- source += fesaTemplates.genCSetScalarUReg(reg.prop('name'), getFesaName(reg), type, lowerType)
-
- else: # signed type
- type = type[:1].upper() + type[1:] # only first character if not unsigned
- if reg.prop('array-dim2') and int(reg.prop('array-dim2')) > 1: # 2D array
- flagReg = True
- flagDim2 = True
- flagDim1 = True
- source += fesaTemplates.genCSetArray2DReg(reg.prop('name'), getFesaName(reg), type)
- elif (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # array
- flagReg = True
- flagDim1 = True
- source += fesaTemplates.genCSetArrayReg(reg.prop('name'), getFesaName(reg), type)
- else: # scalar
- source += fesaTemplates.genCSetScalarReg(reg.prop('name'), getFesaName(reg), type)
-
- source += fesaTemplates.cSend
- source += '\n\t}' # closing bracket for block
-
- #Add data declatation on top if needed and append the final source
- if flagReg == True:
- finalSource += fesaTemplates.cRegVar
- if flagDim1 == True:
- finalSource += fesaTemplates.cSetArrayVar
- if flagDim2 == True:
- finalSource += fesaTemplates.cSetArray2DVar
-
- finalSource += '\n' + source
-
- source = '' #compute one source at a time
- flagReg = False
- flagDim1 = False
- flagDim2 = False
-
+ finalSource += fesaTemplates.cRegVar
+ finalSource += fesaTemplates.cSetArrayVar
+ finalSource += fesaTemplates.cSetArray2DVar
+ for registerNode in block.xpathEval('Register'):
+ register = DesignRegister(registerNode)
+ if register.valueType == 'string':
+ finalSource += fesaTemplates.genCSetStringReg(register)
+ elif register.valueType == 'stringArray':
+ finalSource += fesaTemplates.genCSetStringArrayReg(register)
+ elif register.valueType == 'stringArray2D':
+ iecommon.logError('ERROR: In register '+register.name+' - 2D array of strings not supported in FESA.', True, {'errorlog': True})
+ elif register.valueType == 'scalar':
+ finalSource += fesaTemplates.genCSetScalarReg(register)
+ elif register.valueType == 'array':
+ finalSource += fesaTemplates.genCSetArrayReg(register)
+ elif register.valueType == 'array2D':
+ finalSource += fesaTemplates.genCSetArray2DReg(register)
+ finalSource += fesaTemplates.cSend
+ finalSource += ' }\n'
finalSource += fesaTemplates.genCDatatypeSet(block.prop('name'),getFesaName(block), className)
+ finalSource += fesaTemplates.cRegVar
+ finalSource += fesaTemplates.cSetArrayVar
+ finalSource += fesaTemplates.cSetArray2DVar
- regList = block.xpathEval('Register')
-
- for reg in regList:
- type = reg.prop('format')
- if type == 'string':
- flagReg = True
- if (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # string array
- flagDim1 = True
- source += fesaTemplates.genCSetStringArrayRegData(reg.prop('name'), getFesaName(reg))
- else: # simple string
- source += fesaTemplates.genCSetStringRegData(reg.prop('name'), getFesaName(reg))
-
- else: # not string register
- # uppercasing of type
- fesaType = iecommon.getFesaDataType(type)
- type = iecommon.getSilecsDataType(type)
- lowerType = type+'_t' # store lowercase type for unsigned registers (fesa type)
- if type[0] == 'u': # unsigned type
- type = type[:2].upper() + type[2:] # first two characters if unsigned
- if reg.prop('array-dim2') and int(reg.prop('array-dim2')) > 1: # 2D array
- flagReg = True
- flagDim2 = True
- flagDim1 = True
- source += fesaTemplates.genCSetUnsignedArray2DRegData(reg.prop('name'), getFesaName(reg), fesaType, type)
- elif (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # array
- flagReg = True
- flagDim1 = True
- source += fesaTemplates.genCSetUnsignedArrayRegData(reg.prop('name'), getFesaName(reg), type)
- else: # scalar
- source += fesaTemplates.genCSetScalarURegData(reg.prop('name'), getFesaName(reg), type, lowerType)
-
- else: # signed type
- type = type[:1].upper() + type[1:] # only first character if not unsigned
- if reg.prop('array-dim2') and int(reg.prop('array-dim2')) > 1: # 2D array
- flagReg = True
- flagDim2 = True
- flagDim1 = True
- source += fesaTemplates.genCSetArray2DRegData(reg.prop('name'), getFesaName(reg), fesaType, type)
- elif (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # array
- flagReg = True
- flagDim1 = True
- source += fesaTemplates.genCSetArrayRegData(reg.prop('name'), getFesaName(reg), type)
- else: # scalar
- source += fesaTemplates.genCSetScalarRegData(reg.prop('name'), getFesaName(reg), type)
-
- source += fesaTemplates.cSend
- source += '\n\t}' # closing bracket for block
-
- #Add data declatation on top if needed and append the final source
- if flagReg == True:
- finalSource += fesaTemplates.cRegVar
- if flagDim1 == True:
- finalSource += fesaTemplates.cSetArrayVar
- if flagDim2 == True:
- finalSource += fesaTemplates.cSetArray2DVar
-
- finalSource += '\n' + source
+ for registerNode in block.xpathEval('Register'):
+ register = DesignRegister(registerNode)
+ if register.valueType == 'string':
+ finalSource += fesaTemplates.genCSetStringRegData(register)
+ elif register.valueType == 'stringArray':
+ finalSource += fesaTemplates.genCSetStringArrayRegData(register)
+ elif register.valueType == 'stringArray2D':
+ iecommon.logError('ERROR: In register '+register.name+' - 2D array of strings not supported in FESA.', True, {'errorlog': True})
+ elif register.valueType == 'array2D':
+ finalSource += fesaTemplates.genCSetArray2DRegData(register)
+ elif register.valueType == 'array':
+ finalSource += fesaTemplates.genCSetArrayRegData(register)
+ elif register.valueType == 'scalar':
+ finalSource += fesaTemplates.genCSetScalarRegData(register)
+
+ finalSource += fesaTemplates.cSend
+ finalSource += '\n }\n' # closing bracket for block
finalSource += '\n}\n' # closing bracket for class
diff --git a/silecs-codegen/src/xml/genduwrapper.py b/silecs-codegen/src/xml/genduwrapper.py
index c42a32a..05b7501 100644
--- a/silecs-codegen/src/xml/genduwrapper.py
+++ b/silecs-codegen/src/xml/genduwrapper.py
@@ -24,6 +24,7 @@ import iefiles
import genduwrappertemplate
from iecommon import *
+from model.Register import DesignRegister
#=========================================================================
# Sub-functions
@@ -46,21 +47,9 @@ def getRegisterList(designFile,blockName):
if blockNode.prop("name")==blockName:
break #after the loop blockNode will point to the good node
- registerNodeList=blockNode.xpathEval("Register")
- for registerNode in registerNodeList:
- name = registerNode.prop("name")
- format = registerNode.prop("format")
- dim1 = 1
- dim2 = 1
- try:
- dim1 = int(registerNode.prop("array-dim1"))
- except:
- pass #use 1 as default dimention
- try:
- dim2 = int(registerNode.prop("array-dim2"))
- except:
- pass #use 1 as default dimention
- registerList.append([name,format,dim1,dim2])
+ for registerNode in blockNode.xpathEval("Register"):
+ register = DesignRegister(registerNode)
+ registerList.append([register.name,register.format,register.dim1,register.dim2])
return registerList
def genClassHeader(workspacePath, deployName, classNode, funcGetSilecsDesignFilePath, funcGetDuDesignWrapperFile, logTopics):
diff --git a/silecs-codegen/src/xml/genparam.py b/silecs-codegen/src/xml/genparam.py
index c7cf906..e93bb7c 100644
--- a/silecs-codegen/src/xml/genparam.py
+++ b/silecs-codegen/src/xml/genparam.py
@@ -28,6 +28,7 @@ import xmltemplate
import iefiles
from iecommon import *
+from model.Register import *
#-------------------------------------------------------------------------
# Global definitions
@@ -857,58 +858,32 @@ def genParamBase( funcGetSilecsDesignFilePath, funcGetParameterFile, funcGetSile
# Generate section <Register></Register>
#-------------------------------------------------------------------------
# INNER LOOP TO ACCESS AT REGISTER LEVEL (LOOP-3)
- for register in block.xpathEval("Register"):
- iecommon.logDebug("------ Processing Register "+register.prop('name')+" ------")
- element4 = libxml2.newNode("Register")
- # Set register name
- element4.setProp("name", register.prop("name"))
- # Set register format
- regFormat = register.prop("format")
- element4.setProp("format", regFormat)
-
- # Just get the register dimensions for next computation
- regDimension1 = '1' #by default
- if register.prop('array-dim1'): #possibly single array
- regDimension1 = register.prop("array-dim1")
- regDimension2 = '1' #by default
- if register.prop('array-dim2'): #possibly double array
- regDimension2 = register.prop('array-dim2')
-
+ for registerNode in block.xpathEval("Register"):
+ designRegister = Register(registerNode)
+ iecommon.logDebug("------ Processing Register "+designRegister.name+ " ------")
# Set length attribute only for string registers
- strLen = '1' #not a string by default (no impact on data total-size)
- if regFormat == 'string':
- strLen = register.prop('string-len')
- if strLen: #is string length defined?
- if plcBrand == 'RABBIT':
- # RABBIT has 8bit memory alignment but uses 16bit word communication protocol (MODBUS).
- # String buffer (8bit elements) must have even number of bytes.
- if ((int(regDimension1)*int(regDimension2)*int(strLen)) % 2 == 1): #XML CliX cannot check that constraint!
- iecommon.logError("String length of %s register must be an even value." %register.prop("name"), False,logTopics)
- sys.exit(2)
- else: # if length not given, set default length for string (=64)
- strLen = '64'
- element4.setProp('string-len', strLen)
+ if designRegister.format == 'string':
+ if plcBrand == 'RABBIT':
+ # RABBIT has 8bit memory alignment but uses 16bit word communication protocol (MODBUS).
+ # String buffer (8bit elements) must have even number of bytes.
+ if ((int(designRegister.dim1)*int(designRegister.dim2)*int(designRegister.stringLength)) % 2 == 1): #XML CliX cannot check that constraint!
+ iecommon.logError("String length of %s designRegister must be an even value." %designRegister.name, False,logTopics)
+ sys.exit(2)
- # Set register dimensions
- element4.setProp("array-dim1", regDimension1)
- element4.setProp("array-dim2", regDimension2)
# Set register size
- regSize = whichDataSize[regFormat]
- element4.setProp("size", regSize)
+ regSize = whichDataSize[designRegister.format]
# Set register address
- regAddress = alignRegAddress(regAddress, regFormat, regSize, regDimension1, regDimension2, strLen)
- element4.setProp("address", str(regAddress))
+ regAddress = alignRegAddress(regAddress, designRegister.format, regSize, designRegister.dim1, designRegister.dim2, designRegister.stringLength)
regCounter = regCounter + 1 # used for NI register address generation
# Set register mem-size
- element4.setProp("mem-size", str(msize))
+ paramRegister = ParamRegister()
+ paramRegister.initWithDesignRegister(designRegister,regSize,regAddress,msize)
# Compute address for the next register
- regAddress = computeAnyNextRegAddress(plcBrand, regAddress, regDimension1, regDimension2)
- # Set register synchro
- element4.setProp("synchro", register.prop("synchro"))
+ regAddress = computeAnyNextRegAddress(plcBrand, regAddress, designRegister.dim1, designRegister.dim2)
# Append register
- element3.addChild(element4)
+ element3.addChild(paramRegister.xmlNode)
#iterativelly compute the block size (accumulator initialized outside the loop)
- blockSize = blockSize + (int(regSize) * int(regDimension1) * int(regDimension2))
+ blockSize = blockSize + (int(regSize) * int(designRegister.dim1) * int(designRegister.dim2))
# END OF INNER LOOP TO ACCESS AT REGISTER LEVEL (LOOP-3)
# Set block size
diff --git a/silecs-codegen/src/xml/genplcsrc.py b/silecs-codegen/src/xml/genplcsrc.py
index 0c86eb8..f1e3c2a 100644
--- a/silecs-codegen/src/xml/genplcsrc.py
+++ b/silecs-codegen/src/xml/genplcsrc.py
@@ -28,6 +28,7 @@ import virtualS7Template
import rabbitTemplate
from iecommon import *
+from model.Register import ParamRegister
#=========================================================================
# General remarks
#=========================================================================
@@ -131,7 +132,7 @@ def xsyRegister(regFormat, regDim, regDim2, regLen=1):
def getDateTime():
dt = time.localtime(time.time())
return "DT#%s-%s-%s-%s:%s:%s" %(dt[0],dt[1],dt[2],dt[3],dt[4],dt[5])
-
+
#-------------------------------------------------------------------------
# SIEMENS PLC code generation
#-------------------------------------------------------------------------
@@ -160,28 +161,23 @@ def generateSiemensSources(paramDOM, sourceFolderPath ,logTopics):
for blockIndex, blockDOM in enumerate(blockDOMList):
registerList = ''
blockName = blockDOM.prop('name')
- registerDOMList = blockDOM.xpathEval("Register") # get registers of the current block
- for registerIndex, registerDOM in enumerate(registerDOMList):
- registerName = registerDOM.prop('name')
- registerFormat = registerDOM.prop('format')
+ for registerDOM in blockDOM.xpathEval("Register"):
+ register = ParamRegister()
+ register.initWithParamRegisterNode(registerDOM)
# If PLC does not supports this register format abort this generation and log the error
- if(registerFormat in ['uint64','int64','float64']):
+ if(register.format in ['uint64','int64','float64']):
iecommon.logError('ERROR: In design %s_%s register %s, %s format not supported for current controller model.'
- %(className, classVersion, registerName, registerFormat)
+ %(className, classVersion, register.name, register.format)
, True,logTopics)
#create register value if required (diagnostic registers assignment in particular)
- registerValue = s7template.stlRegisterValue(registerName, deploy.owner, getDateTime(), deploy.checksum,deploy.silecsVersion)
-
- # Read register dimensions
- registerDimension1 = long(registerDOM.prop('array-dim1'))
- registerDimension2 = long(registerDOM.prop('array-dim2'))
+ registerValue = s7template.stlRegisterValue(register.name, deploy.owner, getDateTime(), deploy.checksum,deploy.silecsVersion)
- if registerFormat == 'string':
- registerList += s7template.stlRegister(registerName, registerFormat, registerDimension1, registerDimension2, registerValue, long(registerDOM.prop('string-len')))
+ if register.format == 'string':
+ registerList += s7template.stlRegister(register.name, register.format, register.dim1, register.dim2, registerValue, long(register.stringLength))
else:
- registerList += s7template.stlRegister(registerName, registerFormat, registerDimension1, registerDimension2, registerValue)
+ registerList += s7template.stlRegister(register.name, register.format, register.dim1, register.dim2, registerValue)
stlString += s7template.stlBlockUDT(deploy.owner, className, classVersion, blockName, registerList, (blockIndex == 0))
symString += s7template.symBlockUDT(className, classVersion, blockName, UDTnumber, (blockIndex == 0))
@@ -236,26 +232,20 @@ def generateSchneiderRegisters(xsydoc, classDOM, deviceDOM, blockDOM, deviceInde
deviceAddress = long(deviceDOM.prop('address'))
blockAddress = long(blockDOM.prop('address'))
blockMemSize = long(blockDOM.prop('mem-size'))
- registerDOMList = blockDOM.xpathEval("Register") # get Registers of the current block
- for registerIndex,registerDOM in enumerate(registerDOMList):
- registerName = registerDOM.prop('name')
- registerFormat = registerDOM.prop('format')
- registerDimension1 = long(registerDOM.prop('array-dim1'))
- registerDimension2 = long(registerDOM.prop('array-dim2'))
+ for registerDOM in blockDOM.xpathEval("Register"):
+ register = ParamRegister()
+ register.initWithParamRegisterNode(registerDOM)
# If PLC does not supports this register format abort this generation and log the error
- if(registerFormat in ['uint64','int64','float64']):
- iecommon.logError('ERROR: In register '+registerName+', '+registerFormat+' format not supported for current controller model.', True,logTopics)
-
- #register has relative address irrespective of the protocol mode.
- registerOffset = long(registerDOM.prop('address'))
+ if(register.format in ['uint64','int64','float64']):
+ iecommon.logError('ERROR: In register '+register.name+', '+register.format+' format not supported for current controller model.', True,logTopics)
# Compute the Register address relying on the Class Parameters file data
# Attention! Schneider uses WORD addressing while Parameters data are expressed in bytes to be PLC independent
if modeDevice:
- registerAddress = (deviceAddress + blockAddress + registerOffset)/2
+ totalAddress = (deviceAddress + blockAddress + register.address)/2
else:
- registerAddress = (blockAddress + (deviceIndex * blockMemSize) + registerOffset)/2
+ totalAddress = (blockAddress + (deviceIndex * blockMemSize) + register.address)/2
# then insert the corresponding DOM element
dataElt = xsydoc.xpathEval("//dataBlock")[0] #only one dataBlock node has been inserted so far
@@ -265,21 +255,21 @@ def generateSchneiderRegisters(xsydoc, classDOM, deviceDOM, blockDOM, deviceInde
# Create register name = regname_crc32(classname)_deviceid
# 24 char (register name) + 1 (underscore) + 4 char (CRC classname) + 1 (underscore) + n (device id) = 30 + n (device id)
# possible problem when device id (n)> 99 --> string > 32 not compatible with Schneider PLCs
- regElt.setProp("name", "%s_%04x_%s" %(registerName, classNameCRC, deviceLabel))
+ regElt.setProp("name", "%s_%04x_%s" %(register.name, classNameCRC, deviceLabel))
- if registerFormat == 'string':
- regElt.setProp("typeName", "%s" %xsyRegister(registerFormat, registerDimension1, registerDimension2, registerDOM.prop('string-len')))
+ if register.format == 'string':
+ regElt.setProp("typeName", "%s" %xsyRegister(register.format, register.dim1, register.dim2, register.stringLength ))
else:
- regElt.setProp("typeName", "%s" %xsyRegister(registerFormat, registerDimension1, registerDimension2))
+ regElt.setProp("typeName", "%s" %xsyRegister(register.format, register.dim1, register.dim2))
- regElt.setProp("topologicalAddress", "%%MW%ld" %registerAddress)
+ regElt.setProp("topologicalAddress", "%%MW%ld" %totalAddress)
if blockName == 'hdrBlk':
initElt = libxml2.newNode('variableInit')
- if registerName == '_version': initElt.setProp("value", deploy.silecsVersion )
- if registerName == '_user' : initElt.setProp("value", deploy.owner)
- if registerName == '_checksum': initElt.setProp("value", "%s" %deploy.checksum)
- if registerName == '_date' : initElt.setProp("value", getDateTime())
+ if register.name == '_version': initElt.setProp("value", deploy.silecsVersion )
+ if register.name == '_user' : initElt.setProp("value", deploy.owner)
+ if register.name == '_checksum': initElt.setProp("value", "%s" %deploy.checksum)
+ if register.name == '_date' : initElt.setProp("value", getDateTime())
regElt.addChild(initElt)
commElt = libxml2.newNode('comment')
commElt.setContent(className+"/"+deviceLabel+"/"+blockName)
@@ -348,21 +338,18 @@ def generateRabbitSources(paramDOM,sourceFolderPath,logTopics):
for blockIndex, blockDOM in enumerate(blockDOMList):
registerList = ''
blockName = blockDOM.prop('name')
- registerDOMList = blockDOM.xpathEval("Register") # get Registers of the current block
- for registerIndex, registerDOM in enumerate(registerDOMList):
- registerName = registerDOM.prop('name')
- registerFormat = registerDOM.prop('format')
- registerDimension1 = long(registerDOM.prop('array-dim1'))
- registerDimension2 = long(registerDOM.prop('array-dim2'))
+ for registerDOM in blockDOM.xpathEval("Register"):
+ register = ParamRegister()
+ register.initWithParamRegisterNode(registerDOM)
# If PLC does not supports this register format abort this generation and log the error
- if(registerFormat in ['float64']):
- iecommon.logError('ERROR: In register '+registerName+', '+registerFormat+' format not supported for current controller model.', True,logTopics)
+ if(register.format in ['float64']):
+ iecommon.logError('ERROR: In register '+ register.name +', '+register.format+' format not supported for current controller model.', True,logTopics)
- if(registerFormat == 'string'):
- registerList += rabbitTemplate.cRegister(registerName, registerFormat, registerDimension1, registerDimension2, long(registerDOM.prop('string-len')))
+ if(register.format == 'string'):
+ registerList += rabbitTemplate.cRegister(register.name, register.format, register.dim1, register.dim2, long(register.stringLength))
else:
- registerList += rabbitTemplate.cRegister(registerName, registerFormat, registerDimension1, registerDimension2)
+ registerList += rabbitTemplate.cRegister(register.name, register.format, register.dim1, register.dim2)
cTypeDefinitions += rabbitTemplate.cBlockUDT(className, classVersion, blockName, registerList, (blockIndex == 0))
@@ -416,7 +403,7 @@ def generateRabbitSources(paramDOM,sourceFolderPath,logTopics):
cCodeString += cInitFunction
# Generate and append sample example
- cCodeString += rabbitTemplate.cExample(deploy.plcProtocol,True,className, blockName, registerName, deviceLabel)
+ cCodeString += rabbitTemplate.cExample(deploy.plcProtocol,True,className, blockName, register.name, deviceLabel)
# Finally, write the String C generated code into the temporal output file
generateControllerFiles(sourceFolderPath,deploy,".h",cCodeString,logTopics);
@@ -474,35 +461,27 @@ def generateVirtualS7Sources(paramDOM,sourceFolderPath,logTopics):
blockName = blockDOM.prop('name')
blockOffset = blockDOM.prop('address')
- registerDOMList = blockDOM.xpathEval("Register") # get Registers of the current block
createBlockCodeString += virtualS7Template.vs7ClassCreateBlock(className, blockName)
deleteBlockCodeString += virtualS7Template.vs7ClassDeleteBlock(className, blockName)
- for registerIndex, registerDOM in enumerate(registerDOMList):
- registerName = registerDOM.prop('name')
- registerFormat = registerDOM.prop('format')
- registerDimension1 = long(registerDOM.prop('array-dim1'))
- registerDimension2 = long(registerDOM.prop('array-dim2'))
- registerMemSize = long(registerDOM.prop('mem-size')) #store the reigster mem-size for next iteration
-
- registerLength = 1 #in case string
- if(registerFormat == 'string'):
- registerLength = long(registerDOM.prop('string-len'))
+ for registerDOM in blockDOM.xpathEval("Register"):
+ register = ParamRegister()
+ register.initWithParamRegisterNode(registerDOM)
- getSetCodeString += virtualS7Template.vs7ClassGetSet(registerName, registerFormat, registerDimension1, registerDimension2,registerLength)
- dimsCodeString += virtualS7Template.vs7ClassDimension(registerName, registerFormat, registerDimension1, registerDimension2,registerLength)
+ getSetCodeString += virtualS7Template.vs7ClassGetSet(register.name, register.format, register.dim1, register.dim2,register.stringLength)
+ dimsCodeString += virtualS7Template.vs7ClassDimension(register.name, register.format, register.dim1, register.dim2,register.stringLength)
#Specific code to force 16bit alignment if not scalar 8bit register (==> insert dummy register if needed)
- dummyCodeString = virtualS7Template.vs7ClassDummyRegister(currentRegisterAddress, previousRegisterMemSize, registerMemSize, dummyIndex)
+ dummyCodeString = virtualS7Template.vs7ClassDummyRegister(currentRegisterAddress, previousRegisterMemSize, register.memSize, dummyIndex)
dataCodeString += dummyCodeString
- currentRegisterAddress += registerMemSize
+ currentRegisterAddress += register.memSize
if dummyCodeString != "":
dummyIndex += 1
currentRegisterAddress += 1
#and now insert the normal data register
- dataCodeString += virtualS7Template.vs7ClassDataRegister(registerName, registerFormat, registerDimension1, registerDimension2, registerLength)
- previousRegisterMemSize = registerMemSize
+ dataCodeString += virtualS7Template.vs7ClassDataRegister(register.name, register.format, register.dim1, register.dim2, register.stringLength)
+ previousRegisterMemSize = register.memSize
blocksCodeString += virtualS7Template.vs7ClassBlock(deploy.silecsVersion, deploy.owner, deploy.checksum, className, blockName, getSetCodeString, blockOffset, dimsCodeString, dataCodeString)
@@ -544,38 +523,24 @@ def generateBeckhoffRegisters(classDOM, deviceDOM, blockDOM, deviceIndex, deploy
deviceAddress = long(deviceDOM.prop('address'))
blockAddress = long(blockDOM.prop('address'))
blockMemSize = long(blockDOM.prop('mem-size'))
-
- registerDOMList = blockDOM.xpathEval("Register") # get registers of the current block
- for registerIndex, registerDOM in enumerate(registerDOMList):
- registerName = registerDOM.prop('name')
- registerFormat = registerDOM.prop('format')
- registerDimension1 = long(registerDOM.prop('array-dim1'))
- registerDimension2 = long(registerDOM.prop('array-dim2'))
-
- if registerDOM.prop('string-len'): # only appears for string registers
- registerLength = long(registerDOM.prop('string-len'))
-
- if blockName == 'hdrBlk':
- if registerName == 'ieVersion' or registerName == 'ieUser':
- registerFormat = 'string'
- registerDimension1 = 1
+ for registerDOM in blockDOM.xpathEval("Register"):
+ register = ParamRegister()
+ register.initWithParamRegisterNode(registerDOM)
# If PLC does not supports this register format abort this generation and log the error
- if(registerFormat in ['uint64','int64','float64']):
- iecommon.logError('ERROR: In register '+registerName+', '+registerFormat+' format not supported for current controller model.', True)
+ if(register.format in ['uint64','int64','float64']):
+ iecommon.logError('ERROR: In register '+register.name+', '+register.format+' format not supported for current controller model.', True)
return
- #register has relative address irrespective of the protocol mode.
- registerOffset = long(registerDOM.prop('address'))
- iecommon.logDebug("Processing: %s %s %s %s" %(className, deviceLabel, blockName, registerName))
+ iecommon.logDebug("Processing: %s %s %s %s" %(className, deviceLabel, blockName, register.name))
# Compute the register address relying on the Class Parameters file data
# Attention! Beckhoff uses WORD addressing while Parameters data are expressed in bytes to be PLC independent
if deploy.plcModel == 'BC9020':
- registerAddress = (blockAddress - long(deploy.address) + (deviceIndex * blockMemSize) + registerOffset)/2
+ totalAddress = (blockAddress - long(deploy.address) + (deviceIndex * blockMemSize) + register.address)/2
elif deploy.plcModel == 'CX9020':
- registerAddress = (blockAddress - long(deploy.address) + (deviceIndex * blockMemSize) + registerOffset)
+ totalAddress = (blockAddress - long(deploy.address) + (deviceIndex * blockMemSize) + register.address)
else:
raise "PLC model not supported: " + deploy.plcModel
@@ -586,28 +551,28 @@ def generateBeckhoffRegisters(classDOM, deviceDOM, blockDOM, deviceIndex, deploy
classNameCRC = zlib.crc32(className,0) & 0xffff
if blockName == 'hdrBlk':
- if registerName == '_version':
- source+=beckhoffRegInit %(registerName, classNameCRC, deviceLabel, registerAddress, whichTwincatFormat[registerFormat]+"(16)", deploy.silecsVersion )
- if registerName == '_user':
- source+=beckhoffRegInit %(registerName, classNameCRC, deviceLabel, registerAddress, whichTwincatFormat[registerFormat]+"(16)", "'"+deploy.owner+"'")
- if registerName == '_checksum':
- source+=beckhoffRegInit %(registerName, classNameCRC, deviceLabel, registerAddress, whichTwincatFormat[registerFormat], deploy.checksum)
- if registerName == '_date':
- source+=beckhoffRegInit %(registerName, classNameCRC, deviceLabel, registerAddress, whichTwincatFormat[registerFormat], getDateTime())
+ if register.name == '_version':
+ source+=beckhoffRegInit %(register.name, classNameCRC, deviceLabel, totalAddress, whichTwincatFormat[register.format]+"(16)", deploy.silecsVersion )
+ if register.name == '_user':
+ source+=beckhoffRegInit %(register.name, classNameCRC, deviceLabel, totalAddress, whichTwincatFormat[register.format]+"(16)", "'"+deploy.owner+"'")
+ if register.name == '_checksum':
+ source+=beckhoffRegInit %(register.name, classNameCRC, deviceLabel, totalAddress, whichTwincatFormat[register.format], deploy.checksum)
+ if register.name == '_date':
+ source+=beckhoffRegInit %(register.name, classNameCRC, deviceLabel, totalAddress, whichTwincatFormat[register.format], getDateTime())
else: # not header block
# set data type - for string with fixed value registerLength
- if registerFormat == 'string':
- format = whichTwincatFormat[registerFormat]+'('+str(registerLength)+')'
+ if register.format == 'string':
+ format = whichTwincatFormat[register.format]+'('+str(register.stringLength)+')'
else:
- format = whichTwincatFormat[registerFormat]
+ format = whichTwincatFormat[register.format]
- if registerDimension1 == 1 and registerDimension2 == 1: # scalar
- source += beckhoffReg %(registerName, classNameCRC, deviceLabel, registerAddress, format)
- elif registerDimension1 > 1 and registerDimension2 == 1: # array
- source += beckhoffRegArray %(registerName, classNameCRC, deviceLabel, registerAddress, registerDimension1-1, format)
+ if register.dim1 == 1 and register.dim2 == 1: # scalar
+ source += beckhoffReg %(register.name, classNameCRC, deviceLabel, totalAddress, format)
+ elif register.dim1 > 1 and register.dim2 == 1: # array
+ source += beckhoffRegArray %(register.name, classNameCRC, deviceLabel, totalAddress, register.dim1-1, format)
else: # dim1>=1 and for whatever dim2, use double array syntax
- source += beckhoffRegArray2d %(registerName, classNameCRC, deviceLabel, registerAddress, registerDimension1-1, registerDimension2-1, format)
+ source += beckhoffRegArray2d %(register.name, classNameCRC, deviceLabel, totalAddress, register.dim1-1, register.dim2-1, format)
return source
# ----------------------------------------------------
diff --git a/silecs-codegen/src/xml/iecommon.py b/silecs-codegen/src/xml/iecommon.py
index ab625ff..65cb502 100644
--- a/silecs-codegen/src/xml/iecommon.py
+++ b/silecs-codegen/src/xml/iecommon.py
@@ -61,6 +61,16 @@ def logToFile(path,msg):
#-------------------------------------------------------------------------
# General XML Parsing
#-------------------------------------------------------------------------
+
+def xsdBooleanToBoolean(value):
+ # Remove trailing and leading whitespaces
+ value = value.strip()
+ if value == 'true' or value == '1':
+ return True
+ elif value == 'false' or value == '0':
+ return False
+ raise ValueError(value + ' is not a valid xsd:boolean value')
+
def hasChildren(element):
children = element.xpathEval("*")
if len(children):
@@ -145,7 +155,7 @@ def fillAttributes(element, attrs):
# so here unsigned types are considered as signed to allow users to link
# any field to properties
#-------------------------------------------------------------------------
-def getFesaDataType(type):
+def getFesaDataType(silecsDataType):
return {
'int8' :'int8_t',
'uint8' :'int16_t',
@@ -167,9 +177,13 @@ def getFesaDataType(type):
'real' :'float',
'dt' :'double',
'string' :'char'
- }[type]
+ }[silecsDataType]
+
+def registerFormatType2FesaType(registerFormatType):
+ type = iecommon.getSilecsDataType(registerFormatType)
+ return getFesaDataType(type)
-def getCDataType(type):
+def getCDataType(silecsDataType):
return {
'int8' :'int8_t',
'uint8' :'uint8_t',
@@ -191,12 +205,12 @@ def getCDataType(type):
'real' :'float',
'dt' :'double',
'string' :'std::string'
- }[type]
+ }[silecsDataType]
#-------------------------------------------------------------------------
-# Given data type, returns the corresponding
+# Given PLC data type, returns the corresponding
# SILECS data type
#-------------------------------------------------------------------------
-def getSilecsDataType(type):
+def getSilecsDataType(registerFormatType):
return {
'byte' :'uint8',
'char' :'int8',
@@ -225,7 +239,24 @@ def getSilecsDataType(type):
'float64' :'float64',
'date' :'date',
'string' : 'string'
- }[type]
+ }[registerFormatType]
+
+def isUnsignedType(registerFormatType):
+ type = iecommon.getSilecsDataType(registerFormatType)
+ if type[0] == 'u':
+ return True
+ return False
+#Needed for SilecsMethodNames
+def getSilecsDataTypeUpperCase(registerFormatType):
+ type = iecommon.getSilecsDataType(registerFormatType)
+ typeUpperCase = ""
+ if type[0] == 'u':
+ typeUpperCase = type[:2].upper() + type[2:] # first two characters if unsigned
+ elif type == 'date':
+ typeUpperCase = 'Date'
+ else:
+ typeUpperCase = type[:1].upper() + type[1:] # only first character if not unsigned
+ return typeUpperCase
def capitalizeString(text):
str = ""
diff --git a/silecs-codegen/src/xml/migration/0_10_0to1_0_0.py b/silecs-codegen/src/xml/migration/0_10_0to1_0_0.py
index 775ffdb..eca47e5 100644
--- a/silecs-codegen/src/xml/migration/0_10_0to1_0_0.py
+++ b/silecs-codegen/src/xml/migration/0_10_0to1_0_0.py
@@ -41,32 +41,6 @@ class Migration(MigrationBase):
self.migrateFESAInstanceFile()
return modified
- def backupOldFESAMakeSpecific(self):
- results = self.parser.parse_args()
- silecsDocument = results.silecsDocument
- projectDir = FileUtils.getProjectDir(silecsDocument)
- makeSpecific = projectDir + "/Makefile.specific"
- if os.path.isfile(makeSpecific):
- os.rename(makeSpecific, makeSpecific + ".backup")
- print("Backed up old FESA Make.specific file: " + makeSpecific)
-
- def removeGenCode(self):
- results = self.parser.parse_args()
- silecsDocument = results.silecsDocument
- projectDir = FileUtils.getProjectDir(silecsDocument)
- clientFolder = projectDir + "/generated/client"
- controllerFolder = projectDir + "/generated/controller"
- wrapperFolder = projectDir + "/generated/wrapper"
- if os.path.isdir(clientFolder):
- shutil.rmtree(clientFolder)
- print("removed generation folder: " + clientFolder)
- if os.path.isdir(controllerFolder):
- shutil.rmtree(controllerFolder)
- print("removed generation folder: " + controllerFolder)
- if os.path.isdir(wrapperFolder):
- shutil.rmtree(wrapperFolder)
- print("removed generation folder: " + wrapperFolder)
-
def migrateFESAInstanceFile(self):
results = self.parser.parse_args()
silecsDocument = results.silecsDocument
diff --git a/silecs-codegen/src/xml/migration/1_0_Xto1_1_0.py b/silecs-codegen/src/xml/migration/1_0_Xto1_1_0.py
new file mode 100644
index 0000000..5abb317
--- /dev/null
+++ b/silecs-codegen/src/xml/migration/1_0_Xto1_1_0.py
@@ -0,0 +1,40 @@
+#!/usr/bin/python
+# Copyright 2016 CERN and GSI
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+import os
+import sys
+
+from migrationBase import MigrationBase
+from migration1_0_Xto1_1_0.migrators import *
+
+import libxml2
+import sys
+import FileUtils
+import shutil
+
+class Migration(MigrationBase):
+ def __init__(self, arguments):
+ super(Migration, self).__init__()
+
+ def migrateClass(self, context, projectDir ):
+ modified = designValueTypeMigrator(context)
+ return modified
+
+
+if __name__ == "__main__":
+ migration = Migration(sys.argv)
+ migration.migrate()
+ migration.backupOldFESAMakeSpecific()
diff --git a/silecs-codegen/src/xml/migration/migration1_0_Xto1_1_0/__init__.py b/silecs-codegen/src/xml/migration/migration1_0_Xto1_1_0/__init__.py
new file mode 100644
index 0000000..e69de29
diff --git a/silecs-codegen/src/xml/migration/migration1_0_Xto1_1_0/migrators.py b/silecs-codegen/src/xml/migration/migration1_0_Xto1_1_0/migrators.py
new file mode 100644
index 0000000..f4d3eb2
--- /dev/null
+++ b/silecs-codegen/src/xml/migration/migration1_0_Xto1_1_0/migrators.py
@@ -0,0 +1,66 @@
+#!/usr/bin/python
+# Copyright 2016 CERN and GSI
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+import libxml2
+
+def designValueTypeMigrator(context):
+ modified = False
+ for register in context.xpathEval("//Register"):
+ format = register.prop("format")
+ register.unsetProp("format")
+ dim1 = "1"
+ dim2 = "1"
+ stringLength ="64" #thats the default
+
+ if register.hasProp("string-len"):
+ stringLength = register.prop("string-len")
+ register.unsetProp("string-len")
+ if register.hasProp("array-dim1"):
+ dim1 = register.prop("array-dim1")
+ register.unsetProp("array-dim1")
+ if register.hasProp("array-dim2"):
+ dim2 = register.prop("array-dim2")
+ register.unsetProp("array-dim2")
+
+ valueType = None
+ if(format == 'string'):
+ if int(dim1) > 1:
+ if int(dim2) > 1:
+ valueType = libxml2.newNode("stringArray2D")
+ valueType.newProp("dim1",dim1)
+ valueType.newProp("dim2",dim2)
+ else:
+ valueType = libxml2.newNode("stringArray")
+ valueType.newProp("dim",dim1)
+ else:
+ valueType = libxml2.newNode("string")
+ valueType.newProp("string-length",stringLength)
+ else:
+ if int(dim1) > 1:
+ if int(dim2) > 1:
+ valueType = libxml2.newNode("array2D")
+ valueType.newProp("dim1",dim1)
+ valueType.newProp("dim2",dim2)
+ else:
+ valueType = libxml2.newNode("array")
+ valueType.newProp("dim",dim1)
+ else:
+ valueType = libxml2.newNode("scalar")
+ valueType.newProp("format",format)
+ register.addChild(valueType)
+ modified = True
+ return modified
+
diff --git a/silecs-codegen/src/xml/migration/migration1_0_Xto1_1_0/testMigration.py b/silecs-codegen/src/xml/migration/migration1_0_Xto1_1_0/testMigration.py
new file mode 100644
index 0000000..bebf4bb
--- /dev/null
+++ b/silecs-codegen/src/xml/migration/migration1_0_Xto1_1_0/testMigration.py
@@ -0,0 +1,70 @@
+#!/usr/bin/python
+# Copyright 2016 CERN and GSI
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+from test.testBase import *
+
+import libxml2
+#from migration.0_10_0to1_0_0 import *
+from migration.migration1_0_Xto1_1_0.migrators import *
+import inspect #get caller name
+
+SilecsDesignOld = '''<?xml version="1.0" encoding="UTF-8"?>
+<SILECS-Design xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ silecs-version="0.10.0" created="03/21/16" updated="03/21/16"
+ xsi:noNamespaceSchemaLocation="/common/usr/cscofe/silecs/0.10.0/silecs-model/src/xml/DesignSchema.xsd">
+ <Information>
+ <Owner user-login="schwinn" />
+ <Editor user-login="schwinn" />
+ </Information>
+ <SILECS-Class name="PneuDrive" version="0.1.0" domain="TEST">
+ <Block name="Acq" mode="READ-ONLY">
+ <Register name="string1" synchro="MASTER" format="string" />
+ <Register name="string2" synchro="MASTER" format="string" string-len="65"/>
+ <Register name="string1D" synchro="MASTER" format="string" array-dim1="2" />
+ <Register name="string2D" synchro="MASTER" format="string" array-dim1="2" array-dim2="4"/>
+ <Register name="scalar" synchro="MASTER" format="int8" />
+ <Register name="scalar1D" synchro="MASTER" format="int8" array-dim1="2" />
+ <Register name="scalar2D" synchro="MASTER" format="int8" array-dim1="2" array-dim2="4"/>
+ </Block>
+ </SILECS-Class>
+</SILECS-Design>'''
+SilecsDesignOldParsed = libxml2.parseDoc(SilecsDesignOld)
+
+
+def testdesignValueTypeMigrator(context):
+ designValueTypeMigrator(context)
+ #context.shellPrintNode() #for debug
+ scalar = context.xpathEval("//Register[not(@format)]/scalar[@format='int8']")
+ array = context.xpathEval("//Register[not(@array-dim1)]/array[@dim='2' and @format='int8']")
+ array2D = context.xpathEval("//Register[not(@array-dim2)]/array2D[@dim1='2' and @dim2='4' and @format='int8']")
+ string1 = context.xpathEval("//Register/string[@format='string' and @string-length='64']")
+ string2 = context.xpathEval("//Register[not(@string-len)]/string[@format='string' and @string-length='65']")
+ stringArray = context.xpathEval("//Register/stringArray[@dim='2' and @format='string' and @string-length='64']")
+ stringArray2D = context.xpathEval("//Register/stringArray2D[@dim1='2' and @dim2='4' and @format='string' and @string-length='64']")
+
+
+ assertEqual(len(scalar),1)
+ assertEqual(len(array),1)
+ assertEqual(len(array2D),1)
+ assertEqual(len(string1),1)
+ assertEqual(len(string2),1)
+ assertEqual(len(stringArray),1)
+ assertEqual(len(stringArray2D),1)
+
+
+def runTests():
+ testdesignValueTypeMigrator(SilecsDesignOldParsed)
+ # print deployDoc # for debugging
diff --git a/silecs-codegen/src/xml/migration/migrationBase.py b/silecs-codegen/src/xml/migration/migrationBase.py
index a35e2aa..dd53b60 100644
--- a/silecs-codegen/src/xml/migration/migrationBase.py
+++ b/silecs-codegen/src/xml/migration/migrationBase.py
@@ -44,6 +44,32 @@ class MigrationBase(object):
root.setProp("xsi:noNamespaceSchemaLocation",xmlSchema)
print("Info: Replaced old silecs-xmlSchema")
+ def backupOldFESAMakeSpecific(self):
+ results = self.parser.parse_args()
+ silecsDocument = results.silecsDocument
+ projectDir = FileUtils.getProjectDir(silecsDocument)
+ makeSpecific = projectDir + "/Makefile.specific"
+ if os.path.isfile(makeSpecific):
+ os.rename(makeSpecific, makeSpecific + ".backup")
+ print("Backed up old FESA Make.specific file: " + makeSpecific)
+
+ def removeGenCode(self):
+ results = self.parser.parse_args()
+ silecsDocument = results.silecsDocument
+ projectDir = FileUtils.getProjectDir(silecsDocument)
+ clientFolder = projectDir + "/generated/client"
+ controllerFolder = projectDir + "/generated/controller"
+ wrapperFolder = projectDir + "/generated/wrapper"
+ if os.path.isdir(clientFolder):
+ shutil.rmtree(clientFolder)
+ print("removed generation folder: " + clientFolder)
+ if os.path.isdir(controllerFolder):
+ shutil.rmtree(controllerFolder)
+ print("removed generation folder: " + controllerFolder)
+ if os.path.isdir(wrapperFolder):
+ shutil.rmtree(wrapperFolder)
+ print("removed generation folder: " + wrapperFolder)
+
def migrate(self):
results = self.parser.parse_args()
silecsDocument = results.silecsDocument
diff --git a/silecs-codegen/src/xml/migration/runTests.py b/silecs-codegen/src/xml/migration/runTests.py
index 86c7e16..e440c55 100644
--- a/silecs-codegen/src/xml/migration/runTests.py
+++ b/silecs-codegen/src/xml/migration/runTests.py
@@ -17,6 +17,7 @@
from test.testBase import *
import migration.migration_0_9_0to0_10_0.testMigration
import migration.migration0_10_0to1_0_0.testMigration
+import migration.migration1_0_Xto1_1_0.testMigration
SilecsDeployOld = '''<?xml version="1.0" encoding="UTF-8"?>
<SILECS-Deploy silecs-version="oldVersion" created="03/04/16" updated="03/04/16"
@@ -46,4 +47,5 @@ def runAllTests():
# runbaseTests()
migration.migration_0_9_0to0_10_0.testMigration.runTests()
migration.migration0_10_0to1_0_0.testMigration.runTests()
+ migration.migration1_0_Xto1_1_0.testMigration.runTests()
allTestsOk()
diff --git a/silecs-codegen/src/xml/model/Register.py b/silecs-codegen/src/xml/model/Register.py
new file mode 100644
index 0000000..06566c0
--- /dev/null
+++ b/silecs-codegen/src/xml/model/Register.py
@@ -0,0 +1,103 @@
+#!/usr/bin/python
+# Copyright 2016 CERN and GSI
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+from iecommon import *
+import libxml2
+
+class Register(object):
+
+ def __init__(self, xmlNode):
+ self.initWithDesignRegisterNode(xmlNode)
+
+ def initWithDesignRegisterNode(self, xmlNode):
+ self.xmlNode = xmlNode
+
+ #xmlNode.shellPrintNode()
+ self.name = xmlNode.prop("name")
+ self.syncro = xmlNode.prop("synchro")
+
+ valueTypes = xmlNode.xpathEval("*[name()='scalar' or name()='array' or name()='array2D' or name()='string' or name()='stringArray' or name()='stringArray2D']")
+ if not valueTypes:
+ iecommon.logError('ERROR: The register '+ self.name +' has no valueTypes.', True, {'errorlog': True})
+ if len(valueTypes) < 1:
+ iecommon.logError('ERROR: The register '+ self.name +' has no valueTypes.', True, {'errorlog': True})
+ if len(valueTypes) > 1:
+ iecommon.logError('ERROR: The register '+ self.name +' has multiple valueTypes.', True, {'errorlog': True})
+ self.valueTypeNode = valueTypes[0]
+ self.valueType = self.valueTypeNode.get_name()
+
+ self.dim1 = 1
+ self.dim2 = 1
+ self.stringLength = 1 # ... currently needs to be default because of some old convention
+
+ if self.valueTypeNode.hasProp("dim1"):
+ self.dim1 = long(self.valueTypeNode.prop("dim1"))
+ elif self.valueTypeNode.hasProp("dim"):
+ self.dim1 = long(self.valueTypeNode.prop("dim"))
+
+ if self.valueTypeNode.hasProp("dim2"):
+ self.dim2 = long(self.valueTypeNode.prop("dim2"))
+
+ if self.valueTypeNode.hasProp("string-length"):
+ self.stringLength = long(self.valueTypeNode.prop("string-length"))
+
+ self.format = self.valueTypeNode.prop("format")
+
+ def isArray(self):
+ return self.valueType == 'array' or 'stringArray'
+
+ def isArray2D(self):
+ return self.valueType == 'array2D' or 'stringArray2D'
+
+#has some additionalValues
+class ParamRegister(Register):
+ def __init__(self):
+ self.size = 0
+ self.address = 0
+ self.memSize = 0
+
+ def initWithParamRegisterNode(self, xmlNode):
+ super(ParamRegister, self).__init__(xmlNode)
+ self.size = long(self.xmlNode.prop("size"))
+ self.address = long(self.xmlNode.prop("address"))
+ self.memSize = long(self.xmlNode.prop("mem-size"))
+
+ def initWithDesignRegister(self, designRegister,size,address,memSize):
+ newNodeTree = designRegister.xmlNode.copyNode(1) # 1 is for recursive copy
+ if ( newNodeTree == None ):
+ iecommon.logError('ERROR: Failed to copy register node: '+ designRegister.name +'.', True, {'errorlog': True})
+ newNodeTree.shellPrintNode()
+ super(ParamRegister, self).__init__(designRegister.xmlNode)
+ self.xmlNode = newNodeTree
+ newNodeTree.setProp("size", size)
+ self.size = long(size)
+ newNodeTree.setProp("address", str(address))
+ self.address = address
+ newNodeTree.setProp("mem-size", str(memSize))
+ self.memSize = memSize
+
+
+class DesignRegister(Register):
+ def __init__(self, xmlNode):
+ super(DesignRegister, self).__init__(xmlNode)
+ self.fesaFieldName = ""
+ if self.xmlNode.hasProp("fesaFieldName"):
+ self.fesaFieldName = xmlNode.prop("fesaFieldName")
+ self.generateFesaValueItem = xsdBooleanToBoolean(xmlNode.prop("generateFesaValueItem"))
+ def getFesaName(self):
+ if self.fesaFieldName == "":
+ return self.name
+ return self.fesaFieldName
diff --git a/silecs-codegen/src/xml/model/__init__.py b/silecs-codegen/src/xml/model/__init__.py
new file mode 100644
index 0000000..e69de29
diff --git a/silecs-codegen/src/xml/runTests.py b/silecs-codegen/src/xml/runTests.py
index 47bbe88..ed9aa0c 100644
--- a/silecs-codegen/src/xml/runTests.py
+++ b/silecs-codegen/src/xml/runTests.py
@@ -29,6 +29,7 @@ import test.general.genParamTest
import test.general.genDuWrapperTest
def runTests():
+ migration.runTests.runAllTests()
test.fesa.fillFESADeployUnitTest.runTests()
test.fesa.generateFesaDesignTest.runTests()
test.fesa.generateSourceCodeTest.runTests()
@@ -36,7 +37,7 @@ def runTests():
test.general.genParamTest.runTests()
test.general.genplcsrcTest.runTests()
test.general.genDuWrapperTest.runTests()
- migration.runTests.runAllTests()
+
print "################################################"
print "# Test suite finished - no failures detected ! #"
diff --git a/silecs-codegen/src/xml/test/AllTypes.silecsdesign b/silecs-codegen/src/xml/test/AllTypes.silecsdesign
index c9e16e9..8b41ca0 100644
--- a/silecs-codegen/src/xml/test/AllTypes.silecsdesign
+++ b/silecs-codegen/src/xml/test/AllTypes.silecsdesign
@@ -1,77 +1,177 @@
<?xml version="1.0" encoding="UTF-8"?>
-<SILECS-Design silecs-version="0.10.0" created="06/27/16" updated="06/27/16"
- xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
- xsi:noNamespaceSchemaLocation="/common/home/bel/schwinn/lnx/git/silecs-model/src/xml/DesignSchema.xsd">
- <Information>
- <Owner user-login="schwinn"/>
- <Editor user-login="schwinn"/>
- </Information>
- <SILECS-Class name="AllTypes" version="0.1.0" domain="OPERATIONAL" >
- <Block name="MyROBlock" mode="READ-ONLY" generateFesaProperty="true" fesaPropertyName="MyROBlockProp">
- <Register name="RO_int8" format="int8" synchro="MASTER" generateFesaValueItem="true"/>
- <Register name="RO_uint8" format="uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa"/>
- <Register name="RO_int16" format="int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa"/>
- <Register name="RO_uint16" format="uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa"/>
- <Register name="RO_int32" format="int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa"/>
- <Register name="RO_uint32" format="uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa"/>
- <!--<Register name="RO_int64" format="int64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int64_fesa"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider-->
- <!--<Register name="RO_uint64" format="uint64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint64_fesa"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider-->
- <Register name="RO_float32" format="float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa"/>
- <!--<Register name="RO_float64" format="float64" synchro="MASTER" generateFesaValueItem="true" esaFieldName="RO_float64_fesa"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider-->
- <Register name="RO_string" format="string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_string_fesa"/>
- <Register name="RO_date" format="date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_date_fesa"/>
- <Register name="RO_char" format="char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_char_fesa"/>
- <Register name="RO_byte" format="byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa"/>
- <Register name="RO_word" format="word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_word_fesa"/>
- <Register name="RO_dword" format="dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa"/>
- <Register name="RO_int" format="int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int_fesa"/>
- <Register name="RO_dint" format="dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa"/>
- <Register name="RO_real" format="real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_real_fesa"/>
- <Register name="RO_dt" format="dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa"/>
- </Block>
- <Block name="MyRWBlock" generateFesaProperty="true" fesaPropertyName="MyRWBlockProp" mode="READ-WRITE">
- <Register name="RW_int8" format="int8" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2" />
- <Register name="RW_uint8" format="uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_int16" format="int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_uint16" format="uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_int32" format="int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_uint32" format="uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" array-dim1="2" array-dim2="2"/>
- <!--<Register name="RW_int64" format="int64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int64_fesa" array-dim1="2" array-dim2="2"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider-->
- <!--<Register name="RW_uint64" format="uint64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint64_fesa" array-dim1="2" array-dim2="2"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider-->
- <Register name="RW_float32" format="float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" array-dim1="2" array-dim2="2"/>
- <!--<Register name="RW_float64" format="float64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float64_fesa" array-dim1="2" array-dim2="2"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider-->
- <Register name="RW_string" format="string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_date" format="date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_char" format="char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_byte" format="byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_word" format="word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_dword" format="dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_int" format="int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_dint" format="dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_real" format="real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_dt" format="dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" array-dim1="2" array-dim2="2"/>
- </Block>
- <Block name="MyWOBlock" generateFesaProperty="true" fesaPropertyName="MyWOBlockProp" mode="WRITE-ONLY">
- <Register name="WO_int8" format="int8" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_uint8" format="uint8" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" array-dim1="10"/>
- <Register name="WO_int16" format="int16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" array-dim1="10"/>
- <Register name="WO_uint16" format="uint16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" array-dim1="10"/>
- <Register name="WO_int32" format="int32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" array-dim1="10"/>
- <Register name="WO_uint32" format="uint32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" array-dim1="10"/>
- <!--<Register name="WO_int64" format="int64" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int64_fesa" array-dim1="10"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider-->
- <!--<Register name="WO_uint64" format="uint64" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint64_fesa" array-dim1="10"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider-->
- <Register name="WO_float32" format="float32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" array-dim1="10"/>
- <!--<Register name="WO_float64" format="float64" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float64_fesa" array-dim1="10"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider-->
- <Register name="WO_string" format="string" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" array-dim1="10"/>
- <Register name="WO_date" format="date" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" array-dim1="10"/>
- <Register name="WO_char" format="char" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" array-dim1="10"/>
- <Register name="WO_byte" format="byte" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" array-dim1="10"/>
- <Register name="WO_word" format="word" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" array-dim1="10"/>
- <Register name="WO_dword" format="dword" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" array-dim1="10"/>
- <Register name="WO_int" format="int" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" array-dim1="10"/>
- <Register name="WO_dint" format="dint" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" array-dim1="10"/>
- <Register name="WO_real" format="real" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" array-dim1="10"/>
- <Register name="WO_dt" format="dt" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" array-dim1="10"/>
- </Block>
- </SILECS-Class>
+<SILECS-Design xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" silecs-version="1.1.0" created="06/27/16" updated="06/27/16" xsi:noNamespaceSchemaLocation="/common/home/bel/schwinn/lnx/git/silecs-model/src/xml/DesignSchema.xsd">
+ <Information>
+ <Owner user-login="schwinn" />
+ <Editor user-login="schwinn" />
+ </Information>
+ <SILECS-Class name="AllTypes" version="0.1.0" domain="OPERATIONAL">
+ <Block name="MyROBlock" mode="READ-ONLY" generateFesaProperty="true" fesaPropertyName="MyROBlockProp">
+ <Register name="RO_int8" synchro="MASTER" generateFesaValueItem="true">
+ <scalar format="int8" />
+ </Register>
+ <Register name="RO_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa">
+ <scalar format="uint8" />
+ </Register>
+ <Register name="RO_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa">
+ <scalar format="int16" />
+ </Register>
+ <Register name="RO_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa">
+ <scalar format="uint16" />
+ </Register>
+ <Register name="RO_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa">
+ <scalar format="int32" />
+ </Register>
+ <Register name="RO_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa">
+ <scalar format="uint32" />
+ </Register>
+ <!--<Register name="RO_int64" format="int64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int64_fesa"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <!--<Register name="RO_uint64" format="uint64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint64_fesa"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <Register name="RO_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa">
+ <scalar format="float32" />
+ </Register>
+ <!--<Register name="RO_float64" format="float64" synchro="MASTER" generateFesaValueItem="true" esaFieldName="RO_float64_fesa"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <Register name="RO_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_string_fesa">
+ <string string-length="64" format="string" />
+ </Register>
+ <Register name="RO_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_date_fesa">
+ <scalar format="date" />
+ </Register>
+ <Register name="RO_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_char_fesa">
+ <scalar format="char" />
+ </Register>
+ <Register name="RO_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa">
+ <scalar format="byte" />
+ </Register>
+ <Register name="RO_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_word_fesa">
+ <scalar format="word" />
+ </Register>
+ <Register name="RO_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa">
+ <scalar format="dword" />
+ </Register>
+ <Register name="RO_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int_fesa">
+ <scalar format="int" />
+ </Register>
+ <Register name="RO_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa">
+ <scalar format="dint" />
+ </Register>
+ <Register name="RO_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_real_fesa">
+ <scalar format="real" />
+ </Register>
+ <Register name="RO_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa">
+ <scalar format="dt" />
+ </Register>
+ </Block>
+ <Block name="MyRWBlock" generateFesaProperty="true" fesaPropertyName="MyRWBlockProp" mode="READ-WRITE">
+ <Register name="RW_int8" synchro="MASTER" generateFesaValueItem="true">
+ <array2D dim1="2" dim2="2" format="int8" />
+ </Register>
+ <Register name="RW_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa">
+ <array2D dim1="2" dim2="2" format="uint8" />
+ </Register>
+ <Register name="RW_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa">
+ <array2D dim1="2" dim2="2" format="int16" />
+ </Register>
+ <Register name="RW_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa">
+ <array2D dim1="2" dim2="2" format="uint16" />
+ </Register>
+ <Register name="RW_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa">
+ <array2D dim1="2" dim2="2" format="int32" />
+ </Register>
+ <Register name="RW_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa">
+ <array2D dim1="2" dim2="2" format="uint32" />
+ </Register>
+ <!--<Register name="RW_int64" format="int64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int64_fesa" array-dim1="2" array-dim2="2"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <!--<Register name="RW_uint64" format="uint64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint64_fesa" array-dim1="2" array-dim2="2"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <Register name="RW_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa">
+ <array2D dim1="2" dim2="2" format="float32" />
+ </Register>
+ <!--<Register name="RW_float64" format="float64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float64_fesa" array-dim1="2" array-dim2="2"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <Register name="RW_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_string_fesa">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string" />
+ </Register>
+ <Register name="RW_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_date_fesa">
+ <array2D dim1="2" dim2="2" format="date" />
+ </Register>
+ <Register name="RW_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_char_fesa">
+ <array2D dim1="2" dim2="2" format="char" />
+ </Register>
+ <Register name="RW_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa">
+ <array2D dim1="2" dim2="2" format="byte" />
+ </Register>
+ <Register name="RW_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_word_fesa">
+ <array2D dim1="2" dim2="2" format="word" />
+ </Register>
+ <Register name="RW_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa">
+ <array2D dim1="2" dim2="2" format="dword" />
+ </Register>
+ <Register name="RW_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int_fesa">
+ <array2D dim1="2" dim2="2" format="int" />
+ </Register>
+ <Register name="RW_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa">
+ <array2D dim1="2" dim2="2" format="dint" />
+ </Register>
+ <Register name="RW_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_real_fesa">
+ <array2D dim1="2" dim2="2" format="real" />
+ </Register>
+ <Register name="RW_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa">
+ <array2D dim1="2" dim2="2" format="dt" />
+ </Register>
+ </Block>
+ <Block name="MyWOBlock" generateFesaProperty="true" fesaPropertyName="MyWOBlockProp" mode="WRITE-ONLY">
+ <Register name="WO_int8" synchro="SLAVE" generateFesaValueItem="true">
+ <array dim="10" format="int8" />
+ </Register>
+ <Register name="WO_uint8" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa">
+ <array dim="10" format="uint8" />
+ </Register>
+ <Register name="WO_int16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa">
+ <array dim="10" format="int16" />
+ </Register>
+ <Register name="WO_uint16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa">
+ <array dim="10" format="uint16" />
+ </Register>
+ <Register name="WO_int32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa">
+ <array dim="10" format="int32" />
+ </Register>
+ <Register name="WO_uint32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa">
+ <array dim="10" format="uint32" />
+ </Register>
+ <!--<Register name="WO_int64" format="int64" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int64_fesa" array-dim1="10"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <!--<Register name="WO_uint64" format="uint64" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint64_fesa" array-dim1="10"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <Register name="WO_float32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa">
+ <array dim="10" format="float32" />
+ </Register>
+ <!--<Register name="WO_float64" format="float64" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float64_fesa" array-dim1="10"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <Register name="WO_string" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_string_fesa">
+ <stringArray dim="10" string-length="64" format="string" />
+ </Register>
+ <Register name="WO_date" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_date_fesa">
+ <array dim="10" format="date" />
+ </Register>
+ <Register name="WO_char" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_char_fesa">
+ <array dim="10" format="char" />
+ </Register>
+ <Register name="WO_byte" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa">
+ <array dim="10" format="byte" />
+ </Register>
+ <Register name="WO_word" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_word_fesa">
+ <array dim="10" format="word" />
+ </Register>
+ <Register name="WO_dword" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa">
+ <array dim="10" format="dword" />
+ </Register>
+ <Register name="WO_int" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int_fesa">
+ <array dim="10" format="int" />
+ </Register>
+ <Register name="WO_dint" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa">
+ <array dim="10" format="dint" />
+ </Register>
+ <Register name="WO_real" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_real_fesa">
+ <array dim="10" format="real" />
+ </Register>
+ <Register name="WO_dt" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa">
+ <array dim="10" format="dt" />
+ </Register>
+ </Block>
+ </SILECS-Class>
</SILECS-Design>
diff --git a/silecs-codegen/src/xml/test/AllTypesFESA.silecsdesign b/silecs-codegen/src/xml/test/AllTypesFESA.silecsdesign
index 238d245..aa5455d 100644
--- a/silecs-codegen/src/xml/test/AllTypesFESA.silecsdesign
+++ b/silecs-codegen/src/xml/test/AllTypesFESA.silecsdesign
@@ -1,77 +1,175 @@
<?xml version="1.0" encoding="UTF-8"?>
-<SILECS-Design silecs-version="0.10.0" created="06/27/16" updated="06/27/16"
- xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
- xsi:noNamespaceSchemaLocation="/common/home/bel/schwinn/lnx/git/silecs-model/src/xml/DesignSchema.xsd">
- <Information>
- <Owner user-login="schwinn"/>
- <Editor user-login="schwinn"/>
- </Information>
- <SILECS-Class name="AllTypesFESA" version="0.1.0" domain="OPERATIONAL" >
- <Block name="MyROBlock" mode="READ-ONLY" generateFesaProperty="true" fesaPropertyName="MyROBlockProp">
- <Register name="RO_int8" format="int8" synchro="MASTER" generateFesaValueItem="true"/>
- <Register name="RO_uint8" format="uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa"/>
- <Register name="RO_int16" format="int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa"/>
- <Register name="RO_uint16" format="uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa"/>
- <Register name="RO_int32" format="int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa"/>
- <Register name="RO_uint32" format="uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa"/>
- <!--<Register name="RO_int64" format="int64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int64_fesa"/> not Supported for Beckhoff, Siemens and Schneider-->
- <!--<Register name="RO_uint64" format="uint64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint64_fesa"/> not Supported for Beckhoff, Siemens and Schneider-->
- <Register name="RO_float32" format="float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa"/>
- <!--<Register name="RO_float64" format="float64" synchro="MASTER" generateFesaValueItem="true" esaFieldName="RO_float64_fesa"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider-->
- <Register name="RO_string" format="string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_string_fesa"/>
- <Register name="RO_date" format="date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_date_fesa"/>
- <Register name="RO_char" format="char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_char_fesa"/>
- <Register name="RO_byte" format="byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa"/>
- <Register name="RO_word" format="word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_word_fesa"/>
- <Register name="RO_dword" format="dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa"/>
- <Register name="RO_int" format="int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int_fesa"/>
- <Register name="RO_dint" format="dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa"/>
- <Register name="RO_real" format="real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_real_fesa"/>
- <Register name="RO_dt" format="dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa"/>
- </Block>
- <Block name="MyRWBlock" generateFesaProperty="true" fesaPropertyName="MyRWBlockProp" mode="READ-WRITE">
- <Register name="RW_int8" format="int8" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2" />
- <Register name="RW_uint8" format="uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_int16" format="int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_uint16" format="uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_int32" format="int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_uint32" format="uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" array-dim1="2" array-dim2="2"/>
- <!-- <Register name="RW_int64" format="int64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int64_fesa" array-dim1="2" array-dim2="2"/> not Supported for Beckhoff, Siemens and Schneider-->
- <!--<Register name="RW_uint64" format="uint64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint64_fesa" array-dim1="2" array-dim2="2"/> not Supported for Beckhoff, Siemens and Schneider-->
- <Register name="RW_float32" format="float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" array-dim1="2" array-dim2="2"/>
- <!--<Register name="RW_float64" format="float64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float64_fesa" array-dim1="2" array-dim2="2"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider-->
- <!-- <Register name="RW_string" format="string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" array-dim1="2" array-dim2="2"/> 2d string arrays not supported in FESA -->
- <Register name="RW_date" format="date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_char" format="char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_byte" format="byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_word" format="word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_dword" format="dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_int" format="int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_dint" format="dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_real" format="real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" array-dim1="2" array-dim2="2"/>
- <Register name="RW_dt" format="dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" array-dim1="2" array-dim2="2"/>
- </Block>
- <Block name="MyWOBlock" generateFesaProperty="true" fesaPropertyName="MyWOBlockProp" mode="WRITE-ONLY">
- <Register name="WO_int8" format="int8" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_uint8" format="uint8" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" array-dim1="10"/>
- <Register name="WO_int16" format="int16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" array-dim1="10"/>
- <Register name="WO_uint16" format="uint16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" array-dim1="10"/>
- <Register name="WO_int32" format="int32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" array-dim1="10"/>
- <Register name="WO_uint32" format="uint32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" array-dim1="10"/>
- <!--<Register name="WO_int64" format="int64" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int64_fesa" array-dim1="10"/> not Supported for Beckhoff, Siemens and Schneider-->
- <!--<Register name="WO_uint64" format="uint64" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint64_fesa" array-dim1="10"/> not Supported for Beckhoff, Siemens and Schneider-->
- <Register name="WO_float32" format="float32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" array-dim1="10"/>
- <!--<Register name="WO_float64" format="float64" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float64_fesa" array-dim1="10"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider-->
- <Register name="WO_string" format="string" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" array-dim1="10"/>
- <Register name="WO_date" format="date" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" array-dim1="10"/>
- <Register name="WO_char" format="char" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" array-dim1="10"/>
- <Register name="WO_byte" format="byte" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" array-dim1="10"/>
- <Register name="WO_word" format="word" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" array-dim1="10"/>
- <Register name="WO_dword" format="dword" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" array-dim1="10"/>
- <Register name="WO_int" format="int" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" array-dim1="10"/>
- <Register name="WO_dint" format="dint" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" array-dim1="10"/>
- <Register name="WO_real" format="real" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" array-dim1="10"/>
- <Register name="WO_dt" format="dt" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" array-dim1="10"/>
- </Block>
- </SILECS-Class>
+<SILECS-Design xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" silecs-version="1.1.0" created="06/27/16" updated="06/27/16" xsi:noNamespaceSchemaLocation="/common/home/bel/schwinn/lnx/git/silecs-model/src/xml/DesignSchema.xsd">
+ <Information>
+ <Owner user-login="schwinn" />
+ <Editor user-login="schwinn" />
+ </Information>
+ <SILECS-Class name="AllTypesFESA" version="0.1.0" domain="OPERATIONAL">
+ <Block name="MyROBlock" mode="READ-ONLY" generateFesaProperty="true" fesaPropertyName="MyROBlockProp">
+ <Register name="RO_int8" synchro="MASTER" generateFesaValueItem="true">
+ <scalar format="int8" />
+ </Register>
+ <Register name="RO_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa">
+ <scalar format="uint8" />
+ </Register>
+ <Register name="RO_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa">
+ <scalar format="int16" />
+ </Register>
+ <Register name="RO_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa">
+ <scalar format="uint16" />
+ </Register>
+ <Register name="RO_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa">
+ <scalar format="int32" />
+ </Register>
+ <Register name="RO_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa">
+ <scalar format="uint32" />
+ </Register>
+ <!--<Register name="RO_int64" format="int64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int64_fesa"/> not Supported for Beckhoff, Siemens and Schneider -->
+ <!--<Register name="RO_uint64" format="uint64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint64_fesa"/> not Supported for Beckhoff, Siemens and Schneider -->
+ <Register name="RO_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa">
+ <scalar format="float32" />
+ </Register>
+ <!--<Register name="RO_float64" format="float64" synchro="MASTER" generateFesaValueItem="true" esaFieldName="RO_float64_fesa"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <Register name="RO_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_string_fesa">
+ <string string-length="64" format="string" />
+ </Register>
+ <Register name="RO_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_date_fesa">
+ <scalar format="date" />
+ </Register>
+ <Register name="RO_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_char_fesa">
+ <scalar format="char" />
+ </Register>
+ <Register name="RO_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa">
+ <scalar format="byte" />
+ </Register>
+ <Register name="RO_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_word_fesa">
+ <scalar format="word" />
+ </Register>
+ <Register name="RO_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa">
+ <scalar format="dword" />
+ </Register>
+ <Register name="RO_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int_fesa">
+ <scalar format="int" />
+ </Register>
+ <Register name="RO_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa">
+ <scalar format="dint" />
+ </Register>
+ <Register name="RO_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_real_fesa">
+ <scalar format="real" />
+ </Register>
+ <Register name="RO_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa">
+ <scalar format="dt" />
+ </Register>
+ </Block>
+ <Block name="MyRWBlock" generateFesaProperty="true" fesaPropertyName="MyRWBlockProp" mode="READ-WRITE">
+ <Register name="RW_int8" synchro="MASTER" generateFesaValueItem="true">
+ <array2D dim1="2" dim2="2" format="int8" />
+ </Register>
+ <Register name="RW_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa">
+ <array2D dim1="2" dim2="2" format="uint8" />
+ </Register>
+ <Register name="RW_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa">
+ <array2D dim1="2" dim2="2" format="int16" />
+ </Register>
+ <Register name="RW_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa">
+ <array2D dim1="2" dim2="2" format="uint16" />
+ </Register>
+ <Register name="RW_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa">
+ <array2D dim1="2" dim2="2" format="int32" />
+ </Register>
+ <Register name="RW_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa">
+ <array2D dim1="2" dim2="2" format="uint32" />
+ </Register>
+ <!-- <Register name="RW_int64" format="int64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int64_fesa" array-dim1="2" array-dim2="2"/> not Supported for Beckhoff, Siemens and Schneider -->
+ <!--<Register name="RW_uint64" format="uint64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint64_fesa" array-dim1="2" array-dim2="2"/> not Supported for Beckhoff, Siemens and Schneider -->
+ <Register name="RW_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa">
+ <array2D dim1="2" dim2="2" format="float32" />
+ </Register>
+ <!--<Register name="RW_float64" format="float64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float64_fesa" array-dim1="2" array-dim2="2"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <!-- <Register name="RW_string" format="string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" array-dim1="2" array-dim2="2"/> 2d string arrays not supported in FESA -->
+ <Register name="RW_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_date_fesa">
+ <array2D dim1="2" dim2="2" format="date" />
+ </Register>
+ <Register name="RW_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_char_fesa">
+ <array2D dim1="2" dim2="2" format="char" />
+ </Register>
+ <Register name="RW_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa">
+ <array2D dim1="2" dim2="2" format="byte" />
+ </Register>
+ <Register name="RW_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_word_fesa">
+ <array2D dim1="2" dim2="2" format="word" />
+ </Register>
+ <Register name="RW_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa">
+ <array2D dim1="2" dim2="2" format="dword" />
+ </Register>
+ <Register name="RW_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int_fesa">
+ <array2D dim1="2" dim2="2" format="int" />
+ </Register>
+ <Register name="RW_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa">
+ <array2D dim1="2" dim2="2" format="dint" />
+ </Register>
+ <Register name="RW_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_real_fesa">
+ <array2D dim1="2" dim2="2" format="real" />
+ </Register>
+ <Register name="RW_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa">
+ <array2D dim1="2" dim2="2" format="dt" />
+ </Register>
+ </Block>
+ <Block name="MyWOBlock" generateFesaProperty="true" fesaPropertyName="MyWOBlockProp" mode="WRITE-ONLY">
+ <Register name="WO_int8" synchro="SLAVE" generateFesaValueItem="true">
+ <array dim="10" format="int8" />
+ </Register>
+ <Register name="WO_uint8" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa">
+ <array dim="10" format="uint8" />
+ </Register>
+ <Register name="WO_int16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa">
+ <array dim="10" format="int16" />
+ </Register>
+ <Register name="WO_uint16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa">
+ <array dim="10" format="uint16" />
+ </Register>
+ <Register name="WO_int32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa">
+ <array dim="10" format="int32" />
+ </Register>
+ <Register name="WO_uint32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa">
+ <array dim="10" format="uint32" />
+ </Register>
+ <!--<Register name="WO_int64" format="int64" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int64_fesa" array-dim1="10"/> not Supported for Beckhoff, Siemens and Schneider -->
+ <!--<Register name="WO_uint64" format="uint64" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint64_fesa" array-dim1="10"/> not Supported for Beckhoff, Siemens and Schneider -->
+ <Register name="WO_float32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa">
+ <array dim="10" format="float32" />
+ </Register>
+ <!--<Register name="WO_float64" format="float64" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float64_fesa" array-dim1="10"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <Register name="WO_string" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_string_fesa">
+ <stringArray dim="10" string-length="64" format="string" />
+ </Register>
+ <Register name="WO_date" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_date_fesa">
+ <array dim="10" format="date" />
+ </Register>
+ <Register name="WO_char" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_char_fesa">
+ <array dim="10" format="char" />
+ </Register>
+ <Register name="WO_byte" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa">
+ <array dim="10" format="byte" />
+ </Register>
+ <Register name="WO_word" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_word_fesa">
+ <array dim="10" format="word" />
+ </Register>
+ <Register name="WO_dword" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa">
+ <array dim="10" format="dword" />
+ </Register>
+ <Register name="WO_int" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int_fesa">
+ <array dim="10" format="int" />
+ </Register>
+ <Register name="WO_dint" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa">
+ <array dim="10" format="dint" />
+ </Register>
+ <Register name="WO_real" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_real_fesa">
+ <array dim="10" format="real" />
+ </Register>
+ <Register name="WO_dt" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa">
+ <array dim="10" format="dt" />
+ </Register>
+ </Block>
+ </SILECS-Class>
</SILECS-Design>
diff --git a/silecs-codegen/src/xml/test/fesa/generateFesaDesignTest.py b/silecs-codegen/src/xml/test/fesa/generateFesaDesignTest.py
index 1118df7..620f75e 100644
--- a/silecs-codegen/src/xml/test/fesa/generateFesaDesignTest.py
+++ b/silecs-codegen/src/xml/test/fesa/generateFesaDesignTest.py
@@ -32,10 +32,14 @@ simpleSilecsDesign = '''<?xml version="1.0" encoding="UTF-8"?>
</Information>
<SILECS-Class name="Test123" version="0.1.0" domain="OPERATIONAL">
<Block name="Setting" mode="READ-WRITE" generateFesaProperty="true">
- <Register name="mySettingRegister" format="uint8" synchro="MASTER" generateFesaValueItem="true"/>
+ <Register name="mySettingRegister" synchro="MASTER" generateFesaValueItem="true">
+ <scalar format="uint8"/>
+ </Register>
</Block>
<Block name="Acquisition" mode="READ-ONLY" generateFesaProperty="true">
- <Register name="myAcqRegister" format="uint8" synchro="MASTER" generateFesaValueItem="true"/>
+ <Register name="myAcqRegister" synchro="MASTER" generateFesaValueItem="true">
+ <scalar format="uint8"/>
+ </Register>
</Block>
</SILECS-Class>
</SILECS-Design>'''
diff --git a/silecs-codegen/src/xml/test/generated_correct/AllTypes.cpp b/silecs-codegen/src/xml/test/generated_correct/AllTypes.cpp
index ac67399..1ac635b 100644
--- a/silecs-codegen/src/xml/test/generated_correct/AllTypes.cpp
+++ b/silecs-codegen/src/xml/test/generated_correct/AllTypes.cpp
@@ -98,6 +98,7 @@ namespace AllTypes
{
fesa::NoneContext noneContext;
+ AllTypes::MyRWBlock.setPLCDevices(pPLC, serviceLocator, false, &noneContext);
AllTypes::MyWOBlock.setPLCDevices(pPLC, serviceLocator, false, &noneContext);
}
@@ -192,6 +193,8 @@ namespace AllTypes
Silecs::PLC* pPLC = pCluster_->getPLC(pDevice->plcHostName.get(),pDevice->parameterFile.get());
Silecs::Device* pPLCDevice = pPLC->getDevice(pDevice->plcDeviceLabel.get());
Silecs::Register* pRegister = NULL;
+ uint32_t dim1 = 1;
+ uint32_t dim2 = 1;
if (recvNow) pPLCDevice -> recv(blockName_);
@@ -214,7 +217,8 @@ namespace AllTypes
pDevice->RO_dint_fesa.set( pPLCDevice->getRegister("RO_dint")->getValInt32(), pContext);
pDevice->RO_real_fesa.set( pPLCDevice->getRegister("RO_real")->getValFloat32(), pContext);
pDevice->RO_dt_fesa.set( pPLCDevice->getRegister("RO_dt")->getValDate(), pContext);
- }
+ }
+
void MyRWBlock_Type::getOneDevice(Device* pDevice, const bool recvNow, MultiplexingContext* pContext)
{
if( !isInitialized_ )
@@ -327,7 +331,8 @@ namespace AllTypes
dim2 = pRegister->getDimension2();
pDevice->RW_dt_fesa.set(pRegister->getRefDateArray2D(dim1, dim2), dim1, dim2, pContext);
- }
+ }
+
void MyRWBlock_Type::setOneDevice(Device* pDevice, const bool sendNow, MultiplexingContext* pContext)
{
if( !isInitialized_ )
@@ -342,7 +347,6 @@ namespace AllTypes
uint32_t dim2 = 1;
uint32_t fesaDim2;
-
pRegister = pPLCDevice->getRegister("RW_int8");
dim1 = pRegister->getDimension1();
dim2 = pRegister->getDimension2();
@@ -424,8 +428,8 @@ namespace AllTypes
pRegister->setValDateArray2D(pDevice->RW_dt_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
if (sendNow) pPLCDevice->send(blockName_);
+ }
- }
void MyRWBlock_Type::setOneDevice(Device* pDevice, MyRWBlockPropPropertyData& data, bool sendNow, MultiplexingContext* pContext)
{
if( !isInitialized_ )
@@ -440,11 +444,10 @@ namespace AllTypes
uint32_t dim2 = 1;
uint32_t fesaDim2;
-
pRegister = pPLCDevice->getRegister("RW_int8");
dim1 = pRegister->getDimension1();
dim2 = pRegister->getDimension2();
- (_upper}Available()) ? pRegister->setValInt8Array2D(data.RW_int8.get(fesaDim1, fesaDim2), dim1, dim2) :
+ (data.isRW_int8Available()) ? pRegister->setValInt8Array2D(data.RW_int8.get(fesaDim1, fesaDim2), dim1, dim2) :
pRegister->setValInt8Array2D(pDevice->RW_int8.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
pRegister = pPLCDevice->getRegister("RW_uint8");
@@ -456,7 +459,7 @@ namespace AllTypes
pRegister = pPLCDevice->getRegister("RW_int16");
dim1 = pRegister->getDimension1();
dim2 = pRegister->getDimension2();
- (_upper}Available()) ? pRegister->setValInt16Array2D(data.RW_int16_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ (data.isRW_int16_fesaAvailable()) ? pRegister->setValInt16Array2D(data.RW_int16_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
pRegister->setValInt16Array2D(pDevice->RW_int16_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
pRegister = pPLCDevice->getRegister("RW_uint16");
@@ -468,7 +471,7 @@ namespace AllTypes
pRegister = pPLCDevice->getRegister("RW_int32");
dim1 = pRegister->getDimension1();
dim2 = pRegister->getDimension2();
- (_upper}Available()) ? pRegister->setValInt32Array2D(data.RW_int32_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ (data.isRW_int32_fesaAvailable()) ? pRegister->setValInt32Array2D(data.RW_int32_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
pRegister->setValInt32Array2D(pDevice->RW_int32_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
pRegister = pPLCDevice->getRegister("RW_uint32");
@@ -480,19 +483,19 @@ namespace AllTypes
pRegister = pPLCDevice->getRegister("RW_float32");
dim1 = pRegister->getDimension1();
dim2 = pRegister->getDimension2();
- (_upper}Available()) ? pRegister->setValFloat32Array2D(data.RW_float32_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ (data.isRW_float32_fesaAvailable()) ? pRegister->setValFloat32Array2D(data.RW_float32_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
pRegister->setValFloat32Array2D(pDevice->RW_float32_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
pRegister = pPLCDevice->getRegister("RW_date");
dim1 = pRegister->getDimension1();
dim2 = pRegister->getDimension2();
- (_upper}Available()) ? pRegister->setValDateArray2D(data.RW_date_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ (data.isRW_date_fesaAvailable()) ? pRegister->setValDateArray2D(data.RW_date_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
pRegister->setValDateArray2D(pDevice->RW_date_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
pRegister = pPLCDevice->getRegister("RW_char");
dim1 = pRegister->getDimension1();
dim2 = pRegister->getDimension2();
- (_upper}Available()) ? pRegister->setValInt8Array2D(data.RW_char_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ (data.isRW_char_fesaAvailable()) ? pRegister->setValInt8Array2D(data.RW_char_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
pRegister->setValInt8Array2D(pDevice->RW_char_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
pRegister = pPLCDevice->getRegister("RW_byte");
@@ -516,30 +519,30 @@ namespace AllTypes
pRegister = pPLCDevice->getRegister("RW_int");
dim1 = pRegister->getDimension1();
dim2 = pRegister->getDimension2();
- (_upper}Available()) ? pRegister->setValInt16Array2D(data.RW_int_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ (data.isRW_int_fesaAvailable()) ? pRegister->setValInt16Array2D(data.RW_int_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
pRegister->setValInt16Array2D(pDevice->RW_int_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
pRegister = pPLCDevice->getRegister("RW_dint");
dim1 = pRegister->getDimension1();
dim2 = pRegister->getDimension2();
- (_upper}Available()) ? pRegister->setValInt32Array2D(data.RW_dint_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ (data.isRW_dint_fesaAvailable()) ? pRegister->setValInt32Array2D(data.RW_dint_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
pRegister->setValInt32Array2D(pDevice->RW_dint_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
pRegister = pPLCDevice->getRegister("RW_real");
dim1 = pRegister->getDimension1();
dim2 = pRegister->getDimension2();
- (_upper}Available()) ? pRegister->setValFloat32Array2D(data.RW_real_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ (data.isRW_real_fesaAvailable()) ? pRegister->setValFloat32Array2D(data.RW_real_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
pRegister->setValFloat32Array2D(pDevice->RW_real_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
pRegister = pPLCDevice->getRegister("RW_dt");
dim1 = pRegister->getDimension1();
dim2 = pRegister->getDimension2();
- (_upper}Available()) ? pRegister->setValDateArray2D(data.RW_dt_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ (data.isRW_dt_fesaAvailable()) ? pRegister->setValDateArray2D(data.RW_dt_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
pRegister->setValDateArray2D(pDevice->RW_dt_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
if (sendNow) pPLCDevice->send(blockName_);
- }
+ }
void MyWOBlock_Type::setOneDevice(Device* pDevice, const bool sendNow, MultiplexingContext* pContext)
{
@@ -552,7 +555,8 @@ namespace AllTypes
Silecs::Register* pRegister = NULL;
uint32_t dim1 = 1;
uint32_t fesaDim1;
-
+ uint32_t dim2 = 1;
+ uint32_t fesaDim2;
pRegister = pPLCDevice->getRegister("WO_int8");
dim1 = pRegister->getDimension1();
@@ -628,8 +632,8 @@ namespace AllTypes
pRegister->setValDateArray(pDevice->WO_dt_fesa.get(fesaDim1, pContext), dim1);
if (sendNow) pPLCDevice->send(blockName_);
+ }
- }
void MyWOBlock_Type::setOneDevice(Device* pDevice, MyWOBlockPropPropertyData& data, bool sendNow, MultiplexingContext* pContext)
{
if( !isInitialized_ )
@@ -641,7 +645,8 @@ namespace AllTypes
Silecs::Register* pRegister = NULL;
uint32_t dim1 = 1;
uint32_t fesaDim1;
-
+ uint32_t dim2 = 1;
+ uint32_t fesaDim2;
pRegister = pPLCDevice->getRegister("WO_int8");
dim1 = pRegister->getDimension1();
@@ -734,5 +739,6 @@ namespace AllTypes
if (sendNow) pPLCDevice->send(blockName_);
- }
+ }
+
}
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Beckhoff_BC9020.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Beckhoff_BC9020.silecsparam
index 79e434e..a26d3ee 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Beckhoff_BC9020.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Beckhoff_BC9020.silecsparam
@@ -2,76 +2,186 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 16:03:39.957252"/>
+ <Generation date="2017-06-06 11:12:20.813259"/>
<Deployment checksum="2843029646"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Beckhoff_BC9020" plc-brand="BECKHOFF" plc-system="TWINCat" plc-model="BC9020" protocol="BLOCK_MODE" address="32768" domain="NotUsed" used-mem="TODO">
<SILECS-Class name="SilecsHeader" version="1.0.0" address="32768" used-mem="MW16384..MW16407 / 24 words">
<Block name="hdrBlk" mode="READ-ONLY" size="14" address="32768" mem-size="48">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="17" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="18" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="22" mem-size="17" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="40" mem-size="8" synchro="MASTER"/>
+ <Register name="_version" synchro="MASTER" size="1" address="0" mem-size="17">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_checksum" synchro="MASTER" size="4" address="18" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="_user" synchro="MASTER" size="1" address="22" mem-size="17">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_date" synchro="MASTER" size="8" address="40" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
<SILECS-Class name="AllTypes" version="0.1.0" address="32816" used-mem="MW16408..MW18167 / 1760 words">
<Block name="MyROBlock" mode="READ-ONLY" size="53" address="32816" mem-size="122">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="1" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="2" mem-size="1" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="6" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="8" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="12" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="65" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="86" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="94" mem-size="1" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="96" mem-size="1" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="98" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="100" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="104" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="106" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="110" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="114" mem-size="8" synchro="MASTER"/>
+ <Register name="RO_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="1">
+ <scalar format="int8"/>
+ </Register>
+ <Register name="RO_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="2" mem-size="1">
+ <scalar format="uint8"/>
+ </Register>
+ <Register name="RO_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="int16"/>
+ </Register>
+ <Register name="RO_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="6" mem-size="2">
+ <scalar format="uint16"/>
+ </Register>
+ <Register name="RO_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="8" mem-size="4">
+ <scalar format="int32"/>
+ </Register>
+ <Register name="RO_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="12" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="RO_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="16" mem-size="4">
+ <scalar format="float32"/>
+ </Register>
+ <Register name="RO_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="20" mem-size="65">
+ <string string-length="64" format="string"/>
+ </Register>
+ <Register name="RO_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="86" mem-size="8">
+ <scalar format="date"/>
+ </Register>
+ <Register name="RO_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="94" mem-size="1">
+ <scalar format="char"/>
+ </Register>
+ <Register name="RO_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="96" mem-size="1">
+ <scalar format="byte"/>
+ </Register>
+ <Register name="RO_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="98" mem-size="2">
+ <scalar format="word"/>
+ </Register>
+ <Register name="RO_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="100" mem-size="4">
+ <scalar format="dword"/>
+ </Register>
+ <Register name="RO_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="104" mem-size="2">
+ <scalar format="int"/>
+ </Register>
+ <Register name="RO_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="106" mem-size="4">
+ <scalar format="dint"/>
+ </Register>
+ <Register name="RO_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="110" mem-size="4">
+ <scalar format="real"/>
+ </Register>
+ <Register name="RO_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="114" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Block name="MyRWBlock" mode="READ-WRITE" size="212" address="33060" mem-size="468">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="4" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="4" mem-size="4" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="8" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="16" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="24" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="40" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="56" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="72" mem-size="260" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="332" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="364" mem-size="4" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="368" mem-size="4" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="372" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="380" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="396" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="404" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="420" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="436" mem-size="32" synchro="MASTER"/>
+ <Register name="RW_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="4">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Register>
+ <Register name="RW_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="4" mem-size="4">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Register>
+ <Register name="RW_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="8" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Register>
+ <Register name="RW_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="16" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Register>
+ <Register name="RW_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="24" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Register>
+ <Register name="RW_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="40" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Register>
+ <Register name="RW_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="56" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Register>
+ <Register name="RW_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="72" mem-size="260">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Register>
+ <Register name="RW_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="332" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Register>
+ <Register name="RW_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="364" mem-size="4">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Register>
+ <Register name="RW_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="368" mem-size="4">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Register>
+ <Register name="RW_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="372" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Register>
+ <Register name="RW_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="380" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Register>
+ <Register name="RW_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="396" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Register>
+ <Register name="RW_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="404" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Register>
+ <Register name="RW_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="420" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Register>
+ <Register name="RW_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="436" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Register>
</Block>
<Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="33996" mem-size="1170">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="10" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="20" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="40" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="60" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="100" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="140" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="180" mem-size="650" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="830" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="910" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="920" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="930" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="950" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="990" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1010" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1050" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1090" mem-size="80" synchro="SLAVE"/>
+ <Register name="WO_int8" synchro="SLAVE" generateFesaValueItem="true" size="1" address="0" mem-size="10">
+ <array dim="10" format="int8"/>
+ </Register>
+ <Register name="WO_uint8" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="10" mem-size="10">
+ <array dim="10" format="uint8"/>
+ </Register>
+ <Register name="WO_int16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="20" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Register>
+ <Register name="WO_uint16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="40" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Register>
+ <Register name="WO_int32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="60" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Register>
+ <Register name="WO_uint32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="100" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Register>
+ <Register name="WO_float32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="140" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Register>
+ <Register name="WO_string" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="180" mem-size="650">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Register>
+ <Register name="WO_date" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="830" mem-size="80">
+ <array dim="10" format="date"/>
+ </Register>
+ <Register name="WO_char" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="910" mem-size="10">
+ <array dim="10" format="char"/>
+ </Register>
+ <Register name="WO_byte" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="920" mem-size="10">
+ <array dim="10" format="byte"/>
+ </Register>
+ <Register name="WO_word" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="930" mem-size="20">
+ <array dim="10" format="word"/>
+ </Register>
+ <Register name="WO_dword" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="950" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Register>
+ <Register name="WO_int" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="990" mem-size="20">
+ <array dim="10" format="int"/>
+ </Register>
+ <Register name="WO_dint" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1010" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Register>
+ <Register name="WO_real" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1050" mem-size="40">
+ <array dim="10" format="real"/>
+ </Register>
+ <Register name="WO_dt" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1090" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Register>
</Block>
<Instance label="testDevice1" address="0"/>
<Instance label="testDevice2" address="1"/>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Beckhoff_CX9020.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Beckhoff_CX9020.silecsparam
index 90d7bc2..03c1561 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Beckhoff_CX9020.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Beckhoff_CX9020.silecsparam
@@ -2,76 +2,186 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 16:03:58.791145"/>
+ <Generation date="2017-06-06 11:12:20.853125"/>
<Deployment checksum="427563505"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Beckhoff_CX9020" plc-brand="BECKHOFF" plc-system="TWINCat" plc-model="CX9020" protocol="BLOCK_MODE" address="24576" domain="NotUsed" used-mem="TODO">
<SILECS-Class name="SilecsHeader" version="1.0.0" address="24576" used-mem="MW12288..MW12313 / 26 words">
<Block name="hdrBlk" mode="READ-ONLY" size="14" address="24576" mem-size="52">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="17" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="20" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="24" mem-size="17" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="44" mem-size="8" synchro="MASTER"/>
+ <Register name="_version" synchro="MASTER" size="1" address="0" mem-size="17">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_checksum" synchro="MASTER" size="4" address="20" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="_user" synchro="MASTER" size="1" address="24" mem-size="17">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_date" synchro="MASTER" size="8" address="44" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
<SILECS-Class name="AllTypes" version="0.1.0" address="24628" used-mem="MW12314..MW14081 / 1768 words">
<Block name="MyROBlock" mode="READ-ONLY" size="53" address="24628" mem-size="128">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="1" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="2" mem-size="1" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="6" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="8" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="12" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="65" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="88" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="96" mem-size="1" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="98" mem-size="1" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="100" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="104" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="108" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="112" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="116" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="120" mem-size="8" synchro="MASTER"/>
+ <Register name="RO_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="1">
+ <scalar format="int8"/>
+ </Register>
+ <Register name="RO_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="2" mem-size="1">
+ <scalar format="uint8"/>
+ </Register>
+ <Register name="RO_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="int16"/>
+ </Register>
+ <Register name="RO_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="6" mem-size="2">
+ <scalar format="uint16"/>
+ </Register>
+ <Register name="RO_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="8" mem-size="4">
+ <scalar format="int32"/>
+ </Register>
+ <Register name="RO_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="12" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="RO_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="16" mem-size="4">
+ <scalar format="float32"/>
+ </Register>
+ <Register name="RO_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="20" mem-size="65">
+ <string string-length="64" format="string"/>
+ </Register>
+ <Register name="RO_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="88" mem-size="8">
+ <scalar format="date"/>
+ </Register>
+ <Register name="RO_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="96" mem-size="1">
+ <scalar format="char"/>
+ </Register>
+ <Register name="RO_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="98" mem-size="1">
+ <scalar format="byte"/>
+ </Register>
+ <Register name="RO_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="100" mem-size="2">
+ <scalar format="word"/>
+ </Register>
+ <Register name="RO_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="104" mem-size="4">
+ <scalar format="dword"/>
+ </Register>
+ <Register name="RO_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="108" mem-size="2">
+ <scalar format="int"/>
+ </Register>
+ <Register name="RO_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="112" mem-size="4">
+ <scalar format="dint"/>
+ </Register>
+ <Register name="RO_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="116" mem-size="4">
+ <scalar format="real"/>
+ </Register>
+ <Register name="RO_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="120" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Block name="MyRWBlock" mode="READ-WRITE" size="212" address="24884" mem-size="468">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="4" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="4" mem-size="4" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="8" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="16" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="24" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="40" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="56" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="72" mem-size="260" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="332" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="364" mem-size="4" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="368" mem-size="4" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="372" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="380" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="396" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="404" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="420" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="436" mem-size="32" synchro="MASTER"/>
+ <Register name="RW_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="4">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Register>
+ <Register name="RW_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="4" mem-size="4">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Register>
+ <Register name="RW_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="8" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Register>
+ <Register name="RW_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="16" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Register>
+ <Register name="RW_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="24" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Register>
+ <Register name="RW_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="40" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Register>
+ <Register name="RW_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="56" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Register>
+ <Register name="RW_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="72" mem-size="260">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Register>
+ <Register name="RW_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="332" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Register>
+ <Register name="RW_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="364" mem-size="4">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Register>
+ <Register name="RW_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="368" mem-size="4">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Register>
+ <Register name="RW_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="372" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Register>
+ <Register name="RW_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="380" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Register>
+ <Register name="RW_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="396" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Register>
+ <Register name="RW_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="404" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Register>
+ <Register name="RW_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="420" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Register>
+ <Register name="RW_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="436" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Register>
</Block>
<Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="25820" mem-size="1172">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="10" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="20" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="40" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="60" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="100" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="140" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="180" mem-size="650" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="832" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="912" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="922" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="932" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="952" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="992" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1012" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1052" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1092" mem-size="80" synchro="SLAVE"/>
+ <Register name="WO_int8" synchro="SLAVE" generateFesaValueItem="true" size="1" address="0" mem-size="10">
+ <array dim="10" format="int8"/>
+ </Register>
+ <Register name="WO_uint8" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="10" mem-size="10">
+ <array dim="10" format="uint8"/>
+ </Register>
+ <Register name="WO_int16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="20" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Register>
+ <Register name="WO_uint16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="40" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Register>
+ <Register name="WO_int32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="60" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Register>
+ <Register name="WO_uint32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="100" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Register>
+ <Register name="WO_float32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="140" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Register>
+ <Register name="WO_string" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="180" mem-size="650">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Register>
+ <Register name="WO_date" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="832" mem-size="80">
+ <array dim="10" format="date"/>
+ </Register>
+ <Register name="WO_char" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="912" mem-size="10">
+ <array dim="10" format="char"/>
+ </Register>
+ <Register name="WO_byte" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="922" mem-size="10">
+ <array dim="10" format="byte"/>
+ </Register>
+ <Register name="WO_word" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="932" mem-size="20">
+ <array dim="10" format="word"/>
+ </Register>
+ <Register name="WO_dword" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="952" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Register>
+ <Register name="WO_int" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="992" mem-size="20">
+ <array dim="10" format="int"/>
+ </Register>
+ <Register name="WO_dint" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1012" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Register>
+ <Register name="WO_real" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1052" mem-size="40">
+ <array dim="10" format="real"/>
+ </Register>
+ <Register name="WO_dt" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1092" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Register>
</Block>
<Instance label="testDevice1" address="0"/>
<Instance label="testDevice2" address="1"/>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Rabbit_BlockMode.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Rabbit_BlockMode.silecsparam
index f213b46..b3275d4 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Rabbit_BlockMode.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Rabbit_BlockMode.silecsparam
@@ -2,76 +2,186 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 16:04:28.617415"/>
+ <Generation date="2017-06-06 11:12:21.011368"/>
<Deployment checksum="3940683809"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Rabbit_BlockMode" plc-brand="DIGI" plc-system="Standard-C" plc-model="Rabbit_RCM_4010" protocol="BLOCK_MODE" address="0" domain="NotUsed" used-mem="TODO">
<SILECS-Class name="SilecsHeader" version="1.0.0" address="0" used-mem="MW0..MW21 / 22 words">
<Block name="hdrBlk" mode="READ-ONLY" size="14" address="0" mem-size="44">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="16" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="16" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="36" mem-size="8" synchro="MASTER"/>
+ <Register name="_version" synchro="MASTER" size="1" address="0" mem-size="16">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_checksum" synchro="MASTER" size="4" address="16" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="_user" synchro="MASTER" size="1" address="20" mem-size="16">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_date" synchro="MASTER" size="8" address="36" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
<SILECS-Class name="AllTypes" version="0.1.0" address="44" used-mem="MW22..MW1821 / 1800 words">
<Block name="MyROBlock" mode="READ-ONLY" size="53" address="44" mem-size="120">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="2" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="6" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="8" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="12" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="64" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="84" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="92" mem-size="2" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="94" mem-size="2" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="96" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="98" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="102" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="104" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="108" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="112" mem-size="8" synchro="MASTER"/>
+ <Register name="RO_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="2">
+ <scalar format="int8"/>
+ </Register>
+ <Register name="RO_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="2" mem-size="2">
+ <scalar format="uint8"/>
+ </Register>
+ <Register name="RO_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="int16"/>
+ </Register>
+ <Register name="RO_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="6" mem-size="2">
+ <scalar format="uint16"/>
+ </Register>
+ <Register name="RO_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="8" mem-size="4">
+ <scalar format="int32"/>
+ </Register>
+ <Register name="RO_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="12" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="RO_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="16" mem-size="4">
+ <scalar format="float32"/>
+ </Register>
+ <Register name="RO_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="20" mem-size="64">
+ <string string-length="64" format="string"/>
+ </Register>
+ <Register name="RO_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="84" mem-size="8">
+ <scalar format="date"/>
+ </Register>
+ <Register name="RO_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="92" mem-size="2">
+ <scalar format="char"/>
+ </Register>
+ <Register name="RO_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="94" mem-size="2">
+ <scalar format="byte"/>
+ </Register>
+ <Register name="RO_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="96" mem-size="2">
+ <scalar format="word"/>
+ </Register>
+ <Register name="RO_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="98" mem-size="4">
+ <scalar format="dword"/>
+ </Register>
+ <Register name="RO_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="102" mem-size="2">
+ <scalar format="int"/>
+ </Register>
+ <Register name="RO_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="104" mem-size="4">
+ <scalar format="dint"/>
+ </Register>
+ <Register name="RO_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="108" mem-size="4">
+ <scalar format="real"/>
+ </Register>
+ <Register name="RO_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="112" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Block name="MyRWBlock" mode="READ-WRITE" size="212" address="284" mem-size="480">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="8" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="16" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="24" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="32" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="48" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="64" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="80" mem-size="256" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="336" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="368" mem-size="8" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="376" mem-size="8" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="384" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="392" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="408" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="416" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="432" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="448" mem-size="32" synchro="MASTER"/>
+ <Register name="RW_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Register>
+ <Register name="RW_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="8" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Register>
+ <Register name="RW_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="16" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Register>
+ <Register name="RW_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="24" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Register>
+ <Register name="RW_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="32" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Register>
+ <Register name="RW_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="48" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Register>
+ <Register name="RW_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="64" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Register>
+ <Register name="RW_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="80" mem-size="256">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Register>
+ <Register name="RW_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="336" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Register>
+ <Register name="RW_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="368" mem-size="8">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Register>
+ <Register name="RW_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="376" mem-size="8">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Register>
+ <Register name="RW_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="384" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Register>
+ <Register name="RW_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="392" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Register>
+ <Register name="RW_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="408" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Register>
+ <Register name="RW_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="416" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Register>
+ <Register name="RW_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="432" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Register>
+ <Register name="RW_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="448" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Register>
</Block>
<Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="1244" mem-size="1200">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="20" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="40" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="60" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="80" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="120" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="160" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="200" mem-size="640" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="840" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="920" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="940" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="960" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="980" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="1020" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1040" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1080" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1120" mem-size="80" synchro="SLAVE"/>
+ <Register name="WO_int8" synchro="SLAVE" generateFesaValueItem="true" size="1" address="0" mem-size="20">
+ <array dim="10" format="int8"/>
+ </Register>
+ <Register name="WO_uint8" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="20" mem-size="20">
+ <array dim="10" format="uint8"/>
+ </Register>
+ <Register name="WO_int16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="40" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Register>
+ <Register name="WO_uint16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="60" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Register>
+ <Register name="WO_int32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="80" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Register>
+ <Register name="WO_uint32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="120" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Register>
+ <Register name="WO_float32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="160" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Register>
+ <Register name="WO_string" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="200" mem-size="640">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Register>
+ <Register name="WO_date" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="840" mem-size="80">
+ <array dim="10" format="date"/>
+ </Register>
+ <Register name="WO_char" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="920" mem-size="20">
+ <array dim="10" format="char"/>
+ </Register>
+ <Register name="WO_byte" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="940" mem-size="20">
+ <array dim="10" format="byte"/>
+ </Register>
+ <Register name="WO_word" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="960" mem-size="20">
+ <array dim="10" format="word"/>
+ </Register>
+ <Register name="WO_dword" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="980" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Register>
+ <Register name="WO_int" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="1020" mem-size="20">
+ <array dim="10" format="int"/>
+ </Register>
+ <Register name="WO_dint" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1040" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Register>
+ <Register name="WO_real" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1080" mem-size="40">
+ <array dim="10" format="real"/>
+ </Register>
+ <Register name="WO_dt" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1120" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Register>
</Block>
<Instance label="testDevice1" address="0"/>
<Instance label="testDevice2" address="1"/>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Rabbit_DeviceMode.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Rabbit_DeviceMode.silecsparam
index 73cbd93..3f7bedc 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Rabbit_DeviceMode.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Rabbit_DeviceMode.silecsparam
@@ -2,76 +2,186 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 16:04:38.516577"/>
+ <Generation date="2017-06-06 11:12:20.972129"/>
<Deployment checksum="3940683809"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Rabbit_DeviceMode" plc-brand="DIGI" plc-system="Standard-C" plc-model="Rabbit_RCM_4010" protocol="DEVICE_MODE" address="0" domain="NotUsed" used-mem="TODO">
<SILECS-Class name="SilecsHeader" version="1.0.0" address="0" used-mem="MW0..MW21 / 22 words">
<Block name="hdrBlk" mode="READ-ONLY" size="14" address="0" mem-size="44">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="16" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="16" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="36" mem-size="8" synchro="MASTER"/>
+ <Register name="_version" synchro="MASTER" size="1" address="0" mem-size="16">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_checksum" synchro="MASTER" size="4" address="16" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="_user" synchro="MASTER" size="1" address="20" mem-size="16">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_date" synchro="MASTER" size="8" address="36" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
<SILECS-Class name="AllTypes" version="0.1.0" address="44" used-mem="MW22..MW1821 / 1800 words">
<Block name="MyROBlock" mode="READ-ONLY" size="53" address="0" mem-size="120">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="2" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="6" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="8" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="12" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="64" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="84" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="92" mem-size="2" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="94" mem-size="2" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="96" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="98" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="102" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="104" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="108" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="112" mem-size="8" synchro="MASTER"/>
+ <Register name="RO_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="2">
+ <scalar format="int8"/>
+ </Register>
+ <Register name="RO_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="2" mem-size="2">
+ <scalar format="uint8"/>
+ </Register>
+ <Register name="RO_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="int16"/>
+ </Register>
+ <Register name="RO_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="6" mem-size="2">
+ <scalar format="uint16"/>
+ </Register>
+ <Register name="RO_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="8" mem-size="4">
+ <scalar format="int32"/>
+ </Register>
+ <Register name="RO_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="12" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="RO_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="16" mem-size="4">
+ <scalar format="float32"/>
+ </Register>
+ <Register name="RO_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="20" mem-size="64">
+ <string string-length="64" format="string"/>
+ </Register>
+ <Register name="RO_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="84" mem-size="8">
+ <scalar format="date"/>
+ </Register>
+ <Register name="RO_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="92" mem-size="2">
+ <scalar format="char"/>
+ </Register>
+ <Register name="RO_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="94" mem-size="2">
+ <scalar format="byte"/>
+ </Register>
+ <Register name="RO_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="96" mem-size="2">
+ <scalar format="word"/>
+ </Register>
+ <Register name="RO_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="98" mem-size="4">
+ <scalar format="dword"/>
+ </Register>
+ <Register name="RO_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="102" mem-size="2">
+ <scalar format="int"/>
+ </Register>
+ <Register name="RO_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="104" mem-size="4">
+ <scalar format="dint"/>
+ </Register>
+ <Register name="RO_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="108" mem-size="4">
+ <scalar format="real"/>
+ </Register>
+ <Register name="RO_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="112" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Block name="MyRWBlock" mode="READ-WRITE" size="212" address="120" mem-size="480">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="8" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="16" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="24" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="32" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="48" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="64" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="80" mem-size="256" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="336" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="368" mem-size="8" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="376" mem-size="8" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="384" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="392" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="408" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="416" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="432" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="448" mem-size="32" synchro="MASTER"/>
+ <Register name="RW_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Register>
+ <Register name="RW_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="8" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Register>
+ <Register name="RW_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="16" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Register>
+ <Register name="RW_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="24" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Register>
+ <Register name="RW_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="32" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Register>
+ <Register name="RW_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="48" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Register>
+ <Register name="RW_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="64" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Register>
+ <Register name="RW_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="80" mem-size="256">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Register>
+ <Register name="RW_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="336" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Register>
+ <Register name="RW_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="368" mem-size="8">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Register>
+ <Register name="RW_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="376" mem-size="8">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Register>
+ <Register name="RW_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="384" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Register>
+ <Register name="RW_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="392" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Register>
+ <Register name="RW_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="408" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Register>
+ <Register name="RW_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="416" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Register>
+ <Register name="RW_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="432" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Register>
+ <Register name="RW_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="448" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Register>
</Block>
<Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="600" mem-size="1200">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="20" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="40" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="60" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="80" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="120" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="160" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="200" mem-size="640" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="840" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="920" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="940" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="960" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="980" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="1020" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1040" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1080" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1120" mem-size="80" synchro="SLAVE"/>
+ <Register name="WO_int8" synchro="SLAVE" generateFesaValueItem="true" size="1" address="0" mem-size="20">
+ <array dim="10" format="int8"/>
+ </Register>
+ <Register name="WO_uint8" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="20" mem-size="20">
+ <array dim="10" format="uint8"/>
+ </Register>
+ <Register name="WO_int16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="40" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Register>
+ <Register name="WO_uint16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="60" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Register>
+ <Register name="WO_int32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="80" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Register>
+ <Register name="WO_uint32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="120" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Register>
+ <Register name="WO_float32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="160" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Register>
+ <Register name="WO_string" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="200" mem-size="640">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Register>
+ <Register name="WO_date" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="840" mem-size="80">
+ <array dim="10" format="date"/>
+ </Register>
+ <Register name="WO_char" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="920" mem-size="20">
+ <array dim="10" format="char"/>
+ </Register>
+ <Register name="WO_byte" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="940" mem-size="20">
+ <array dim="10" format="byte"/>
+ </Register>
+ <Register name="WO_word" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="960" mem-size="20">
+ <array dim="10" format="word"/>
+ </Register>
+ <Register name="WO_dword" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="980" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Register>
+ <Register name="WO_int" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="1020" mem-size="20">
+ <array dim="10" format="int"/>
+ </Register>
+ <Register name="WO_dint" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1040" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Register>
+ <Register name="WO_real" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1080" mem-size="40">
+ <array dim="10" format="real"/>
+ </Register>
+ <Register name="WO_dt" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1120" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Register>
</Block>
<Instance label="testDevice1" address="44"/>
<Instance label="testDevice2" address="1844"/>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Schneider_M340.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Schneider_M340.silecsparam
index 1ea96e0..a4271a2 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Schneider_M340.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Schneider_M340.silecsparam
@@ -2,76 +2,186 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 16:04:09.437778"/>
+ <Generation date="2017-06-06 11:12:20.934851"/>
<Deployment checksum="3940683809"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Schneider_M340" plc-brand="SCHNEIDER" plc-system="UNITY Pro" plc-model="M340" protocol="BLOCK_MODE" address="0" domain="NotUsed" used-mem="TODO">
<SILECS-Class name="SilecsHeader" version="1.0.0" address="0" used-mem="MW0..MW21 / 22 words">
<Block name="hdrBlk" mode="READ-ONLY" size="14" address="0" mem-size="44">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="16" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="16" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="36" mem-size="8" synchro="MASTER"/>
+ <Register name="_version" synchro="MASTER" size="1" address="0" mem-size="16">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_checksum" synchro="MASTER" size="4" address="16" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="_user" synchro="MASTER" size="1" address="20" mem-size="16">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_date" synchro="MASTER" size="8" address="36" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
<SILECS-Class name="AllTypes" version="0.1.0" address="44" used-mem="MW22..MW1801 / 1780 words">
<Block name="MyROBlock" mode="READ-ONLY" size="53" address="44" mem-size="124">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="2" mem-size="1" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="6" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="8" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="12" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="64" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="84" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="92" mem-size="2" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="94" mem-size="1" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="96" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="100" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="104" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="108" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="112" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="116" mem-size="8" synchro="MASTER"/>
+ <Register name="RO_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="2">
+ <scalar format="int8"/>
+ </Register>
+ <Register name="RO_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="2" mem-size="1">
+ <scalar format="uint8"/>
+ </Register>
+ <Register name="RO_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="int16"/>
+ </Register>
+ <Register name="RO_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="6" mem-size="2">
+ <scalar format="uint16"/>
+ </Register>
+ <Register name="RO_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="8" mem-size="4">
+ <scalar format="int32"/>
+ </Register>
+ <Register name="RO_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="12" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="RO_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="16" mem-size="4">
+ <scalar format="float32"/>
+ </Register>
+ <Register name="RO_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="20" mem-size="64">
+ <string string-length="64" format="string"/>
+ </Register>
+ <Register name="RO_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="84" mem-size="8">
+ <scalar format="date"/>
+ </Register>
+ <Register name="RO_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="92" mem-size="2">
+ <scalar format="char"/>
+ </Register>
+ <Register name="RO_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="94" mem-size="1">
+ <scalar format="byte"/>
+ </Register>
+ <Register name="RO_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="96" mem-size="2">
+ <scalar format="word"/>
+ </Register>
+ <Register name="RO_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="100" mem-size="4">
+ <scalar format="dword"/>
+ </Register>
+ <Register name="RO_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="104" mem-size="2">
+ <scalar format="int"/>
+ </Register>
+ <Register name="RO_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="108" mem-size="4">
+ <scalar format="dint"/>
+ </Register>
+ <Register name="RO_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="112" mem-size="4">
+ <scalar format="real"/>
+ </Register>
+ <Register name="RO_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="116" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Block name="MyRWBlock" mode="READ-WRITE" size="212" address="292" mem-size="472">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="8" mem-size="4" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="12" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="20" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="28" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="44" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="60" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="76" mem-size="256" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="332" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="364" mem-size="8" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="372" mem-size="4" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="376" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="384" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="400" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="408" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="424" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="440" mem-size="32" synchro="MASTER"/>
+ <Register name="RW_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Register>
+ <Register name="RW_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="8" mem-size="4">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Register>
+ <Register name="RW_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="12" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Register>
+ <Register name="RW_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="20" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Register>
+ <Register name="RW_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="28" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Register>
+ <Register name="RW_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="44" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Register>
+ <Register name="RW_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="60" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Register>
+ <Register name="RW_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="76" mem-size="256">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Register>
+ <Register name="RW_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="332" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Register>
+ <Register name="RW_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="364" mem-size="8">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Register>
+ <Register name="RW_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="372" mem-size="4">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Register>
+ <Register name="RW_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="376" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Register>
+ <Register name="RW_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="384" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Register>
+ <Register name="RW_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="400" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Register>
+ <Register name="RW_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="408" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Register>
+ <Register name="RW_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="424" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Register>
+ <Register name="RW_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="440" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Register>
</Block>
<Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="1236" mem-size="1184">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="20" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="30" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="50" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="72" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="112" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="152" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="192" mem-size="640" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="832" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="912" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="932" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="942" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="964" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="1004" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1024" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1064" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1104" mem-size="80" synchro="SLAVE"/>
+ <Register name="WO_int8" synchro="SLAVE" generateFesaValueItem="true" size="1" address="0" mem-size="20">
+ <array dim="10" format="int8"/>
+ </Register>
+ <Register name="WO_uint8" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="20" mem-size="10">
+ <array dim="10" format="uint8"/>
+ </Register>
+ <Register name="WO_int16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="30" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Register>
+ <Register name="WO_uint16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="50" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Register>
+ <Register name="WO_int32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="72" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Register>
+ <Register name="WO_uint32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="112" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Register>
+ <Register name="WO_float32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="152" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Register>
+ <Register name="WO_string" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="192" mem-size="640">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Register>
+ <Register name="WO_date" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="832" mem-size="80">
+ <array dim="10" format="date"/>
+ </Register>
+ <Register name="WO_char" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="912" mem-size="20">
+ <array dim="10" format="char"/>
+ </Register>
+ <Register name="WO_byte" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="932" mem-size="10">
+ <array dim="10" format="byte"/>
+ </Register>
+ <Register name="WO_word" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="942" mem-size="20">
+ <array dim="10" format="word"/>
+ </Register>
+ <Register name="WO_dword" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="964" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Register>
+ <Register name="WO_int" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="1004" mem-size="20">
+ <array dim="10" format="int"/>
+ </Register>
+ <Register name="WO_dint" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1024" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Register>
+ <Register name="WO_real" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1064" mem-size="40">
+ <array dim="10" format="real"/>
+ </Register>
+ <Register name="WO_dt" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1104" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Register>
</Block>
<Instance label="testDevice1" address="0"/>
<Instance label="testDevice2" address="1"/>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Schneider_PremiumQuantum.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Schneider_PremiumQuantum.silecsparam
index 0e904f0..fc8dc15 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Schneider_PremiumQuantum.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Schneider_PremiumQuantum.silecsparam
@@ -2,76 +2,186 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 16:04:19.735644"/>
+ <Generation date="2017-06-06 11:12:20.891171"/>
<Deployment checksum="3940683809"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Schneider_PremiumQuantum" plc-brand="SCHNEIDER" plc-system="UNITY Pro" plc-model="Premium" protocol="BLOCK_MODE" address="0" domain="NotUsed" used-mem="TODO">
<SILECS-Class name="SilecsHeader" version="1.0.0" address="0" used-mem="MW0..MW21 / 22 words">
<Block name="hdrBlk" mode="READ-ONLY" size="14" address="0" mem-size="44">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="16" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="16" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="36" mem-size="8" synchro="MASTER"/>
+ <Register name="_version" synchro="MASTER" size="1" address="0" mem-size="16">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_checksum" synchro="MASTER" size="4" address="16" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="_user" synchro="MASTER" size="1" address="20" mem-size="16">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_date" synchro="MASTER" size="8" address="36" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
<SILECS-Class name="AllTypes" version="0.1.0" address="44" used-mem="MW22..MW1793 / 1772 words">
<Block name="MyROBlock" mode="READ-ONLY" size="53" address="44" mem-size="120">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="2" mem-size="1" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="6" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="8" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="12" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="64" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="84" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="92" mem-size="2" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="94" mem-size="1" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="96" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="98" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="102" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="104" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="108" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="112" mem-size="8" synchro="MASTER"/>
+ <Register name="RO_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="2">
+ <scalar format="int8"/>
+ </Register>
+ <Register name="RO_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="2" mem-size="1">
+ <scalar format="uint8"/>
+ </Register>
+ <Register name="RO_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="int16"/>
+ </Register>
+ <Register name="RO_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="6" mem-size="2">
+ <scalar format="uint16"/>
+ </Register>
+ <Register name="RO_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="8" mem-size="4">
+ <scalar format="int32"/>
+ </Register>
+ <Register name="RO_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="12" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="RO_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="16" mem-size="4">
+ <scalar format="float32"/>
+ </Register>
+ <Register name="RO_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="20" mem-size="64">
+ <string string-length="64" format="string"/>
+ </Register>
+ <Register name="RO_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="84" mem-size="8">
+ <scalar format="date"/>
+ </Register>
+ <Register name="RO_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="92" mem-size="2">
+ <scalar format="char"/>
+ </Register>
+ <Register name="RO_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="94" mem-size="1">
+ <scalar format="byte"/>
+ </Register>
+ <Register name="RO_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="96" mem-size="2">
+ <scalar format="word"/>
+ </Register>
+ <Register name="RO_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="98" mem-size="4">
+ <scalar format="dword"/>
+ </Register>
+ <Register name="RO_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="102" mem-size="2">
+ <scalar format="int"/>
+ </Register>
+ <Register name="RO_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="104" mem-size="4">
+ <scalar format="dint"/>
+ </Register>
+ <Register name="RO_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="108" mem-size="4">
+ <scalar format="real"/>
+ </Register>
+ <Register name="RO_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="112" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Block name="MyRWBlock" mode="READ-WRITE" size="212" address="284" mem-size="472">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="8" mem-size="4" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="12" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="20" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="28" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="44" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="60" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="76" mem-size="256" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="332" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="364" mem-size="8" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="372" mem-size="4" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="376" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="384" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="400" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="408" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="424" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="440" mem-size="32" synchro="MASTER"/>
+ <Register name="RW_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Register>
+ <Register name="RW_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="8" mem-size="4">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Register>
+ <Register name="RW_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="12" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Register>
+ <Register name="RW_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="20" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Register>
+ <Register name="RW_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="28" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Register>
+ <Register name="RW_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="44" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Register>
+ <Register name="RW_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="60" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Register>
+ <Register name="RW_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="76" mem-size="256">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Register>
+ <Register name="RW_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="332" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Register>
+ <Register name="RW_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="364" mem-size="8">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Register>
+ <Register name="RW_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="372" mem-size="4">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Register>
+ <Register name="RW_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="376" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Register>
+ <Register name="RW_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="384" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Register>
+ <Register name="RW_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="400" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Register>
+ <Register name="RW_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="408" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Register>
+ <Register name="RW_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="424" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Register>
+ <Register name="RW_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="440" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Register>
</Block>
<Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="1228" mem-size="1180">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="20" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="30" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="50" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="70" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="110" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="150" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="190" mem-size="640" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="830" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="910" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="930" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="940" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="960" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="1000" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1020" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1060" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1100" mem-size="80" synchro="SLAVE"/>
+ <Register name="WO_int8" synchro="SLAVE" generateFesaValueItem="true" size="1" address="0" mem-size="20">
+ <array dim="10" format="int8"/>
+ </Register>
+ <Register name="WO_uint8" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="20" mem-size="10">
+ <array dim="10" format="uint8"/>
+ </Register>
+ <Register name="WO_int16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="30" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Register>
+ <Register name="WO_uint16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="50" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Register>
+ <Register name="WO_int32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="70" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Register>
+ <Register name="WO_uint32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="110" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Register>
+ <Register name="WO_float32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="150" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Register>
+ <Register name="WO_string" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="190" mem-size="640">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Register>
+ <Register name="WO_date" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="830" mem-size="80">
+ <array dim="10" format="date"/>
+ </Register>
+ <Register name="WO_char" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="910" mem-size="20">
+ <array dim="10" format="char"/>
+ </Register>
+ <Register name="WO_byte" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="930" mem-size="10">
+ <array dim="10" format="byte"/>
+ </Register>
+ <Register name="WO_word" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="940" mem-size="20">
+ <array dim="10" format="word"/>
+ </Register>
+ <Register name="WO_dword" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="960" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Register>
+ <Register name="WO_int" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="1000" mem-size="20">
+ <array dim="10" format="int"/>
+ </Register>
+ <Register name="WO_dint" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1020" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Register>
+ <Register name="WO_real" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1060" mem-size="40">
+ <array dim="10" format="real"/>
+ </Register>
+ <Register name="WO_dt" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1100" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Register>
</Block>
<Instance label="testDevice1" address="0"/>
<Instance label="testDevice2" address="1"/>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Siemens_Step7Block.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Siemens_Step7Block.silecsparam
index 8182e9e..64589a2 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Siemens_Step7Block.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Siemens_Step7Block.silecsparam
@@ -2,76 +2,186 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 16:03:31.706052"/>
+ <Generation date="2017-06-06 11:12:20.641338"/>
<Deployment checksum="3940683809"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Siemens_Step7Block" plc-brand="SIEMENS" plc-system="STEP-7" plc-model="SIMATIC_S7-300" protocol="DEVICE_MODE" address="0" domain="NotUsed" used-mem="TODO">
<SILECS-Class name="SilecsHeader" version="1.0.0" address="0" used-mem="DB0..DB0 / 48 bytes">
<Block name="hdrBlk" mode="READ-ONLY" size="14" address="0" mem-size="48">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="18" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="18" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="22" mem-size="18" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="40" mem-size="8" synchro="MASTER"/>
+ <Register name="_version" synchro="MASTER" size="1" address="0" mem-size="18">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_checksum" synchro="MASTER" size="4" address="18" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="_user" synchro="MASTER" size="1" address="22" mem-size="18">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_date" synchro="MASTER" size="8" address="40" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
<SILECS-Class name="AllTypes" version="0.1.0" address="1" used-mem="DB1..DB2 / 3540 bytes">
<Block name="MyROBlock" mode="READ-ONLY" size="53" address="0" mem-size="118">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="1" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="1" mem-size="1" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="2" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="6" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="10" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="14" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="18" mem-size="66" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="84" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="92" mem-size="1" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="93" mem-size="1" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="94" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="96" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="100" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="102" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="106" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="110" mem-size="8" synchro="MASTER"/>
+ <Register name="RO_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="1">
+ <scalar format="int8"/>
+ </Register>
+ <Register name="RO_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="1" mem-size="1">
+ <scalar format="uint8"/>
+ </Register>
+ <Register name="RO_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="2" mem-size="2">
+ <scalar format="int16"/>
+ </Register>
+ <Register name="RO_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="uint16"/>
+ </Register>
+ <Register name="RO_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="6" mem-size="4">
+ <scalar format="int32"/>
+ </Register>
+ <Register name="RO_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="10" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="RO_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="14" mem-size="4">
+ <scalar format="float32"/>
+ </Register>
+ <Register name="RO_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="18" mem-size="66">
+ <string string-length="64" format="string"/>
+ </Register>
+ <Register name="RO_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="84" mem-size="8">
+ <scalar format="date"/>
+ </Register>
+ <Register name="RO_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="92" mem-size="1">
+ <scalar format="char"/>
+ </Register>
+ <Register name="RO_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="93" mem-size="1">
+ <scalar format="byte"/>
+ </Register>
+ <Register name="RO_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="94" mem-size="2">
+ <scalar format="word"/>
+ </Register>
+ <Register name="RO_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="96" mem-size="4">
+ <scalar format="dword"/>
+ </Register>
+ <Register name="RO_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="100" mem-size="2">
+ <scalar format="int"/>
+ </Register>
+ <Register name="RO_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="102" mem-size="4">
+ <scalar format="dint"/>
+ </Register>
+ <Register name="RO_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="106" mem-size="4">
+ <scalar format="real"/>
+ </Register>
+ <Register name="RO_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="110" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Block name="MyRWBlock" mode="READ-WRITE" size="212" address="118" mem-size="472">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="4" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="4" mem-size="4" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="8" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="16" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="24" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="40" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="56" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="72" mem-size="264" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="336" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="368" mem-size="4" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="372" mem-size="4" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="376" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="384" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="400" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="408" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="424" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="440" mem-size="32" synchro="MASTER"/>
+ <Register name="RW_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="4">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Register>
+ <Register name="RW_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="4" mem-size="4">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Register>
+ <Register name="RW_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="8" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Register>
+ <Register name="RW_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="16" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Register>
+ <Register name="RW_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="24" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Register>
+ <Register name="RW_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="40" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Register>
+ <Register name="RW_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="56" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Register>
+ <Register name="RW_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="72" mem-size="264">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Register>
+ <Register name="RW_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="336" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Register>
+ <Register name="RW_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="368" mem-size="4">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Register>
+ <Register name="RW_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="372" mem-size="4">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Register>
+ <Register name="RW_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="376" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Register>
+ <Register name="RW_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="384" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Register>
+ <Register name="RW_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="400" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Register>
+ <Register name="RW_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="408" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Register>
+ <Register name="RW_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="424" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Register>
+ <Register name="RW_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="440" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Register>
</Block>
<Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="590" mem-size="1180">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="10" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="20" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="40" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="60" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="100" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="140" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="180" mem-size="660" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="840" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="920" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="930" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="940" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="960" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="1000" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1020" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1060" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1100" mem-size="80" synchro="SLAVE"/>
+ <Register name="WO_int8" synchro="SLAVE" generateFesaValueItem="true" size="1" address="0" mem-size="10">
+ <array dim="10" format="int8"/>
+ </Register>
+ <Register name="WO_uint8" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="10" mem-size="10">
+ <array dim="10" format="uint8"/>
+ </Register>
+ <Register name="WO_int16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="20" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Register>
+ <Register name="WO_uint16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="40" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Register>
+ <Register name="WO_int32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="60" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Register>
+ <Register name="WO_uint32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="100" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Register>
+ <Register name="WO_float32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="140" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Register>
+ <Register name="WO_string" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="180" mem-size="660">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Register>
+ <Register name="WO_date" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="840" mem-size="80">
+ <array dim="10" format="date"/>
+ </Register>
+ <Register name="WO_char" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="920" mem-size="10">
+ <array dim="10" format="char"/>
+ </Register>
+ <Register name="WO_byte" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="930" mem-size="10">
+ <array dim="10" format="byte"/>
+ </Register>
+ <Register name="WO_word" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="940" mem-size="20">
+ <array dim="10" format="word"/>
+ </Register>
+ <Register name="WO_dword" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="960" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Register>
+ <Register name="WO_int" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="1000" mem-size="20">
+ <array dim="10" format="int"/>
+ </Register>
+ <Register name="WO_dint" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1020" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Register>
+ <Register name="WO_real" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1060" mem-size="40">
+ <array dim="10" format="real"/>
+ </Register>
+ <Register name="WO_dt" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1100" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Register>
</Block>
<Instance label="testDevice1" address="1"/>
<Instance label="testDevice2" address="2"/>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Siemens_Step7Device.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Siemens_Step7Device.silecsparam
index 46bf195..3c1e348 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Siemens_Step7Device.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Siemens_Step7Device.silecsparam
@@ -2,76 +2,186 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 16:03:18.892092"/>
+ <Generation date="2017-06-06 11:12:20.678230"/>
<Deployment checksum="3940683809"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Siemens_Step7Device" plc-brand="SIEMENS" plc-system="STEP-7" plc-model="SIMATIC_S7-300" protocol="BLOCK_MODE" address="0" domain="NotUsed" used-mem="TODO">
<SILECS-Class name="SilecsHeader" version="1.0.0" address="0" used-mem="DB0..DB0 / 48 bytes">
<Block name="hdrBlk" mode="READ-ONLY" size="14" address="0" mem-size="48">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="18" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="18" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="22" mem-size="18" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="40" mem-size="8" synchro="MASTER"/>
+ <Register name="_version" synchro="MASTER" size="1" address="0" mem-size="18">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_checksum" synchro="MASTER" size="4" address="18" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="_user" synchro="MASTER" size="1" address="22" mem-size="18">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_date" synchro="MASTER" size="8" address="40" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
<SILECS-Class name="AllTypes" version="0.1.0" address="1" used-mem="DB1..DB3 / 3540 bytes">
<Block name="MyROBlock" mode="READ-ONLY" size="53" address="1" mem-size="118">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="1" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="1" mem-size="1" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="2" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="6" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="10" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="14" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="18" mem-size="66" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="84" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="92" mem-size="1" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="93" mem-size="1" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="94" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="96" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="100" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="102" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="106" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="110" mem-size="8" synchro="MASTER"/>
+ <Register name="RO_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="1">
+ <scalar format="int8"/>
+ </Register>
+ <Register name="RO_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="1" mem-size="1">
+ <scalar format="uint8"/>
+ </Register>
+ <Register name="RO_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="2" mem-size="2">
+ <scalar format="int16"/>
+ </Register>
+ <Register name="RO_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="uint16"/>
+ </Register>
+ <Register name="RO_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="6" mem-size="4">
+ <scalar format="int32"/>
+ </Register>
+ <Register name="RO_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="10" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="RO_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="14" mem-size="4">
+ <scalar format="float32"/>
+ </Register>
+ <Register name="RO_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="18" mem-size="66">
+ <string string-length="64" format="string"/>
+ </Register>
+ <Register name="RO_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="84" mem-size="8">
+ <scalar format="date"/>
+ </Register>
+ <Register name="RO_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="92" mem-size="1">
+ <scalar format="char"/>
+ </Register>
+ <Register name="RO_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="93" mem-size="1">
+ <scalar format="byte"/>
+ </Register>
+ <Register name="RO_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="94" mem-size="2">
+ <scalar format="word"/>
+ </Register>
+ <Register name="RO_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="96" mem-size="4">
+ <scalar format="dword"/>
+ </Register>
+ <Register name="RO_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="100" mem-size="2">
+ <scalar format="int"/>
+ </Register>
+ <Register name="RO_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="102" mem-size="4">
+ <scalar format="dint"/>
+ </Register>
+ <Register name="RO_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="106" mem-size="4">
+ <scalar format="real"/>
+ </Register>
+ <Register name="RO_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="110" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Block name="MyRWBlock" mode="READ-WRITE" size="212" address="2" mem-size="472">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="4" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="4" mem-size="4" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="8" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="16" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="24" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="40" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="56" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="72" mem-size="264" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="336" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="368" mem-size="4" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="372" mem-size="4" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="376" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="384" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="400" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="408" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="424" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="440" mem-size="32" synchro="MASTER"/>
+ <Register name="RW_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="4">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Register>
+ <Register name="RW_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="4" mem-size="4">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Register>
+ <Register name="RW_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="8" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Register>
+ <Register name="RW_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="16" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Register>
+ <Register name="RW_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="24" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Register>
+ <Register name="RW_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="40" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Register>
+ <Register name="RW_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="56" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Register>
+ <Register name="RW_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="72" mem-size="264">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Register>
+ <Register name="RW_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="336" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Register>
+ <Register name="RW_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="368" mem-size="4">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Register>
+ <Register name="RW_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="372" mem-size="4">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Register>
+ <Register name="RW_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="376" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Register>
+ <Register name="RW_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="384" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Register>
+ <Register name="RW_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="400" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Register>
+ <Register name="RW_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="408" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Register>
+ <Register name="RW_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="424" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Register>
+ <Register name="RW_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="440" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Register>
</Block>
<Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="3" mem-size="1180">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="10" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="20" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="40" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="60" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="100" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="140" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="180" mem-size="660" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="840" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="920" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="930" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="940" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="960" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="1000" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1020" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1060" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1100" mem-size="80" synchro="SLAVE"/>
+ <Register name="WO_int8" synchro="SLAVE" generateFesaValueItem="true" size="1" address="0" mem-size="10">
+ <array dim="10" format="int8"/>
+ </Register>
+ <Register name="WO_uint8" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="10" mem-size="10">
+ <array dim="10" format="uint8"/>
+ </Register>
+ <Register name="WO_int16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="20" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Register>
+ <Register name="WO_uint16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="40" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Register>
+ <Register name="WO_int32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="60" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Register>
+ <Register name="WO_uint32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="100" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Register>
+ <Register name="WO_float32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="140" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Register>
+ <Register name="WO_string" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="180" mem-size="660">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Register>
+ <Register name="WO_date" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="840" mem-size="80">
+ <array dim="10" format="date"/>
+ </Register>
+ <Register name="WO_char" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="920" mem-size="10">
+ <array dim="10" format="char"/>
+ </Register>
+ <Register name="WO_byte" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="930" mem-size="10">
+ <array dim="10" format="byte"/>
+ </Register>
+ <Register name="WO_word" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="940" mem-size="20">
+ <array dim="10" format="word"/>
+ </Register>
+ <Register name="WO_dword" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="960" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Register>
+ <Register name="WO_int" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="1000" mem-size="20">
+ <array dim="10" format="int"/>
+ </Register>
+ <Register name="WO_dint" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1020" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Register>
+ <Register name="WO_real" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1060" mem-size="40">
+ <array dim="10" format="real"/>
+ </Register>
+ <Register name="WO_dt" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1100" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Register>
</Block>
<Instance label="testDevice1" address="0"/>
<Instance label="testDevice2" address="1"/>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Siemens_TiaBlock.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Siemens_TiaBlock.silecsparam
index 7f4c984..5f82300 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Siemens_TiaBlock.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Siemens_TiaBlock.silecsparam
@@ -2,76 +2,186 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 16:02:43.799998"/>
+ <Generation date="2017-06-06 11:12:20.606090"/>
<Deployment checksum="3940683809"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Siemens_TiaBlock" plc-brand="SIEMENS" plc-system="TIA-PORTAL" plc-model="SIMATIC_S7-300" protocol="BLOCK_MODE" address="0" domain="NotUsed" used-mem="TODO">
<SILECS-Class name="SilecsHeader" version="1.0.0" address="0" used-mem="DB0..DB0 / 48 bytes">
<Block name="hdrBlk" mode="READ-ONLY" size="14" address="0" mem-size="48">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="18" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="18" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="22" mem-size="18" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="40" mem-size="8" synchro="MASTER"/>
+ <Register name="_version" synchro="MASTER" size="1" address="0" mem-size="18">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_checksum" synchro="MASTER" size="4" address="18" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="_user" synchro="MASTER" size="1" address="22" mem-size="18">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_date" synchro="MASTER" size="8" address="40" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
<SILECS-Class name="AllTypes" version="0.1.0" address="1" used-mem="DB1..DB3 / 3540 bytes">
<Block name="MyROBlock" mode="READ-ONLY" size="53" address="1" mem-size="118">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="1" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="1" mem-size="1" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="2" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="6" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="10" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="14" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="18" mem-size="66" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="84" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="92" mem-size="1" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="93" mem-size="1" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="94" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="96" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="100" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="102" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="106" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="110" mem-size="8" synchro="MASTER"/>
+ <Register name="RO_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="1">
+ <scalar format="int8"/>
+ </Register>
+ <Register name="RO_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="1" mem-size="1">
+ <scalar format="uint8"/>
+ </Register>
+ <Register name="RO_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="2" mem-size="2">
+ <scalar format="int16"/>
+ </Register>
+ <Register name="RO_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="uint16"/>
+ </Register>
+ <Register name="RO_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="6" mem-size="4">
+ <scalar format="int32"/>
+ </Register>
+ <Register name="RO_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="10" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="RO_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="14" mem-size="4">
+ <scalar format="float32"/>
+ </Register>
+ <Register name="RO_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="18" mem-size="66">
+ <string string-length="64" format="string"/>
+ </Register>
+ <Register name="RO_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="84" mem-size="8">
+ <scalar format="date"/>
+ </Register>
+ <Register name="RO_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="92" mem-size="1">
+ <scalar format="char"/>
+ </Register>
+ <Register name="RO_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="93" mem-size="1">
+ <scalar format="byte"/>
+ </Register>
+ <Register name="RO_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="94" mem-size="2">
+ <scalar format="word"/>
+ </Register>
+ <Register name="RO_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="96" mem-size="4">
+ <scalar format="dword"/>
+ </Register>
+ <Register name="RO_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="100" mem-size="2">
+ <scalar format="int"/>
+ </Register>
+ <Register name="RO_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="102" mem-size="4">
+ <scalar format="dint"/>
+ </Register>
+ <Register name="RO_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="106" mem-size="4">
+ <scalar format="real"/>
+ </Register>
+ <Register name="RO_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="110" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Block name="MyRWBlock" mode="READ-WRITE" size="212" address="2" mem-size="472">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="4" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="4" mem-size="4" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="8" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="16" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="24" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="40" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="56" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="72" mem-size="264" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="336" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="368" mem-size="4" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="372" mem-size="4" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="376" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="384" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="400" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="408" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="424" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="440" mem-size="32" synchro="MASTER"/>
+ <Register name="RW_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="4">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Register>
+ <Register name="RW_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="4" mem-size="4">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Register>
+ <Register name="RW_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="8" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Register>
+ <Register name="RW_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="16" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Register>
+ <Register name="RW_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="24" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Register>
+ <Register name="RW_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="40" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Register>
+ <Register name="RW_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="56" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Register>
+ <Register name="RW_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="72" mem-size="264">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Register>
+ <Register name="RW_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="336" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Register>
+ <Register name="RW_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="368" mem-size="4">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Register>
+ <Register name="RW_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="372" mem-size="4">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Register>
+ <Register name="RW_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="376" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Register>
+ <Register name="RW_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="384" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Register>
+ <Register name="RW_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="400" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Register>
+ <Register name="RW_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="408" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Register>
+ <Register name="RW_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="424" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Register>
+ <Register name="RW_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="440" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Register>
</Block>
<Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="3" mem-size="1180">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="10" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="20" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="40" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="60" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="100" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="140" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="180" mem-size="660" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="840" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="920" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="930" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="940" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="960" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="1000" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1020" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1060" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1100" mem-size="80" synchro="SLAVE"/>
+ <Register name="WO_int8" synchro="SLAVE" generateFesaValueItem="true" size="1" address="0" mem-size="10">
+ <array dim="10" format="int8"/>
+ </Register>
+ <Register name="WO_uint8" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="10" mem-size="10">
+ <array dim="10" format="uint8"/>
+ </Register>
+ <Register name="WO_int16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="20" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Register>
+ <Register name="WO_uint16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="40" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Register>
+ <Register name="WO_int32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="60" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Register>
+ <Register name="WO_uint32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="100" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Register>
+ <Register name="WO_float32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="140" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Register>
+ <Register name="WO_string" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="180" mem-size="660">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Register>
+ <Register name="WO_date" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="840" mem-size="80">
+ <array dim="10" format="date"/>
+ </Register>
+ <Register name="WO_char" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="920" mem-size="10">
+ <array dim="10" format="char"/>
+ </Register>
+ <Register name="WO_byte" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="930" mem-size="10">
+ <array dim="10" format="byte"/>
+ </Register>
+ <Register name="WO_word" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="940" mem-size="20">
+ <array dim="10" format="word"/>
+ </Register>
+ <Register name="WO_dword" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="960" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Register>
+ <Register name="WO_int" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="1000" mem-size="20">
+ <array dim="10" format="int"/>
+ </Register>
+ <Register name="WO_dint" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1020" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Register>
+ <Register name="WO_real" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1060" mem-size="40">
+ <array dim="10" format="real"/>
+ </Register>
+ <Register name="WO_dt" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1100" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Register>
</Block>
<Instance label="testDevice1" address="0"/>
<Instance label="testDevice2" address="1"/>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Siemens_TiaDevice.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Siemens_TiaDevice.silecsparam
index 766dea9..4938f35 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Siemens_TiaDevice.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Siemens_TiaDevice.silecsparam
@@ -2,76 +2,186 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 15:59:09.165849"/>
+ <Generation date="2017-06-06 11:12:20.553639"/>
<Deployment checksum="3940683809"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Siemens_TiaDevice" plc-brand="SIEMENS" plc-system="TIA-PORTAL" plc-model="SIMATIC_S7-300" protocol="DEVICE_MODE" address="0" domain="NotUsed" used-mem="TODO">
<SILECS-Class name="SilecsHeader" version="1.0.0" address="0" used-mem="DB0..DB0 / 48 bytes">
<Block name="hdrBlk" mode="READ-ONLY" size="14" address="0" mem-size="48">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="18" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="18" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="22" mem-size="18" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="40" mem-size="8" synchro="MASTER"/>
+ <Register name="_version" synchro="MASTER" size="1" address="0" mem-size="18">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_checksum" synchro="MASTER" size="4" address="18" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="_user" synchro="MASTER" size="1" address="22" mem-size="18">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_date" synchro="MASTER" size="8" address="40" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
<SILECS-Class name="AllTypes" version="0.1.0" address="1" used-mem="DB1..DB2 / 3540 bytes">
<Block name="MyROBlock" mode="READ-ONLY" size="53" address="0" mem-size="118">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="1" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="1" mem-size="1" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="2" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="6" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="10" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="14" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="18" mem-size="66" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="84" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="92" mem-size="1" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="93" mem-size="1" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="94" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="96" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="100" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="102" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="106" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="110" mem-size="8" synchro="MASTER"/>
+ <Register name="RO_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="1">
+ <scalar format="int8"/>
+ </Register>
+ <Register name="RO_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="1" mem-size="1">
+ <scalar format="uint8"/>
+ </Register>
+ <Register name="RO_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="2" mem-size="2">
+ <scalar format="int16"/>
+ </Register>
+ <Register name="RO_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="uint16"/>
+ </Register>
+ <Register name="RO_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="6" mem-size="4">
+ <scalar format="int32"/>
+ </Register>
+ <Register name="RO_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="10" mem-size="4">
+ <scalar format="uint32"/>
+ </Register>
+ <Register name="RO_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="14" mem-size="4">
+ <scalar format="float32"/>
+ </Register>
+ <Register name="RO_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="18" mem-size="66">
+ <string string-length="64" format="string"/>
+ </Register>
+ <Register name="RO_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="84" mem-size="8">
+ <scalar format="date"/>
+ </Register>
+ <Register name="RO_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="92" mem-size="1">
+ <scalar format="char"/>
+ </Register>
+ <Register name="RO_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="93" mem-size="1">
+ <scalar format="byte"/>
+ </Register>
+ <Register name="RO_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="94" mem-size="2">
+ <scalar format="word"/>
+ </Register>
+ <Register name="RO_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="96" mem-size="4">
+ <scalar format="dword"/>
+ </Register>
+ <Register name="RO_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="100" mem-size="2">
+ <scalar format="int"/>
+ </Register>
+ <Register name="RO_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="102" mem-size="4">
+ <scalar format="dint"/>
+ </Register>
+ <Register name="RO_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="106" mem-size="4">
+ <scalar format="real"/>
+ </Register>
+ <Register name="RO_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="110" mem-size="8">
+ <scalar format="dt"/>
+ </Register>
</Block>
<Block name="MyRWBlock" mode="READ-WRITE" size="212" address="118" mem-size="472">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="4" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="4" mem-size="4" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="8" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="16" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="24" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="40" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="56" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="72" mem-size="264" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="336" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="368" mem-size="4" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="372" mem-size="4" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="376" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="384" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="400" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="408" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="424" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="440" mem-size="32" synchro="MASTER"/>
+ <Register name="RW_int8" synchro="MASTER" generateFesaValueItem="true" size="1" address="0" mem-size="4">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Register>
+ <Register name="RW_uint8" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="4" mem-size="4">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Register>
+ <Register name="RW_int16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="8" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Register>
+ <Register name="RW_uint16" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="16" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Register>
+ <Register name="RW_int32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="24" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Register>
+ <Register name="RW_uint32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="40" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Register>
+ <Register name="RW_float32" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="56" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Register>
+ <Register name="RW_string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="72" mem-size="264">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Register>
+ <Register name="RW_date" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="336" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Register>
+ <Register name="RW_char" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="368" mem-size="4">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Register>
+ <Register name="RW_byte" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="372" mem-size="4">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Register>
+ <Register name="RW_word" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="376" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Register>
+ <Register name="RW_dword" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="384" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Register>
+ <Register name="RW_int" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="400" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Register>
+ <Register name="RW_dint" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="408" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Register>
+ <Register name="RW_real" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="424" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Register>
+ <Register name="RW_dt" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="440" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Register>
</Block>
<Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="590" mem-size="1180">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="10" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="20" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="40" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="60" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="100" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="140" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="180" mem-size="660" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="840" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="920" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="930" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="940" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="960" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="1000" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1020" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1060" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1100" mem-size="80" synchro="SLAVE"/>
+ <Register name="WO_int8" synchro="SLAVE" generateFesaValueItem="true" size="1" address="0" mem-size="10">
+ <array dim="10" format="int8"/>
+ </Register>
+ <Register name="WO_uint8" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="10" mem-size="10">
+ <array dim="10" format="uint8"/>
+ </Register>
+ <Register name="WO_int16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="20" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Register>
+ <Register name="WO_uint16" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="40" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Register>
+ <Register name="WO_int32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="60" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Register>
+ <Register name="WO_uint32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="100" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Register>
+ <Register name="WO_float32" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="140" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Register>
+ <Register name="WO_string" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="180" mem-size="660">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Register>
+ <Register name="WO_date" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="840" mem-size="80">
+ <array dim="10" format="date"/>
+ </Register>
+ <Register name="WO_char" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="920" mem-size="10">
+ <array dim="10" format="char"/>
+ </Register>
+ <Register name="WO_byte" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="930" mem-size="10">
+ <array dim="10" format="byte"/>
+ </Register>
+ <Register name="WO_word" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="940" mem-size="20">
+ <array dim="10" format="word"/>
+ </Register>
+ <Register name="WO_dword" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="960" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Register>
+ <Register name="WO_int" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="1000" mem-size="20">
+ <array dim="10" format="int"/>
+ </Register>
+ <Register name="WO_dint" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1020" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Register>
+ <Register name="WO_real" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1060" mem-size="40">
+ <array dim="10" format="real"/>
+ </Register>
+ <Register name="WO_dt" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1100" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Register>
</Block>
<Instance label="testDevice1" address="1"/>
<Instance label="testDevice2" address="2"/>
diff --git a/silecs-codegen/src/xml/xmltemplate.py b/silecs-codegen/src/xml/xmltemplate.py
index 19bdc3f..af23ae1 100644
--- a/silecs-codegen/src/xml/xmltemplate.py
+++ b/silecs-codegen/src/xml/xmltemplate.py
@@ -28,10 +28,18 @@ silecsHeader = """<?xml version="1.0" encoding="UTF-8"?>
</Information>
<SILECS-Class domain="TEST" name="SilecsHeader" version="1.0.0">
<Block mode="READ-ONLY" name="hdrBlk">
- <Register array-dim1="1" array-dim2="1" format="string" name="_version" string-len="16" synchro="MASTER"/>
- <Register array-dim1="1" array-dim2="1" format="uint32" name="_checksum" synchro="MASTER"/>
- <Register array-dim1="1" array-dim2="1" format="string" name="_user" string-len="16" synchro="MASTER"/>
- <Register array-dim1="1" array-dim2="1" format="dt" name="_date" synchro="MASTER"/>
+ <Register name="_version" synchro="MASTER">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_checksum" synchro="MASTER">
+ <scalar format="uint32" />
+ </Register>
+ <Register name="_user" synchro="MASTER">
+ <string string-length="16" format="string"/>
+ </Register>
+ <Register name="_date" synchro="MASTER">
+ <scalar format="dt" />
+ </Register>
</Block>
</SILECS-Class>
</SILECS-Design>
diff --git a/silecs-model/src/xml/DesignSchema.xsd b/silecs-model/src/xml/DesignSchema.xsd
index 6e53ecd..d6a75ca 100644
--- a/silecs-model/src/xml/DesignSchema.xsd
+++ b/silecs-model/src/xml/DesignSchema.xsd
@@ -180,9 +180,51 @@ along with this program. If not, see http://www.gnu.org/licenses/.-->
</xs:attribute>
</xs:complexType>
+
+<xs:complexType name="ScalarValueType">
+ <xs:attribute name="format" type="FormatType" use="required" />
+</xs:complexType>
+
+<xs:complexType name="ArrayValueType">
+ <xs:attribute name="format" type="FormatType" use="required" />
+ <xs:attribute name="dim" type="DimensionType" use="required"/>
+</xs:complexType>
+
+<xs:complexType name="Array2DValueType">
+ <xs:attribute name="format" type="FormatType" use="required" />
+ <xs:attribute name="dim1" type="DimensionType" use="required"/>
+ <xs:attribute name="dim2" type="DimensionType" use="required"/>
+</xs:complexType>
+
+<xs:complexType name="StringValueType">
+ <xs:attribute name="format" fixed="string" use="required" />
+ <xs:attribute name="string-length" type="LengthType" use="required"/>
+</xs:complexType>
+
+<xs:complexType name="StringArrayValueType">
+ <xs:attribute name="format" fixed="string" use="required" />
+ <xs:attribute name="string-length" type="LengthType" use="required"/>
+ <xs:attribute name="dim" type="DimensionType" use="required"/>
+</xs:complexType>
+
+<xs:complexType name="StringArray2DValueType">
+ <xs:attribute name="format" fixed="string" use="required" />
+ <xs:attribute name="string-length" type="LengthType" use="required"/>
+ <xs:attribute name="dim1" type="DimensionType" use="required"/>
+ <xs:attribute name="dim2" type="DimensionType" use="required"/>
+</xs:complexType>
+
<xs:complexType name="RegisterType">
<xs:sequence>
<xs:element name="Description" type="xs:string" minOccurs="0"/>
+ <xs:choice>
+ <xs:element name="scalar" type="ScalarValueType" />
+ <xs:element name="array" type="ArrayValueType" />
+ <xs:element name="array2D" type="Array2DValueType" />
+ <xs:element name="string" type="StringValueType" />
+ <xs:element name="stringArray" type="StringArrayValueType" />
+ <xs:element name="stringArray2D" type="StringArray2DValueType" />
+ </xs:choice>
</xs:sequence>
<xs:attribute name="name" type="RegisterNameType" use="required">
<xs:annotation>
@@ -191,68 +233,6 @@ along with this program. If not, see http://www.gnu.org/licenses/.-->
</xs:appinfo>
</xs:annotation>
</xs:attribute>
- <xs:attribute name="format" type="FormatType" use="required">
- <xs:annotation>
- <xs:appinfo>
- <doc>
- <table border = "1">
- <tr>
- <th align="center"> Hardware types </th>
- <th align="center"> Client process types </th>
- </tr>
- <tr>
- <td align="center"> uint8 / byte </td>
- <td align="center"> uint8_t </td>
- </tr>
- <tr>
- <td align="center"> int8 / char </td>
- <td align="center"> int8_t </td>
- </tr>
- <tr>
- <td align="center"> uint16 / word </td>
- <td align="center"> uint16_t </td>
- </tr>
- <tr>
- <td align="center"> int16 / int </td>
- <td align="center"> int16_t </td>
- </tr>
- <tr>
- <td align="center"> uint32 / dword </td>
- <td align="center"> uint32_t </td>
- </tr>
- <tr>
- <td align="center"> int32 / dint </td>
- <td align="center"> int32_t </td>
- </tr>
- <tr>
- <td align="center"> uint64 </td>
- <td align="center"> uint64_t </td>
- </tr>
- <tr>
- <td align="center"> int64 </td>
- <td align="center"> int64_t </td>
- </tr>
- <tr>
- <td align="center"> float32 / real </td>
- <td align="center"> float </td>
- </tr>
- <tr>
- <td align="center"> float64 </td>
- <td align="center"> double </td>
- </tr>
- <tr>
- <td align="center"> date / dt </td>
- <td align="center"> double </td>
- </tr>
- <tr>
- <td align="center"> string / char[] </td>
- <td align="center"> string </td>
- </tr>
- </table>
- </doc>
- </xs:appinfo>
- </xs:annotation>
- </xs:attribute>
<xs:attribute name="synchro" use="required">
<xs:annotation>
<xs:appinfo>
@@ -275,33 +255,6 @@ along with this program. If not, see http://www.gnu.org/licenses/.-->
</xs:restriction>
</xs:simpleType>
</xs:attribute>
- <xs:attribute name="array-dim1" type="DimensionType" use="optional" default="1">
- <xs:annotation>
- <xs:appinfo>
- <doc>
- specify register dimension.
- <br/> if array-dim1 = 1 the register is a scalar. If array-dim1 > 1 the register is an array.
- </doc>
- </xs:appinfo>
- </xs:annotation>
- </xs:attribute>
- <xs:attribute name="array-dim2" type="DimensionType" use="optional" default="1">
- <xs:annotation>
- <xs:appinfo>
- <doc>
- specify second register dimension.
- <br/> if array-dim2 = 1 the register is monodimensional. If array-dim2 > 1 the register is bidimensional.
- </doc>
- </xs:appinfo>
- </xs:annotation>
- </xs:attribute>
- <xs:attribute name="string-len" type="LengthType" use="optional">
- <xs:annotation>
- <xs:appinfo>
- <doc>specify length of string. If not specified, default value is 64.</doc>
- </xs:appinfo>
- </xs:annotation>
- </xs:attribute>
<xs:attribute name="generateFesaValueItem" type="xs:boolean" use="required">
<xs:annotation>
<xs:appinfo>
@@ -346,7 +299,6 @@ along with this program. If not, see http://www.gnu.org/licenses/.-->
<xs:enumeration value="int64"/>
<xs:enumeration value="float32"/>
<xs:enumeration value="float64"/>
- <xs:enumeration value="string"/>
<xs:enumeration value="date"/>
<xs:enumeration value="char"/>
<xs:enumeration value="byte"/>
--
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