diff --git a/jenkins.sh b/jenkins.sh
index a08590d1da684a1547e1c87e1362fa2c3baae613..bd8e69d753cfa904faf31f79d2b4a7dc1235a80d 100755
--- a/jenkins.sh
+++ b/jenkins.sh
@@ -1,28 +1,51 @@
#!/bin/sh
+set -e
+
+echo "##############################################"
+echo "configuration of build environment"
+echo "##############################################"
# $WORKSPACE is the jenkins workspace, will be filled by jenkins
export COMMON_MAKE_PATH="$WORKSPACE/../../generics/generic-makefiles"
export SNAP7_BASE="$WORKSPACE/snap7/snap7-full"
export BOOST_HOME="$WORKSPACE/../../generics/boost_1.54.0/boost/1.54.0"
+export SILECS_COMM_HOME="$WORKSPACE/silecs-communication-cpp/build"
-##############################################
+echo "##############################################"
+echo "building snap7"
+echo "##############################################"
cd snap7
./build.sh
cd ..
-##############################################
+echo "##############################################"
+echo "building silecs-communication-cpp"
+echo "##############################################"
cd silecs-communication-cpp
make clean
make all CPU=x86_64 -j4
cd ..
-##############################################
-cd silecs-codegen
-cd src/xml
-python runTest.py
+echo "##############################################"
+echo "building silecs-codegen"
+echo "##############################################"
+cd silecs-codegen/src/xml
+python runTests.py
cd ../../..
-##############################################
+echo "##############################################"
+echo "building silecs-diagnostic-cpp"
+echo "##############################################"
cd silecs-diagnostic-cpp
make clean
make CPU=x86_64 -j1
cd ..
-##############################################
+echo "##############################################"
+echo "building silecs-cli-client"
+echo "##############################################"
+cd silecs-cli-client
+make clean
+make CPU=x86_64 -j1
+cd ..
+echo "##############################################"
+echo "build finished sucessfully"
+echo "##############################################"
+
diff --git a/silecs-cli-client/.cproject b/silecs-cli-client/.cproject
new file mode 100644
index 0000000000000000000000000000000000000000..5fa0af23ed34d2b6b4b46419e137ace85e62d10b
--- /dev/null
+++ b/silecs-cli-client/.cproject
@@ -0,0 +1,135 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
+ <cconfiguration id="cdt.managedbuild.config.gnu.exe.debug.2141938844">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="cdt.managedbuild.config.gnu.exe.debug.2141938844" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+ <externalSettings/>
+ <extensions>
+ <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="cdt.managedbuild.config.gnu.exe.debug.2141938844" name="Debug" parent="cdt.managedbuild.config.gnu.exe.debug">
+ <folderInfo id="cdt.managedbuild.config.gnu.exe.debug.2141938844." name="/" resourcePath="">
+ <toolChain id="cdt.managedbuild.toolchain.gnu.exe.debug.148999669" name="Linux GCC" superClass="cdt.managedbuild.toolchain.gnu.exe.debug">
+ <targetPlatform id="cdt.managedbuild.target.gnu.platform.exe.debug.1502172553" name="Debug Platform" superClass="cdt.managedbuild.target.gnu.platform.exe.debug"/>
+ <builder buildPath="${workspace_loc:/silecs-cli-client}/Debug" id="cdt.managedbuild.target.gnu.builder.exe.debug.1879335443" managedBuildOn="true" name="Gnu Make Builder.Debug" superClass="cdt.managedbuild.target.gnu.builder.exe.debug"/>
+ <tool id="cdt.managedbuild.tool.gnu.archiver.base.1403566861" name="GCC Archiver" superClass="cdt.managedbuild.tool.gnu.archiver.base"/>
+ <tool id="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug.1842696123" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug">
+ <option id="gnu.cpp.compiler.exe.debug.option.optimization.level.1327874570" superClass="gnu.cpp.compiler.exe.debug.option.optimization.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.optimization.level.none" valueType="enumerated"/>
+ <option id="gnu.cpp.compiler.exe.debug.option.debugging.level.295080131" superClass="gnu.cpp.compiler.exe.debug.option.debugging.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.debugging.level.max" valueType="enumerated"/>
+ <inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.422825111" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
+ </tool>
+ <tool id="cdt.managedbuild.tool.gnu.c.compiler.exe.debug.716578848" name="GCC C Compiler" superClass="cdt.managedbuild.tool.gnu.c.compiler.exe.debug">
+ <option defaultValue="gnu.c.optimization.level.none" id="gnu.c.compiler.exe.debug.option.optimization.level.1945002178" superClass="gnu.c.compiler.exe.debug.option.optimization.level" useByScannerDiscovery="false" valueType="enumerated"/>
+ <option id="gnu.c.compiler.exe.debug.option.debugging.level.1863346534" superClass="gnu.c.compiler.exe.debug.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
+ <inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.1710627947" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
+ </tool>
+ <tool id="cdt.managedbuild.tool.gnu.c.linker.exe.debug.415604299" name="GCC C Linker" superClass="cdt.managedbuild.tool.gnu.c.linker.exe.debug"/>
+ <tool id="cdt.managedbuild.tool.gnu.cpp.linker.exe.debug.563268854" name="GCC C++ Linker" superClass="cdt.managedbuild.tool.gnu.cpp.linker.exe.debug">
+ <inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.634389681" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
+ <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+ <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+ </inputType>
+ </tool>
+ <tool id="cdt.managedbuild.tool.gnu.assembler.exe.debug.2024598489" name="GCC Assembler" superClass="cdt.managedbuild.tool.gnu.assembler.exe.debug">
+ <inputType id="cdt.managedbuild.tool.gnu.assembler.input.1509579893" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+ </tool>
+ </toolChain>
+ </folderInfo>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ <cconfiguration id="cdt.managedbuild.config.gnu.exe.release.958720723">
+ <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="cdt.managedbuild.config.gnu.exe.release.958720723" moduleId="org.eclipse.cdt.core.settings" name="Release">
+ <externalSettings/>
+ <extensions>
+ <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+ <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="cdt.managedbuild.config.gnu.exe.release.958720723" name="Release" parent="cdt.managedbuild.config.gnu.exe.release">
+ <folderInfo id="cdt.managedbuild.config.gnu.exe.release.958720723." name="/" resourcePath="">
+ <toolChain id="cdt.managedbuild.toolchain.gnu.exe.release.328873722" name="Linux GCC" superClass="cdt.managedbuild.toolchain.gnu.exe.release">
+ <targetPlatform id="cdt.managedbuild.target.gnu.platform.exe.release.1654063617" name="Debug Platform" superClass="cdt.managedbuild.target.gnu.platform.exe.release"/>
+ <builder buildPath="${workspace_loc:/silecs-cli-client}/Release" id="cdt.managedbuild.target.gnu.builder.exe.release.2000858798" managedBuildOn="true" name="Gnu Make Builder.Release" superClass="cdt.managedbuild.target.gnu.builder.exe.release"/>
+ <tool id="cdt.managedbuild.tool.gnu.archiver.base.1798805476" name="GCC Archiver" superClass="cdt.managedbuild.tool.gnu.archiver.base"/>
+ <tool id="cdt.managedbuild.tool.gnu.cpp.compiler.exe.release.1309368114" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.exe.release">
+ <option id="gnu.cpp.compiler.exe.release.option.optimization.level.702925897" superClass="gnu.cpp.compiler.exe.release.option.optimization.level" value="gnu.cpp.compiler.optimization.level.most" valueType="enumerated"/>
+ <option id="gnu.cpp.compiler.exe.release.option.debugging.level.346748341" superClass="gnu.cpp.compiler.exe.release.option.debugging.level" value="gnu.cpp.compiler.debugging.level.none" valueType="enumerated"/>
+ <inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.1555609612" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
+ </tool>
+ <tool id="cdt.managedbuild.tool.gnu.c.compiler.exe.release.762305723" name="GCC C Compiler" superClass="cdt.managedbuild.tool.gnu.c.compiler.exe.release">
+ <option defaultValue="gnu.c.optimization.level.most" id="gnu.c.compiler.exe.release.option.optimization.level.1247297257" superClass="gnu.c.compiler.exe.release.option.optimization.level" valueType="enumerated"/>
+ <option id="gnu.c.compiler.exe.release.option.debugging.level.1961744080" superClass="gnu.c.compiler.exe.release.option.debugging.level" value="gnu.c.debugging.level.none" valueType="enumerated"/>
+ <inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.1727621506" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
+ </tool>
+ <tool id="cdt.managedbuild.tool.gnu.c.linker.exe.release.1812801652" name="GCC C Linker" superClass="cdt.managedbuild.tool.gnu.c.linker.exe.release"/>
+ <tool id="cdt.managedbuild.tool.gnu.cpp.linker.exe.release.1740298277" name="GCC C++ Linker" superClass="cdt.managedbuild.tool.gnu.cpp.linker.exe.release">
+ <inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.1135886637" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
+ <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+ <additionalInput kind="additionalinput" paths="$(LIBS)"/>
+ </inputType>
+ </tool>
+ <tool id="cdt.managedbuild.tool.gnu.assembler.exe.release.309095766" name="GCC Assembler" superClass="cdt.managedbuild.tool.gnu.assembler.exe.release">
+ <inputType id="cdt.managedbuild.tool.gnu.assembler.input.1368235097" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+ </tool>
+ </toolChain>
+ </folderInfo>
+ </configuration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ </storageModule>
+ <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+ <project id="silecs-cli-client.cdt.managedbuild.target.gnu.exe.202646488" name="Executable" projectType="cdt.managedbuild.target.gnu.exe"/>
+ </storageModule>
+ <storageModule moduleId="scannerConfiguration">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ <scannerConfigBuildInfo instanceId="cdt.managedbuild.config.gnu.exe.debug.2141938844;cdt.managedbuild.config.gnu.exe.debug.2141938844.;cdt.managedbuild.tool.gnu.c.compiler.exe.debug.716578848;cdt.managedbuild.tool.gnu.c.compiler.input.1710627947">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </scannerConfigBuildInfo>
+ <scannerConfigBuildInfo instanceId="cdt.managedbuild.config.gnu.exe.debug.2141938844;cdt.managedbuild.config.gnu.exe.debug.2141938844.;cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug.1842696123;cdt.managedbuild.tool.gnu.cpp.compiler.input.422825111">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </scannerConfigBuildInfo>
+ <scannerConfigBuildInfo instanceId="cdt.managedbuild.config.gnu.exe.release.958720723;cdt.managedbuild.config.gnu.exe.release.958720723.;cdt.managedbuild.tool.gnu.c.compiler.exe.release.762305723;cdt.managedbuild.tool.gnu.c.compiler.input.1727621506">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </scannerConfigBuildInfo>
+ <scannerConfigBuildInfo instanceId="cdt.managedbuild.config.gnu.exe.release.958720723;cdt.managedbuild.config.gnu.exe.release.958720723.;cdt.managedbuild.tool.gnu.cpp.compiler.exe.release.1309368114;cdt.managedbuild.tool.gnu.cpp.compiler.input.1555609612">
+ <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+ </scannerConfigBuildInfo>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="refreshScope"/>
+ <storageModule moduleId="org.eclipse.cdt.make.core.buildtargets">
+ <buildTargets>
+ <target name="x86_64" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+ <buildCommand>make</buildCommand>
+ <buildArguments/>
+ <buildTarget>CPU=x86_64 -j4</buildTarget>
+ <stopOnError>true</stopOnError>
+ <useDefaultCommand>true</useDefaultCommand>
+ <runAllBuilders>true</runAllBuilders>
+ </target>
+ <target name="clean" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+ <buildCommand>make</buildCommand>
+ <buildArguments/>
+ <buildTarget>clean</buildTarget>
+ <stopOnError>true</stopOnError>
+ <useDefaultCommand>true</useDefaultCommand>
+ <runAllBuilders>true</runAllBuilders>
+ </target>
+ </buildTargets>
+ </storageModule>
+</cproject>
diff --git a/silecs-cli-client/.gitignore b/silecs-cli-client/.gitignore
new file mode 100644
index 0000000000000000000000000000000000000000..4a95481e611021403799e1b0a49ae9c4f18d2e2f
--- /dev/null
+++ b/silecs-cli-client/.gitignore
@@ -0,0 +1,2 @@
+/bin/
+/build/
diff --git a/silecs-cli-client/.project b/silecs-cli-client/.project
new file mode 100644
index 0000000000000000000000000000000000000000..78a830f597cddfe6fe7be061b3fa54fea18791a7
--- /dev/null
+++ b/silecs-cli-client/.project
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>silecs-cli-client</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+ <triggers>full,incremental,</triggers>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+ <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+ </natures>
+</projectDescription>
diff --git a/silecs-cli-client/.settings/language.settings.xml b/silecs-cli-client/.settings/language.settings.xml
new file mode 100644
index 0000000000000000000000000000000000000000..2e25a62948670e967fd05196e5cebe1b4de4e8b7
--- /dev/null
+++ b/silecs-cli-client/.settings/language.settings.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+ <configuration id="cdt.managedbuild.config.gnu.exe.debug.2141938844" name="Debug">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-226059455508497530" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+ <configuration id="cdt.managedbuild.config.gnu.exe.release.958720723" name="Release">
+ <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+ <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+ <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+ <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+ <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-226059455508497530" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <language-scope id="org.eclipse.cdt.core.gcc"/>
+ <language-scope id="org.eclipse.cdt.core.g++"/>
+ </provider>
+ </extension>
+ </configuration>
+</project>
diff --git a/silecs-cli-client/LICENSE b/silecs-cli-client/LICENSE
new file mode 100644
index 0000000000000000000000000000000000000000..20d40b6bceca3a6c0237d7455ebf1820aeff3680
--- /dev/null
+++ b/silecs-cli-client/LICENSE
@@ -0,0 +1,674 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
+ The GNU General Public License is a free, copyleft license for
+software and other kinds of works.
+
+ The licenses for most software and other practical works are designed
+to take away your freedom to share and change the works. By contrast,
+the GNU General Public License is intended to guarantee your freedom to
+share and change all versions of a program--to make sure it remains free
+software for all its users. We, the Free Software Foundation, use the
+GNU General Public License for most of our software; it applies also to
+any other work released this way by its authors. You can apply it to
+your programs, too.
+
+ When we speak of free software, we are referring to freedom, not
+price. Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+them if you wish), that you receive source code or can get it if you
+want it, that you can change the software or use pieces of it in new
+free programs, and that you know you can do these things.
+
+ To protect your rights, we need to prevent others from denying you
+these rights or asking you to surrender the rights. Therefore, you have
+certain responsibilities if you distribute copies of the software, or if
+you modify it: responsibilities to respect the freedom of others.
+
+ For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must pass on to the recipients the same
+freedoms that you received. You must make sure that they, too, receive
+or can get the source code. And you must show them these terms so they
+know their rights.
+
+ Developers that use the GNU GPL protect your rights with two steps:
+(1) assert copyright on the software, and (2) offer you this License
+giving you legal permission to copy, distribute and/or modify it.
+
+ For the developers' and authors' protection, the GPL clearly explains
+that there is no warranty for this free software. For both users' and
+authors' sake, the GPL requires that modified versions be marked as
+changed, so that their problems will not be attributed erroneously to
+authors of previous versions.
+
+ Some devices are designed to deny users access to install or run
+modified versions of the software inside them, although the manufacturer
+can do so. This is fundamentally incompatible with the aim of
+protecting users' freedom to change the software. The systematic
+pattern of such abuse occurs in the area of products for individuals to
+use, which is precisely where it is most unacceptable. Therefore, we
+have designed this version of the GPL to prohibit the practice for those
+products. If such problems arise substantially in other domains, we
+stand ready to extend this provision to those domains in future versions
+of the GPL, as needed to protect the freedom of users.
+
+ Finally, every program is threatened constantly by software patents.
+States should not allow patents to restrict development and use of
+software on general-purpose computers, but in those that do, we wish to
+avoid the special danger that patents applied to a free program could
+make it effectively proprietary. To prevent this, the GPL assures that
+patents cannot be used to render the program non-free.
+
+ The precise terms and conditions for copying, distribution and
+modification follow.
+
+ TERMS AND CONDITIONS
+
+ 0. Definitions.
+
+ "This License" refers to version 3 of the GNU General Public License.
+
+ "Copyright" also means copyright-like laws that apply to other kinds of
+works, such as semiconductor masks.
+
+ "The Program" refers to any copyrightable work licensed under this
+License. Each licensee is addressed as "you". "Licensees" and
+"recipients" may be individuals or organizations.
+
+ To "modify" a work means to copy from or adapt all or part of the work
+in a fashion requiring copyright permission, other than the making of an
+exact copy. The resulting work is called a "modified version" of the
+earlier work or a work "based on" the earlier work.
+
+ A "covered work" means either the unmodified Program or a work based
+on the Program.
+
+ To "propagate" a work means to do anything with it that, without
+permission, would make you directly or secondarily liable for
+infringement under applicable copyright law, except executing it on a
+computer or modifying a private copy. Propagation includes copying,
+distribution (with or without modification), making available to the
+public, and in some countries other activities as well.
+
+ To "convey" a work means any kind of propagation that enables other
+parties to make or receive copies. Mere interaction with a user through
+a computer network, with no transfer of a copy, is not conveying.
+
+ An interactive user interface displays "Appropriate Legal Notices"
+to the extent that it includes a convenient and prominently visible
+feature that (1) displays an appropriate copyright notice, and (2)
+tells the user that there is no warranty for the work (except to the
+extent that warranties are provided), that licensees may convey the
+work under this License, and how to view a copy of this License. If
+the interface presents a list of user commands or options, such as a
+menu, a prominent item in the list meets this criterion.
+
+ 1. Source Code.
+
+ The "source code" for a work means the preferred form of the work
+for making modifications to it. "Object code" means any non-source
+form of a work.
+
+ A "Standard Interface" means an interface that either is an official
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+interfaces specified for a particular programming language, one that
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+
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+
+ Nothing in this License shall be construed as excluding or limiting
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+
+ 12. No Surrender of Others' Freedom.
+
+ If conditions are imposed on you (whether by court order, agreement or
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+
+ 13. Use with the GNU Affero General Public License.
+
+ Notwithstanding any other provision of this License, you have
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+ 14. Revised Versions of this License.
+
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+be similar in spirit to the present version, but may differ in detail to
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+copy of the Program in return for a fee.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Programs
+
+ If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
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+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+ <one line to give the program's name and a brief idea of what it does.>
+ Copyright (C) <year> <name of author>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
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+notice like this when it starts in an interactive mode:
+
+ <program> Copyright (C) <year> <name of author>
+ This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, your program's commands
+might be different; for a GUI interface, you would use an "about box".
+
+ You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU GPL, see
+<http://www.gnu.org/licenses/>.
+
+ The GNU General Public License does not permit incorporating your program
+into proprietary programs. If your program is a subroutine library, you
+may consider it more useful to permit linking proprietary applications with
+the library. If this is what you want to do, use the GNU Lesser General
+Public License instead of this License. But first, please read
+<http://www.gnu.org/philosophy/why-not-lgpl.html>.
\ No newline at end of file
diff --git a/silecs-cli-client/Makefile b/silecs-cli-client/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..5bfd3419e3275e3342d2bdf1ccc27ce05b3eeba8
--- /dev/null
+++ b/silecs-cli-client/Makefile
@@ -0,0 +1,31 @@
+# Copyright 2016 CERN and GSI
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+PROJECT = silecs
+PRODUCT = cli-client
+VERSION = 1.0.2
+
+SKIP_MANIFEST = TRUE
+#local
+#COMMON_MAKE_PATH ?= /common/home/bel/schwinn/lnx/workspace-silecs-neon/generic-makefiles
+#global
+COMMON_MAKE_PATH ?= /opt/cern/buildsystem/generic/2.9.0
+
+# product configuration
+BIN_NAME = $(PROJECT)-$(PRODUCT)
+DBG = false
+
+# Include the generic make file
+include $(COMMON_MAKE_PATH)/Make.generic
\ No newline at end of file
diff --git a/silecs-cli-client/Makefile.dep b/silecs-cli-client/Makefile.dep
new file mode 100644
index 0000000000000000000000000000000000000000..678a51802841bbbeaade2408d0aae5ce8526df61
--- /dev/null
+++ b/silecs-cli-client/Makefile.dep
@@ -0,0 +1,24 @@
+BOOST_VERSION ?= 1.54.0
+SILECS_COMM_VERSION = 1.0.2
+
+BOOST_HOME ?= /acc/local/$(CPU)/3rdparty/boost/$(BOOST_VERSION)
+
+#for compile out of eclipse
+SILECS_COMM_HOME ?= ../../git/silecs-communication-cpp/build
+#SILECS_COMM_HOME ?= ../silecs-communication-cpp/build
+
+LIBXML_PATH ?= /usr/include/libxml2/
+
+#for compile out of eclipse
+SNAP7_BASE ?= ../../git/snap7/snap7-full
+#SNAP7_BASE ?= ../snap7/snap7-full
+
+DEPENDENT_COMPILER_OPTIONS += -I$(SILECS_COMM_HOME)/include
+DEPENDENT_COMPILER_OPTIONS += -I$(LIBXML_PATH)
+DEPENDENT_COMPILER_OPTIONS += -I$(BOOST_HOME)/include
+
+DEPENDENT_LINKER_OPTIONS += -L$(SILECS_COMM_HOME)/lib/$(CPU)
+DEPENDENT_LINKER_OPTIONS += -L$(SNAP7_BASE)/build/bin/$(CPU)-linux -lsnap7
+DEPENDENT_LINKER_OPTIONS += -L/usr/lib64 -lxml2
+DEPENDENT_LINKER_OPTIONS += -lsilecs-comm
+DEPENDENT_LINKER_OPTIONS += -lstdc++ -lxml2 -lcurl
diff --git a/silecs-cli-client/README.md b/silecs-cli-client/README.md
new file mode 100644
index 0000000000000000000000000000000000000000..d7aa52747755308a40e32c2dfe0f81cca4e4e333
--- /dev/null
+++ b/silecs-cli-client/README.md
@@ -0,0 +1,19 @@
+# silecs-cli-client
+
+This component of the SILECS PLC-framework allows to connect to a silecs-configured PLC by using the command-line
+
+## Getting Started
+
+Please check the lab-specific SILECS-Wikis for more information:
+
+[CERN SILECS Wiki Page][CERN_Wiki]
+
+[GSI SILECS Wiki Page][GSI_Wiki]
+
+## License
+
+Licensed under the GNU GENERAL PUBLIC LICENSE Version 3. See the [LICENSE file][license] for details.
+
+[license]: LICENSE
+[CERN_Wiki]: https://wikis.cern.ch/display/SIL/SILECs+Home
+[GSI_Wiki]: https://www-acc.gsi.de/wiki/Frontend/SILECS
\ No newline at end of file
diff --git a/silecs-cli-client/examples/getBlock.sh b/silecs-cli-client/examples/getBlock.sh
new file mode 100755
index 0000000000000000000000000000000000000000..6989c0c53c631832263d9c9239373a5dda6b6b6e
--- /dev/null
+++ b/silecs-cli-client/examples/getBlock.sh
@@ -0,0 +1,28 @@
+#!/bin/sh
+set -e
+
+CPU="x86_64"
+SCRIPT=$(readlink -f "$0")
+SCRIPTPATH=$(dirname "$SCRIPT") # path where this script is located in
+
+#SNAP7_PATH=${SCRIPTPATH}/../../../git/snap7/snap7-full/build/bin/${CPU}-linux #local
+SNAP7_PATH=${SCRIPTPATH}/../../../snap7/2.0.0/bin/${CPU}-linux
+
+#BINARY="${SCRIPTPATH}/../build/bin/${CPU}/silecs-cli-client" #local
+BINARY="${SCRIPTPATH}/../bin/${CPU}/silecs-cli-client"
+
+export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$SNAP7_PATH
+echo "##### LD_LIBRARY_PATH: ###################################################################################"
+echo "$LD_LIBRARY_PATH"
+echo "##########################################################################################################"
+echo ""
+
+PARAM_FILE=/common/home/bel/schwinn/lnx/workspace-silecs-neon/SiemensTestDU/generated/client/tsts7001.silecsparam
+BLOCK=MyAcquisitionBlock
+DEVICE=MyDevice1
+
+# config for SiemensTestDU
+ARGUMENTS="-f $PARAM_FILE -b $BLOCK -d $DEVICE -m GET_BLOCK"
+COMMAND="$BINARY $ARGUMENTS"
+$COMMAND
+
diff --git a/silecs-cli-client/examples/getDevice.sh b/silecs-cli-client/examples/getDevice.sh
new file mode 100755
index 0000000000000000000000000000000000000000..7399a96e4b24eb99c6804482e87fe3ff18b7eb0a
--- /dev/null
+++ b/silecs-cli-client/examples/getDevice.sh
@@ -0,0 +1,27 @@
+#!/bin/sh
+set -e
+
+CPU="x86_64"
+SCRIPT=$(readlink -f "$0")
+SCRIPTPATH=$(dirname "$SCRIPT") # path where this script is located in
+
+#SNAP7_PATH=${SCRIPTPATH}/../../../git/snap7/snap7-full/build/bin/${CPU}-linux #local
+SNAP7_PATH=${SCRIPTPATH}/../../../snap7/2.0.0/bin/${CPU}-linux
+
+#BINARY="${SCRIPTPATH}/../build/bin/${CPU}/silecs-cli-client" #local
+BINARY="${SCRIPTPATH}/../bin/${CPU}/silecs-cli-client"
+
+export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$SNAP7_PATH
+echo "##### LD_LIBRARY_PATH: ###################################################################################"
+echo "$LD_LIBRARY_PATH"
+echo "##########################################################################################################"
+echo ""
+
+PARAM_FILE=/common/home/bel/schwinn/lnx/workspace-silecs-neon/SiemensTestDU/generated/client/tsts7001.silecsparam
+DEVICE=MyDevice1
+
+# config for SiemensTestDU
+ARGUMENTS="-f $PARAM_FILE -d $DEVICE -m GET_DEVICE"
+COMMAND="$BINARY $ARGUMENTS"
+$COMMAND
+
diff --git a/silecs-cli-client/examples/getRegister_periodic.sh b/silecs-cli-client/examples/getRegister_periodic.sh
new file mode 100755
index 0000000000000000000000000000000000000000..b5c1209de37a293b75808521cda5d9cba300a24f
--- /dev/null
+++ b/silecs-cli-client/examples/getRegister_periodic.sh
@@ -0,0 +1,29 @@
+#!/bin/sh
+set -e
+
+CPU="x86_64"
+SCRIPT=$(readlink -f "$0")
+SCRIPTPATH=$(dirname "$SCRIPT") # path where this script is located in
+
+#SNAP7_PATH=${SCRIPTPATH}/../../../git/snap7/snap7-full/build/bin/${CPU}-linux #local
+SNAP7_PATH=${SCRIPTPATH}/../../../snap7/2.0.0/bin/${CPU}-linux
+
+#BINARY="${SCRIPTPATH}/../build/bin/${CPU}/silecs-cli-client" #local
+BINARY="${SCRIPTPATH}/../bin/${CPU}/silecs-cli-client"
+
+export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$SNAP7_PATH
+echo "##### LD_LIBRARY_PATH: ###################################################################################"
+echo "$LD_LIBRARY_PATH"
+echo "##########################################################################################################"
+echo ""
+
+PARAM_FILE=/common/home/bel/schwinn/lnx/workspace-silecs-neon/SiemensTestDU/generated/client/tsts7001.silecsparam
+REGISTER=DQ_Anlog00
+DEVICE=MyDevice1
+DELAY_MICRO_SEC=100000
+
+# config for SiemensTestDU
+ARGUMENTS="-f $PARAM_FILE -p $DELAY_MICRO_SEC -d $DEVICE -r $REGISTER -m GET_REGISTER"
+COMMAND="$BINARY $ARGUMENTS"
+$COMMAND
+
diff --git a/silecs-cli-client/examples/interactive.sh b/silecs-cli-client/examples/interactive.sh
new file mode 100755
index 0000000000000000000000000000000000000000..faee41547fec8ed22f56f2aa5c57bb944e1c065e
--- /dev/null
+++ b/silecs-cli-client/examples/interactive.sh
@@ -0,0 +1,26 @@
+#!/bin/sh
+set -e
+
+CPU="x86_64"
+SCRIPT=$(readlink -f "$0")
+SCRIPTPATH=$(dirname "$SCRIPT") # path where this script is located in
+
+
+#SNAP7_PATH=${SCRIPTPATH}/../../../git/snap7/snap7-full/build/bin/${CPU}-linux #local
+SNAP7_PATH=${SCRIPTPATH}/../../../snap7/2.0.0/bin/${CPU}-linux
+
+#BINARY="${SCRIPTPATH}/../build/bin/${CPU}/silecs-cli-client" #local
+BINARY="${SCRIPTPATH}/../bin/${CPU}/silecs-cli-client"
+
+export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$SNAP7_PATH
+echo "##### LD_LIBRARY_PATH: ###################################################################################"
+echo "$LD_LIBRARY_PATH"
+echo "##########################################################################################################"
+echo ""
+
+PARAM_FILE=/common/home/bel/schwinn/lnx/workspace-silecs-neon/SiemensTestDU/generated/client/tsts7001.silecsparam
+
+# config for SiemensTestDU
+ARGUMENTS="-f $PARAM_FILE -i -c"
+COMMAND="$BINARY $ARGUMENTS"
+$COMMAND
diff --git a/silecs-cli-client/install.sh b/silecs-cli-client/install.sh
new file mode 100755
index 0000000000000000000000000000000000000000..9664c3ba34b5ea02229ebabb7d6df91cb4deff24
--- /dev/null
+++ b/silecs-cli-client/install.sh
@@ -0,0 +1,11 @@
+#!/bin/sh
+set -e
+
+INSTALL_DIR=$1
+
+SCRIPT=$(readlink -f "$0")
+SCRIPTPATH=$(dirname "$SCRIPT") # path where this script is located in
+
+mkdir -p ${INSTALL_DIR}
+cp -r ${SCRIPTPATH}/build/bin ${INSTALL_DIR}
+cp -r ${SCRIPTPATH}/examples ${INSTALL_DIR}
\ No newline at end of file
diff --git a/silecs-cli-client/src/silecs-cli-client/main.cpp b/silecs-cli-client/src/silecs-cli-client/main.cpp
new file mode 100755
index 0000000000000000000000000000000000000000..f63b4de88b12ec239202c7c8f383c8498c0dcbc2
--- /dev/null
+++ b/silecs-cli-client/src/silecs-cli-client/main.cpp
@@ -0,0 +1,616 @@
+// Copyright 2016 CERN and GSI
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <getopt.h>
+#include <termios.h>// getch
+#include <iostream>
+#include <iomanip> // std::right, etc
+#include <unistd.h>//usleep
+
+#include <silecs-communication/interface/utility/XMLParser.h>
+#include <silecs-communication/interface/core/SilecsService.h>
+#include <silecs-communication/interface/equipment/SilecsCluster.h>
+#include <silecs-communication/interface/equipment/SilecsDevice.h>
+#include <silecs-communication/interface/equipment/SilecsRegister.h>
+
+#include <boost/assign/list_of.hpp> // init vector of strings
+
+const std::string startbold = "\e[1m";
+const std::string endbold = "\e[0m";
+
+enum ModeType { UNDEFINED, GET_DEVICE, GET_BLOCK, GET_REGISTER, SET_REGISTER };
+
+std::string arg_logTopics; //comma separated list ? space-separated ?
+std::string arg_parameterFile = "";
+std::string arg_plcName = "";
+std::string arg_deviceName = "";
+std::string arg_blockName = "";
+std::string arg_registerName = "";
+bool arg_silent = false;
+bool arg_verbose = false;
+bool arg_checkChecksum = true;
+ModeType arg_mode = UNDEFINED;
+uint32_t periodicInterval = 0;
+
+char* log_arg_base[2] = {(char*)"-plcLog",(char*)"ERROR,COMM"};
+char* log_arg_verbose[2] = {(char*)"-plcLog",(char*)"ERROR,DEBUG,SETUP,ALLOC,LOCK,COMM,SEND,RECV,DATA,DIAG"};
+
+void printHelp()
+{
+ std::cout << std::endl;
+ std::cout << startbold << "NAME" << endbold << std::endl;
+ std::cout << "\tsilecs-cli-client - Command Line Client to connect to a silecs-configured PLC" << std::endl;
+ std::cout << std::endl;
+
+ std::cout << startbold << "SYNOPSIS" << endbold << std::endl;
+ std::cout << "\tsilecs-cli-client - [OPTIONS]" << std::endl;
+ std::cout << std::endl;
+
+ std::cout << startbold << "DESCRIPTION" << endbold << std::endl;
+ std::cout << "\t Connect to a PLC and get/set values by using the Silecs-framework." << std::endl;
+ std::cout << startbold << "\t-b " << endbold << "silecs-block to get" << std::endl;
+ std::cout << startbold << "\t-c " << endbold << "ignore silecs-checksum, force connect to PLC" << std::endl;
+ std::cout << startbold << "\t-d " << endbold << "silecs-device to request" << std::endl;
+ std::cout << startbold << "\t-f " << endbold << "path to silecs-parameter-file of the plc" << std::endl;
+ std::cout << startbold << "\t-h " << endbold << "print this help" << std::endl;
+ std::cout << startbold << "\t-i " << endbold << "start interactive session" << std::endl; // TODO: Implement
+ std::cout << startbold << "\t-v " << endbold << "verbose, all LOGTOPICS are enabled" << std::endl; // TODO: Implement
+ //std::cout << startbold << "\t-m " << endbold << "mode, can be 'GET_DEVICE', 'GET_BLOCK', 'GET_REGISTER' or 'SET_REGISTER'" << std::endl;
+ std::cout << startbold << "\t-m " << endbold << "mode, can be 'GET_DEVICE', 'GET_BLOCK' or 'GET_REGISTER'" << std::endl;
+ std::cout << startbold << "\t-p " << endbold << "periodic Interval(ms) us ? to measure" << std::endl;
+ std::cout << startbold << "\t-r " << endbold << "optional, register to get/set" << std::endl;
+ std::cout << startbold << "\t-s " << endbold << "silent, minimal output (only the register-values, no meta information)" << std::endl;
+
+ std::cout << std::endl;
+
+ std::cout << startbold << "AUTHOR" << endbold << std::endl;
+ std::cout << "\t Written by Alexander Schwinn" << std::endl;
+ std::cout << std::endl;
+
+ std::cout << startbold << "REPORTING BUGS" << endbold << std::endl;
+ std::cout << "\t Please contact the author vie the gsi mail-address" << std::endl;
+ std::cout << std::endl;
+
+ std::cout << startbold << "COPYRIGHT" << endbold << std::endl;
+ std::cout << "\tCopyright © 2017 Free Software Foundation, Inc. License GPLv3+: GNU" << std::endl;
+ std::cout << "\tGPL version 3 or later <http://gnu.org/licenses/gpl.html>." << std::endl;
+ std::cout << "\tThis is free software: you are free to change and redistribute it." << std::endl;
+ std::cout << "\tThere is NO WARRANTY, to the extent permitted by law." << std::endl;
+ std::cout << std::endl;
+}
+
+/* reads from keypress, doesn't echo */
+int getch(void)
+{
+ struct termios oldattr, newattr;
+ int ch;
+ tcgetattr( STDIN_FILENO, &oldattr );
+ newattr = oldattr;
+ newattr.c_lflag &= ~( ICANON | ECHO );
+ tcsetattr( STDIN_FILENO, TCSANOW, &newattr );
+ ch = getchar();
+ tcsetattr( STDIN_FILENO, TCSANOW, &oldattr );
+ return ch;
+}
+
+//returns -1 for "return to previous menu" or array-index of list
+int querryUserPickFromList(std::vector<std::string> &list)
+{
+ int selection = -1;
+ std::vector<std::string>::iterator item;
+ while(selection < 0 || (unsigned int)selection > list.size())
+ {
+ int itemIndex = 1;
+ std::cout << std::endl;
+ std::cout << "The following options are available:" << std::endl;
+ std::cout << std::endl;
+ for( item = list.begin();item!= list.end(); item++)
+ {
+ std::cout << std::setw(5) << std::right << itemIndex << ": " << std::setw(30) << std::left << *item << std::endl;
+ itemIndex++;
+ }
+
+ std::cout << std::endl;
+ std::cout << std::setw(5) << std::right << "0" << ": " << std::setw(30) << std::left << "return to previous menu" << std::endl;
+ std::cout << std::endl;
+ std::cout << "Waiting for your selection ";
+ int input = getch();
+ std::cout << std::endl;
+ selection = input - 48; //ascii magic
+ if( selection < 0 || (unsigned int)selection > list.size() )
+ {
+ std::cout << "Invalid input: '" << input << "'. press any key to take another try!" << std::endl;
+ getch();
+ }
+ }
+ return selection-1; // -1 = return ... everything else is array-index
+}
+
+std::string getPLCName(Silecs::XMLParser ¶mParser)
+{
+ Silecs::ElementXML mappingNode = paramParser.getFirstElementFromXPath("/SILECS-Param/SILECS-Mapping");
+ return mappingNode.getAttribute("plc-name");
+}
+
+Silecs::Cluster* getSilecsClusterbyDevice(std::string deviceName, Silecs::XMLParser ¶mParser, Silecs::Service *silecsService)
+{
+ Silecs::ElementXML classNode = paramParser.getFirstElementFromXPath("/SILECS-Param/SILECS-Mapping/SILECS-Class[Instance/@label='"+ deviceName + "']");
+ std::string className = classNode.getAttribute("name");
+ std::string classVersion = classNode.getAttribute("version");
+ return silecsService->getCluster(className,classVersion);
+}
+
+std::string getSilecsBlockNamebyRegisterName(std::string registerName, Silecs::XMLParser ¶mParser)
+{
+ Silecs::ElementXML blockNode = paramParser.getFirstElementFromXPath("/SILECS-Param/SILECS-Mapping/SILECS-Class/*[*/@name='"+ registerName + "']");
+ return blockNode.getAttribute("name");
+}
+
+bool isRegisterInBlock(std::string registerName, std::string blockName, Silecs::XMLParser ¶mParser)
+{
+ Silecs::ElementXML blockNode = paramParser.getFirstElementFromXPath("/SILECS-Param/SILECS-Mapping/SILECS-Class/*[*/@name='"+ registerName + "']");
+ if( blockName == blockNode.getAttribute("name"))
+ return true;
+ return false;
+}
+
+std::vector<std::string> getDeviceNames(Silecs::XMLParser ¶mParser)
+{
+ std::vector< std::string > deviceNames;
+ boost::ptr_vector<Silecs::ElementXML> deviceNodes = paramParser.getElementsFromXPath_throwIfEmpty("/SILECS-Param/SILECS-Mapping/SILECS-Class/Instance");
+ boost::ptr_vector<Silecs::ElementXML>::iterator deviceNode;
+ for( deviceNode = deviceNodes.begin();deviceNode!= deviceNodes.end(); deviceNode++)
+ {
+ deviceNames.push_back(deviceNode->getAttribute("label"));
+ }
+ return deviceNames;
+}
+
+std::vector<std::string> getBlockNamesFromDeviceName(std::string deviceName, Silecs::XMLParser ¶mParser)
+{
+ std::vector< std::string > blockNames;
+ Silecs::ElementXML classNode = paramParser.getFirstElementFromXPath("/SILECS-Param/SILECS-Mapping/SILECS-Class[Instance/@label='"+ deviceName + "']");
+ std::string className = classNode.getAttribute("name");
+ boost::ptr_vector<Silecs::ElementXML> blocks = paramParser.getElementsFromXPath_throwIfEmpty("/SILECS-Param/SILECS-Mapping/SILECS-Class[@name='"+ className + "']/*[ name()='Acquisition-Block' or name()='Setting-Block' or name()='Command-Block']");
+ boost::ptr_vector<Silecs::ElementXML>::iterator block;
+ for( block = blocks.begin();block!= blocks.end(); block++)
+ {
+ //std::cout<< block->getAttribute("name") << std::endl;
+ blockNames.push_back(block->getAttribute("name"));
+ }
+ return blockNames;
+}
+
+std::vector<std::string> getRegisterNamesFromDeviceBlockName(std::string deviceName, std::string blockName, Silecs::XMLParser ¶mParser)
+{
+ std::vector< std::string > registerNames;
+ Silecs::ElementXML classNode = paramParser.getFirstElementFromXPath("/SILECS-Param/SILECS-Mapping/SILECS-Class[Instance/@label='"+ deviceName + "']");
+ std::string className = classNode.getAttribute("name");
+ boost::ptr_vector<Silecs::ElementXML> registerNodes = paramParser.getElementsFromXPath_throwIfEmpty("/SILECS-Param/SILECS-Mapping/SILECS-Class[@name='"+ className + "']/*[@name='"+ blockName + "']/*[ name()='Acquisition-Register' or name()='Setting-Register' or name()='Volatile-Register']");
+ boost::ptr_vector<Silecs::ElementXML>::iterator registerNode;
+ for( registerNode = registerNodes.begin();registerNode!= registerNodes.end(); registerNode++)
+ {
+ //std::cout<< block->getAttribute("name") << std::endl;
+ registerNames.push_back(registerNode->getAttribute("name"));
+ }
+ return registerNames;
+}
+
+std::string getRegisterValueAsString(Silecs::Register* reg )
+{
+ std::ostringstream os;
+ uint32_t dim1 = reg->getDimension1();
+ uint32_t dim2 = reg->getDimension2();
+ for (unsigned int i=0; i<dim1; i++)
+ for (unsigned int j=0; j<dim2; j++)
+ os << reg->getInputValAsString(i, j) << " ";
+ return os.str();
+}
+
+void printTableHead()
+{
+ std::cout << "------------------------------------------------------------------------------------------------------------------------------------------------" << std::endl;
+ std::cout << "| "<< std::setw(20) << std::left << "Device" << "| " << std::setw(30) << std::left << "Block" << "| " << std::setw(50) << std::left << "Register" << "| " << std::setw(30) << std::left<< "Value" << "|" << std::endl;
+ std::cout << "------------------------------------------------------------------------------------------------------------------------------------------------" << std::endl;
+}
+
+void printRunState(Silecs::PLC *plc)
+{
+ std::cout << "------------------------------------------------------------------------------------------------------------------------------------------------" << std::endl;
+ if( plc->isRunning() )
+ std::cout << "plc run-state is: RUNNING" << std::endl;
+ else
+ std::cout << "plc run-state is: STOPPED" << std::endl;
+ std::cout << "------------------------------------------------------------------------------------------------------------------------------------------------" << std::endl;
+}
+
+void printRegister(Silecs::Device *device, Silecs::Register* reg )
+{
+ if( arg_silent )
+ {
+ std::cout << getRegisterValueAsString(reg) << std::endl;
+ }
+ else
+ {
+ std::cout << "| " << std::setw(20) << std::left << device->getLabel() << "| " << std::setw(30) << std::left << reg->getBlockName() << "| " << std::setw(50) << std::left << reg->getName() << "| " << std::setw(30) << std::left << getRegisterValueAsString(reg) << "|" << std::endl;
+ }
+}
+
+void printBlock(Silecs::Device *device, std::string blockName,Silecs::XMLParser ¶mParser)
+{
+ device->recv(blockName);
+ std::vector<Silecs::Register*> regCol = device->getRegisterCollection(blockName);
+ std::vector<Silecs::Register*>::iterator reg;
+ for (reg = regCol.begin();reg != regCol.end(); reg++ )
+ {
+ if(isRegisterInBlock((*reg)->getName(), blockName, paramParser))
+ {
+ printRegister(device, *reg);
+ }
+ }
+}
+
+void printDevice(Silecs::Device *device, Silecs::XMLParser ¶mParser)
+{
+ std::vector<std::string> blockNames = getBlockNamesFromDeviceName(device->getLabel(), paramParser);
+ std::vector<std::string>::iterator blockName;
+ for( blockName = blockNames.begin();blockName!= blockNames.end(); blockName++)
+ {
+ device->recv(*blockName);
+ std::vector<Silecs::Register*> regCol = device->getRegisterCollection(*blockName);
+ std::vector<Silecs::Register*>::iterator reg;
+ for (reg = regCol.begin();reg != regCol.end(); reg++ )
+ {
+ printRegister(device, *reg);
+ }
+ }
+}
+
+void setRegister(Silecs::Register* reg,std::string value)
+{
+ std::cout << "Error: Setting values not yet supported."<< std::endl;
+ exit(EXIT_FAILURE);
+}
+
+int connectInteractive(Silecs::Service *service, Silecs::XMLParser ¶mParser)
+{
+ std::vector<std::string> mainMenu = boost::assign::list_of("connect to plc-device")("select block")("select register")("print whole device")("print block")("print register")("query plc run state")("cold-restart plc");
+ Silecs::Cluster *silecsCluster = NULL;
+ Silecs::PLC *plc = NULL;
+ Silecs::Device *device = NULL;
+ Silecs::Register* reg = NULL;
+
+ while(true)
+ {
+ std::cout << std::setw(20) << std::right << "Device:" << std::setw(20) << std::left << startbold << arg_deviceName << endbold <<std::endl;
+ std::cout << std::setw(20) << std::right << "Block:" << std::setw(20) << std::left << startbold << arg_blockName << endbold <<std::endl;
+ std::cout << std::setw(20) << std::right << "Register:" << std::setw(20) << std::left << startbold << arg_registerName << endbold <<std::endl;
+ int item = querryUserPickFromList(mainMenu);
+ switch(item)
+ {
+ case -1:
+ return EXIT_SUCCESS;
+ case 0:
+ {
+ std::vector<std::string> devices = getDeviceNames(paramParser);
+ int index = querryUserPickFromList(devices);
+ if( index == -1 )
+ break;
+ arg_deviceName = devices[index];
+ arg_blockName = "";
+ arg_registerName = "";
+ silecsCluster = getSilecsClusterbyDevice(arg_deviceName, paramParser, service);
+ plc = silecsCluster->getPLC(getPLCName(paramParser),arg_parameterFile);
+ plc->connect(Silecs::MASTER_SYNCHRO,true,arg_checkChecksum);
+ device = plc->getDevice(arg_deviceName);
+ break;
+ }
+ case 1:
+ {
+ if(arg_deviceName.empty())
+ {
+ std::cout << "Please select a device first! - Press any key to continue." << std::endl;
+ getch();
+ break;
+ }
+ std::vector<std::string> blocks = getBlockNamesFromDeviceName(arg_deviceName,paramParser);
+ int index = querryUserPickFromList(blocks);
+ if( index == -1 )
+ break;
+ arg_blockName = blocks[index];
+ arg_registerName = "";
+ break;
+ }
+ case 2:
+ {
+ if(arg_deviceName.empty() || arg_blockName.empty() )
+ {
+ std::cout << "Please connect to a device first! - Press any key to continue." << std::endl;
+ getch();
+ break;
+ }
+ std::vector<std::string> registers = getRegisterNamesFromDeviceBlockName(arg_deviceName,arg_blockName,paramParser);
+ int index = querryUserPickFromList(registers);
+ if( index == -1 )
+ break;
+ arg_registerName = registers[index];
+ reg = device->getRegister(arg_registerName);
+ break;
+ }
+ case 3:
+ if(arg_deviceName.empty())
+ {
+ std::cout << "Please connect to a device first! - Press any key to continue." << std::endl;
+ getch();
+ break;
+ }
+ printTableHead();
+ printDevice(device, paramParser);
+ break;
+ case 4:
+ if(arg_deviceName.empty() || arg_blockName.empty())
+ {
+ std::cout << "Please first connect to a device and select a block! - Press any key to continue." << std::endl;
+ getch();
+ break;
+ }
+ printTableHead();
+ printBlock(device, arg_blockName, paramParser);
+ break;
+ case 5:
+ if(arg_deviceName.empty() || arg_blockName.empty() || arg_registerName.empty())
+ {
+ std::cout << "Please first connect to device and pick a block and a register! - Press any key to continue." << std::endl;
+ getch();
+ break;
+ }
+ printTableHead();
+ printRegister(device,reg );
+ break;
+ case 6:
+ if(arg_deviceName.empty())
+ {
+ std::cout << "Please connect to a device first! - Press any key to continue." << std::endl;
+ getch();
+ break;
+ }
+ printRunState(plc);
+ break;
+ case 7:
+ if(arg_deviceName.empty())
+ {
+ std::cout << "Please connect to a device first! - Press any key to continue." << std::endl;
+ getch();
+ break;
+ }
+ plc->sendColdRestart();
+ break;
+ default:
+ std::cout << "Invalid option:" << item << std::endl;
+ return EXIT_FAILURE;
+ }
+ }
+
+ return EXIT_SUCCESS;
+}
+
+int connectNonInteractive(Silecs::Service *service, Silecs::XMLParser ¶mParser, bool periodicOptionSet)
+{
+ Silecs::Cluster *silecsCluster = getSilecsClusterbyDevice(arg_deviceName, paramParser, service);
+ Silecs::PLC *plc = silecsCluster->getPLC(getPLCName(paramParser),arg_parameterFile);
+ plc->connect(Silecs::MASTER_SYNCHRO,true,arg_checkChecksum);
+ if(!plc->isConnected())
+ {
+ std::cout << "Error: Failed to connect to PLC."<< std::endl;
+ return EXIT_FAILURE;
+ }
+
+ if( !arg_silent )
+ {
+ printRunState(plc);
+ }
+ Silecs::Device *device = plc->getDevice(arg_deviceName);
+
+ Silecs::Register* reg = NULL;
+ if(!arg_registerName.empty())
+ {
+ reg = device->getRegister(arg_registerName);
+ arg_blockName = getSilecsBlockNamebyRegisterName(arg_registerName, paramParser);
+ }
+
+ if( !arg_silent )
+ {
+ printTableHead();
+ }
+
+ do
+ {
+ switch(arg_mode)
+ {
+ case GET_DEVICE:
+ printDevice(device,paramParser);
+ break;
+ case GET_BLOCK:
+ printBlock(device, arg_blockName, paramParser);
+ break;
+ case GET_REGISTER:
+ device->recv(arg_blockName);
+ printRegister(device, reg);
+ break;
+ case SET_REGISTER:
+ setRegister(reg,"");
+ break;
+ default:
+ std::cout << "Unknown mode defined by -m" << std::endl;
+ return EXIT_FAILURE;
+ }
+ usleep(periodicInterval);
+ }while ( periodicOptionSet );
+
+
+ return EXIT_SUCCESS;
+}
+
+
+
+int main(int argc, char **argv)
+{
+ try
+ {
+ int opt;
+ bool interactiveOptionSet = false;
+ bool periodicOptionSet = false;
+
+ while ((opt = getopt(argc, argv, ":vhcp:r:b:d:f:m:is")) != -1)
+ {
+
+ switch (opt)
+ {
+ case 'c':
+ arg_checkChecksum = false;
+ break;
+ case 'h':
+ printHelp();
+ return EXIT_SUCCESS;
+ case 'v':
+ arg_verbose = true;
+ break;
+ case 'p':
+ {
+ if(interactiveOptionSet)
+ {
+ std::cout << "Error: options '-i' and '-p' are mutually exclusive " << std::endl;
+ printHelp();
+ return EXIT_FAILURE;
+ }
+ periodicOptionSet = true;
+ std::istringstream ss(optarg);
+ ss >> periodicInterval;
+ break;
+ }
+ case 'r':
+ arg_registerName.assign(optarg);
+ break;
+ case 'd':
+ arg_deviceName.assign(optarg);
+ break;
+ case 'f':
+ arg_parameterFile.assign(optarg);
+ break;
+ case 'b':
+ arg_blockName.assign(optarg);
+ break;
+ case 'm':
+ {
+ std::string mode;
+ mode.assign(optarg);
+
+ if(mode == "GET_DEVICE")
+ arg_mode = GET_DEVICE;
+ else if( mode == "GET_BLOCK")
+ arg_mode = GET_BLOCK;
+ else if( mode == "GET_REGISTER")
+ arg_mode = GET_REGISTER;
+ else if( mode == "SET_REGISTER")
+ arg_mode = SET_REGISTER;
+ else
+ {
+ std::cout << "Error: invalid mode passed. Please check the help:" << std::endl;
+ printHelp();
+ return EXIT_FAILURE;
+ }
+ break;
+ }
+ case 'i':
+ if(interactiveOptionSet)
+ {
+ std::cout << "Error: options '-i' and '-p' are mutually exclusive " << std::endl;
+ printHelp();
+ return EXIT_FAILURE;
+ }
+ interactiveOptionSet = true;
+ break;
+ case 's':
+ arg_silent = true;
+ break;
+ case '?':
+ std::cout << "Unrecognized option: " << optopt << std::endl;
+
+ }
+ }
+
+ if( arg_mode == GET_BLOCK && arg_blockName.empty())
+ {
+ std::cout << "Error: No block-name specified, cannot execute GET_BLOCK" << std::endl;
+ printHelp();
+ return EXIT_FAILURE;
+ }
+
+ if( ( arg_mode == GET_REGISTER || arg_mode == SET_REGISTER ) && arg_registerName.empty())
+ {
+ std::cout << "Error: No block-name specified, cannot execute GET_REGISTER or SET_REGISTER" << std::endl;
+ printHelp();
+ return EXIT_FAILURE;
+ }
+
+ if( arg_parameterFile.empty() )
+ {
+ std::cout << "Error: no parameter-file was passed. You need to at least pass -f [filename]" << std::endl;
+ printHelp();
+ return EXIT_FAILURE;
+ }
+
+ Silecs::XMLParser::init();
+ Silecs::XMLParser paramParser(arg_parameterFile,true);
+ Silecs::Service *silecsService = NULL;
+ if(arg_verbose)
+ silecsService = Silecs::Service::getInstance(2,log_arg_verbose);
+ else
+ silecsService = Silecs::Service::getInstance(2,log_arg_base);
+
+ if(interactiveOptionSet)
+ {
+ return connectInteractive(silecsService, paramParser);
+ }
+ else
+ {
+ if( arg_deviceName.empty() )
+ {
+ std::cout << "Error: no deviceName was passed. You need to pass -d [devicename]" << std::endl;
+ printHelp();
+ return EXIT_FAILURE;
+ }
+ return connectNonInteractive(silecsService, paramParser, periodicOptionSet );
+ }
+
+ return EXIT_SUCCESS;
+ }
+ catch(std::string *str)
+ {
+ std::cout << str << std::endl;
+ }
+ catch(std::exception& ex)
+ {
+ std::cout << ex.what() << std::endl;
+ }
+ catch(...)
+ {
+ std::cout << "Unexpected error caught in Main. Please notify SILECS support" << std::endl;
+ }
+ return -1;
+}
diff --git a/silecs-codegen/.project b/silecs-codegen/.project
index d8a27b477aebaf971619fa0ff83654a04205ffc4..fc18960fb921896114e9062816360f751b0aeb27 100644
--- a/silecs-codegen/.project
+++ b/silecs-codegen/.project
@@ -5,7 +5,13 @@
<projects>
</projects>
<buildSpec>
+ <buildCommand>
+ <name>org.python.pydev.PyDevBuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
</buildSpec>
<natures>
+ <nature>org.python.pydev.pythonNature</nature>
</natures>
</projectDescription>
diff --git a/silecs-codegen/.pydevproject b/silecs-codegen/.pydevproject
new file mode 100644
index 0000000000000000000000000000000000000000..40e9f40a0ade3a088c757afd454acb9750da90c3
--- /dev/null
+++ b/silecs-codegen/.pydevproject
@@ -0,0 +1,5 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?eclipse-pydev version="1.0"?><pydev_project>
+<pydev_property name="org.python.pydev.PYTHON_PROJECT_INTERPRETER">Default</pydev_property>
+<pydev_property name="org.python.pydev.PYTHON_PROJECT_VERSION">python 2.7</pydev_property>
+</pydev_project>
diff --git a/silecs-codegen/README.md b/silecs-codegen/README.md
index a5e382f8130b53a8742069d0e76622107f890ba1..852f1dbe3efd41463ad71b4886a45ca62addf1e6 100644
--- a/silecs-codegen/README.md
+++ b/silecs-codegen/README.md
@@ -16,4 +16,4 @@ Licensed under the GNU GENERAL PUBLIC LICENSE Version 3. See the [LICENSE file][
[license]: LICENSE
[CERN_Wiki]: https://wikis.cern.ch/display/SIL/SILECs+Home
-[GSI_Wiki]: https://www-acc.gsi.de/wiki/Frontend/SILECS
\ No newline at end of file
+[GSI_Wiki]: https://www-acc.gsi.de/wiki/Frontend/SILECS
diff --git a/silecs-codegen/jenkins.sh b/silecs-codegen/jenkins.sh
deleted file mode 100755
index ec0824653036ec35619018b05ae91ef53b192791..0000000000000000000000000000000000000000
--- a/silecs-codegen/jenkins.sh
+++ /dev/null
@@ -1,8 +0,0 @@
-#!/bin/sh
-
-#export COMMON_MAKE_PATH="$WORKSPACE/../../generics/generic-makefiles"
-#export SNAP7_BASE="$WORKSPACE/../snap7/snap7-full"
-#export BOOST_HOME="$WORKSPACE/../../generics/boost_1.54.0/boost/1.54.0"
-#make all CPU=x86_64 -j4
-cd src/xml
-python runTests.py
diff --git a/silecs-codegen/src/xml/fesa/fesa_3_0_0/fesaTemplates.py b/silecs-codegen/src/xml/fesa/fesa_3_0_0/fesaTemplates.py
index 2406e29d2155bf31e4e36709aaae9d8f52085ff0..f5709632cd4ceac1c9d92e9f5b3be3d764ccbc89 100644
--- a/silecs-codegen/src/xml/fesa/fesa_3_0_0/fesaTemplates.py
+++ b/silecs-codegen/src/xml/fesa/fesa_3_0_0/fesaTemplates.py
@@ -14,9 +14,6 @@
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
-import iecommon
-import time
-
#=========================================================================
# FESA .cproject file
#=========================================================================
@@ -98,25 +95,26 @@ cproject = """<?xml version="1.0" encoding="UTF-8" standalone="no"?>
#=========================================================================
# H Source template (.h file)
#=========================================================================
-hTop = """/*
- * %s.h
+
+htop = """/*
+ * ${className}.h
*
* Generated by SILECS framework tools
*/
-#ifndef %s_%s_H_
-#define %s_%s_H_
+#ifndef ${className}_${className}_H_
+#define ${className}_${className}_H_
#include <SilecsService.h>
#include <fesa-core/Synchronization/MultiplexingContext.h>
-#include <%s/GeneratedCode/ServiceLocator.h>
- """
+#include <${className}/GeneratedCode/ServiceLocator.h>
+"""
-hTopBlock = """#include <%s/Server/%s.h>
- """
+hTopBlock = """#include <${className}/Server/${blockName}.h>
+"""
hTop2 = """
-namespace %s
+namespace ${className}
{
/*---------------------------------------------------------------------------------------------------------
@@ -150,7 +148,7 @@ namespace %s
* --------------------------------------------------------------------------------------------------------
*/
- class Abstract%s
+ class Abstract${className}
{
public:
static inline Silecs::Service* theService() { return pService_; }
@@ -159,11 +157,12 @@ namespace %s
static void setup(const ServiceLocator* serviceLocator);
static void cleanup();
+ static bool isInitialized(){ return Abstract${className}::isInitialized_; }
static void setPLCSlaveRegisters(Silecs::PLC* pPLC, const ServiceLocator* serviceLocator);
static void getPLCMasterRegisters(Silecs::PLC* pPLC, const ServiceLocator* serviceLocator);
- Abstract%s(std::string blockName);
- virtual ~Abstract%s();
+ Abstract${className}(std::string blockName);
+ virtual ~Abstract${className}();
void getAllDevices(const ServiceLocator* serviceLocator, const bool recvNow, MultiplexingContext* pContext);
void getPLCDevices(Silecs::PLC* pPLC, const ServiceLocator* serviceLocator, const bool recvNow, MultiplexingContext* pContext);
@@ -185,45 +184,45 @@ namespace %s
std::string blockName_;
// not copyable object
- Abstract%s(const Abstract%s&);
- Abstract%s& operator=(const Abstract%s&);
+ Abstract${className}(const Abstract${className}&);
+ Abstract${className}& operator=(const Abstract${className}&);
};
// -------------------------------------------------------------------------------------------------
- #define BLOCK_RO( name )\t\\
- class name##_Type : public Abstract%s\t\\
+ #define BLOCK_RO( blockName, propName )\t\\
+ class blockName##_Type : public Abstract${className}\t\\
{\t\\
public:\t\\
- name##_Type(std::string name);\t\\
- ~name##_Type();\t\\
+ blockName##_Type(std::string name);\t\\
+ ~blockName##_Type();\t\\
void getOneDevice(Device* pDevice, const bool transmitNow, MultiplexingContext* pContext);\t\\
}
- #define BLOCK_WO( name )\t\\
- class name##_Type : public Abstract%s\t\\
+ #define BLOCK_WO( blockName, propName )\t\\
+ class blockName##_Type : public Abstract${className}\t\\
{\t\\
public:\t\\
- name##_Type(std::string name);\t\\
- ~name##_Type();\t\\
+ blockName##_Type(std::string name);\t\\
+ ~blockName##_Type();\t\\
void setOneDevice(Device* pDevice, const bool transmitNow, MultiplexingContext* pContext);\t\\
- void setOneDevice(Device* pDevice, name##PropertyData& data, const bool transmitNow, MultiplexingContext* pContext);\t\\
+ void setOneDevice(Device* pDevice, propName##PropertyData& data, const bool transmitNow, MultiplexingContext* pContext);\t\\
}
- #define BLOCK_RW( name )\t\\
- class name##_Type : public Abstract%s\t\\
+ #define BLOCK_RW( blockName, propName )\t\\
+ class blockName##_Type : public Abstract${className}\t\\
{\t\\
public:\t\\
- name##_Type(std::string name);\t\\
- ~name##_Type();\t\\
+ blockName##_Type(std::string name);\t\\
+ ~blockName##_Type();\t\\
void getOneDevice(Device* pDevice, const bool transmitNow, MultiplexingContext* pContext);\t\\
void setOneDevice(Device* pDevice, const bool transmitNow, MultiplexingContext* pContext);\t\\
- void setOneDevice(Device* pDevice, name##PropertyData& data, const bool transmitNow, MultiplexingContext* pContext);\t\\
+ void setOneDevice(Device* pDevice, propName##PropertyData& data, const bool transmitNow, MultiplexingContext* pContext);\t\\
}
"""
-hBlock = """BLOCK_%s( %s );
+hBlock = """BLOCK_${mode}( ${blockName}, ${propName} );
"""
hBottom = """
@@ -232,68 +231,72 @@ hBottom = """
*---------------------------------------------------------------------------------------------------------
* This is the public interface used from the FESA code to access the PLC service.
*/
- class %s
+ class ${className}
{
public:
- static inline Silecs::Service* theService() { return Abstract%s::theService(); }
- static inline Silecs::Cluster* theCluster() { return Abstract%s::theCluster(); }
- static void setup(const ServiceLocator* serviceLocator) { Abstract%s::setup(serviceLocator); }
- static void cleanup() { Abstract%s::cleanup(); }
-
+ static inline Silecs::Service* theService() { return Abstract${className}::theService(); }
+ static inline Silecs::Cluster* theCluster() { return Abstract${className}::theCluster(); }
+ static void setup(const ServiceLocator* serviceLocator) { Abstract${className}::setup(serviceLocator); }
+ static void cleanup() { Abstract${className}::cleanup(); }
+ static bool isInitialized(){ return Abstract${className}::isInitialized(); }
+ static Silecs::PLC* getPLC(Device* pDevice)
+ {
+ return Abstract${className}::theCluster()->getPLC(pDevice->plcHostName.get(),pDevice->parameterFile.get());
+ }
"""
-hDeclBlocks = """ static %s_Type %s;
- """
+hDeclBlocks = """
+ static ${className}_Type ${className};"""
hClosing = """
};
}
- #endif /* %s_%s_H_ */
+ #endif /* ${className}_${className}_H_ */
"""
#=========================================================================
# C++ Source template (.cpp file)
#=========================================================================
cTop = """/*
- * %s.cpp
+ * ${className}.cpp
*
* Generated by SILECS framework tools
*/
-#include <%s/Common/%s.h>
+#include <${className}/Common/${className}.h>
#include <fesa-core/Synchronization/NoneContext.h>
#include <fesa-core/Synchronization/MultiplexingContext.h>
-namespace %s
+namespace ${className}
{
//Global objects of the SILECS class
- Silecs::Service* Abstract%s::pService_ = NULL;
- Silecs::Cluster* Abstract%s::pCluster_ = NULL;
- bool Abstract%s::isInitialized_ = false;
+ Silecs::Service* Abstract${className}::pService_ = NULL;
+ Silecs::Cluster* Abstract${className}::pCluster_ = NULL;
+ bool Abstract${className}::isInitialized_ = false;
"""
-cGlobal = """%s_Type\t%s::%s("%s");
+cGlobal = """${blockName}_Type\t${className}::${blockName}("${blockName}");
"""
cPart1 = """
//-------------------------------------------------------------------------------------------------------------
// Constructor & Destructor methods
- Abstract%s::Abstract%s(std::string blockName): blockName_(blockName) {}
- Abstract%s::~Abstract%s() {}
+ Abstract${className}::Abstract${className}(std::string blockName): blockName_(blockName) {}
+ Abstract${className}::~Abstract${className}() {}
"""
cBlockConstr = """
- %s_Type::%s_Type(std::string name): Abstract%s(name) {}
- %s_Type::~%s_Type() {}
+ ${blockName}_Type::${blockName}_Type(std::string name): Abstract${className}(name) {}
+ ${blockName}_Type::~${blockName}_Type() {}
"""
cPart2 = """
//---------------------------------------------------------------------------------------------------------
- // Set-up the SILECS components for the Abstract%s class (service & cluster)
+ // Set-up the SILECS components for the Abstract${className} class (service & cluster)
- void Abstract%s::setup(const ServiceLocator* serviceLocator)
+ void Abstract${className}::setup(const ServiceLocator* serviceLocator)
{
try
{
@@ -305,7 +308,7 @@ cPart2 = """
// Instantiate the SILECS Cluster object for the given Class/Version
GlobalDevice* pGlobalDevice = serviceLocator->getGlobalDevice();
- pCluster_ = pService_->getCluster( "%s", pGlobalDevice->plcClassVersion.get());
+ pCluster_ = pService_->getCluster( "${className}", pGlobalDevice->plcClassVersion.get());
isInitialized_ = true;
// Connect each PLC of the Cluster that is referred from the FESA instance
@@ -339,7 +342,7 @@ cPart2 = """
//---------------------------------------------------------------------------------------------------------
// Release all the SILECS resources
- void Abstract%s::cleanup()
+ void Abstract${className}::cleanup()
{
// Attention! This method is responsible to stop all the PLC connections
// and to remove all the SILECS resources (Clusters and related components: PLCs, Devices, Registers, ..)
@@ -350,24 +353,24 @@ cPart2 = """
//---------------------------------------------------------------------------------------------------------
// Synchronise PLC SLAVE/MASTER registers and related FESA fields (automatically called by the setup method @connection time)
- void Abstract%s::setPLCSlaveRegisters(Silecs::PLC* pPLC, const ServiceLocator* serviceLocator)
+ void Abstract${className}::setPLCSlaveRegisters(Silecs::PLC* pPLC, const ServiceLocator* serviceLocator)
{
fesa::NoneContext noneContext;
"""
cSetPLC = """
- %s::%s.setPLCDevices(pPLC, serviceLocator, false, &noneContext);"""
+ ${className}::${blockName}.setPLCDevices(pPLC, serviceLocator, false, &noneContext);"""
cPart3 = """
}
- void Abstract%s::getPLCMasterRegisters(Silecs::PLC* pPLC, const ServiceLocator* serviceLocator)
+ void Abstract${className}::getPLCMasterRegisters(Silecs::PLC* pPLC, const ServiceLocator* serviceLocator)
{
fesa::NoneContext noneContext; //MASTER acquisition fields are not consistent, can be set with none-context
"""
cGetPLC = """
- %s::%s.getPLCDevices(pPLC, serviceLocator, false, &noneContext);"""
+ ${className}::${blockName}.getPLCDevices(pPLC, serviceLocator, false, &noneContext);"""
cPart4 = """
}
@@ -380,7 +383,7 @@ cPart4 = """
//---------------------------------------------------------------------------------------------------------
- void Abstract%s::getAllDevices(const ServiceLocator* serviceLocator, const bool recvNow, MultiplexingContext* pContext)
+ void Abstract${className}::getAllDevices(const ServiceLocator* serviceLocator, const bool recvNow, MultiplexingContext* pContext)
{
if (recvNow) theCluster()->recv(blockName_);
@@ -390,7 +393,7 @@ cPart4 = """
}
}
- void Abstract%s::getPLCDevices(Silecs::PLC* pPLC, const ServiceLocator* serviceLocator, const bool recvNow, MultiplexingContext* pContext)
+ void Abstract${className}::getPLCDevices(Silecs::PLC* pPLC, const ServiceLocator* serviceLocator, const bool recvNow, MultiplexingContext* pContext)
{
if (recvNow) pPLC->recv(blockName_);
@@ -402,18 +405,18 @@ cPart4 = """
}
}
- void Abstract%s::getSomeDevices(std::vector<Device*> deviceCol, const bool sendNow, MultiplexingContext* pContext)
+ void Abstract${className}::getSomeDevices(std::vector<Device*> deviceCol, const bool sendNow, MultiplexingContext* pContext)
{
for(std::vector<Device*>::iterator pDeviceIter=deviceCol.begin(); pDeviceIter!= deviceCol.end(); pDeviceIter++)
{ getOneDevice(*pDeviceIter, sendNow, pContext);
}
}
- void Abstract%s::getOneDevice(Device* pDevice, const bool recvNow, MultiplexingContext* pContext) {};
+ void Abstract${className}::getOneDevice(Device* pDevice, const bool recvNow, MultiplexingContext* pContext) {};
//---------------------------------------------------------------------------------------------------------
- void Abstract%s::setAllDevices(const ServiceLocator* serviceLocator, bool sendNow, MultiplexingContext* pContext)
+ void Abstract${className}::setAllDevices(const ServiceLocator* serviceLocator, bool sendNow, MultiplexingContext* pContext)
{
std::vector<Device*> deviceCol = serviceLocator->getDeviceCollection();
for(std::vector<Device*>::iterator pDeviceIter=deviceCol.begin(); pDeviceIter!= deviceCol.end(); pDeviceIter++)
@@ -423,7 +426,7 @@ cPart4 = """
if (sendNow) theCluster()->send(blockName_);
}
- void Abstract%s::setPLCDevices(Silecs::PLC* pPLC, const ServiceLocator* serviceLocator, bool sendNow, MultiplexingContext* pContext)
+ void Abstract${className}::setPLCDevices(Silecs::PLC* pPLC, const ServiceLocator* serviceLocator, bool sendNow, MultiplexingContext* pContext)
{
std::vector<Device*> deviceCol = serviceLocator->getDeviceCollection();
for(std::vector<Device*>::iterator pDeviceIter=deviceCol.begin(); pDeviceIter!= deviceCol.end(); pDeviceIter++)
@@ -435,101 +438,99 @@ cPart4 = """
if (sendNow) pPLC->send(blockName_);
}
- void Abstract%s::setSomeDevices(std::vector<Device*> deviceCol, bool sendNow, MultiplexingContext* pContext)
+ void Abstract${className}::setSomeDevices(std::vector<Device*> deviceCol, bool sendNow, MultiplexingContext* pContext)
{
for(std::vector<Device*>::iterator pDeviceIter=deviceCol.begin(); pDeviceIter!= deviceCol.end(); pDeviceIter++)
{ setOneDevice(*pDeviceIter, sendNow, pContext);
}
}
- void Abstract%s::setOneDevice(Device* pDevice, const bool sendNow, MultiplexingContext* pContext) {};
+ void Abstract${className}::setOneDevice(Device* pDevice, const bool sendNow, MultiplexingContext* pContext) {};
//---------------------------------------------------------------------------------------------------------
"""
cCommonGet = """
- void %s_Type::getOneDevice(Device* pDevice, const bool recvNow, MultiplexingContext* pContext)
+ void ${blockName}_Type::getOneDevice(Device* pDevice, const bool recvNow, MultiplexingContext* pContext)
{
if( !isInitialized_ )
{
- throw fesa::FesaException(__FILE__, __LINE__, "SILECS-Service not initialized yet - %s::setup needs to be called before any plc-interaction can be done");
+ throw fesa::FesaException(__FILE__, __LINE__, "SILECS-Service not initialized yet - ${className}::setup needs to be called before any plc-interaction can be done");
}
Silecs::PLC* pPLC = pCluster_->getPLC(pDevice->plcHostName.get(),pDevice->parameterFile.get());
Silecs::Device* pPLCDevice = pPLC->getDevice(pDevice->plcDeviceLabel.get());
"""
-cRegVar = """ Silecs::Register* pRegister = NULL;
-"""
-
-cGetArrayVar = """ uint32_t dim1 = 1;
-"""
-cGetArray2DVar = """ uint32_t dim2 = 1;
-"""
-cSetArrayVar = """ uint32_t dim1 = 1;
- uint32_t fesaDim1;
-"""
-cSetArray2DVar = """ uint32_t dim2 = 1;
- uint32_t fesaDim2;
-"""
-
cRecv = """ if (recvNow) pPLCDevice -> recv(blockName_);
"""
cGetStringReg = """
- pRegister = pPLCDevice->getRegister("%s");
- pDevice->%s.set(pRegister->getValString().c_str(), pContext);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("${regName}");
+ pDevice->${fesaFieldName}.set(pRegister->getValString().c_str(), pContext);
+ }
"""
cGetStringArrayReg = """
{
- pRegister = pPLCDevice->getRegister("%s");
- dim1 = pRegister->getDimension1();
- const std::string** stdStringArray = pRegister->getRefStringArray(dim1);
- for (unsigned int i=0; i<dim1; i++)
- { pDevice->%s.setString(stdStringArray[i]->c_str(), i, pContext);
- }
+ Silecs::Register* pRegister = pPLCDevice->getRegister("${regName}");
+ uint32_t dim1 = pRegister->getDimension1();
+ const std::string** stdStringArray = pRegister->getRefStringArray(dim1);
+ for (unsigned int i=0; i<dim1; i++)
+ {
+ pDevice->${fesaFieldName}.setString(stdStringArray[i]->c_str(), i, pContext);
+ }
}
"""
cGetScalarReg = """
- pDevice->%s.set( pPLCDevice->getRegister("%s")->getVal%s(), pContext);"""
+ pDevice->${fesaFieldName}.set( pPLCDevice->getRegister("${regName}")->getVal${regType}(), pContext);"""
cGetArrayReg = """
- pRegister = pPLCDevice->getRegister("%s");
- dim1 = pRegister->getDimension1();
- pDevice->%s.set(pRegister->getRef%sArray(dim1), dim1, pContext);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("${regName}");
+ uint32_t dim1 = pRegister->getDimension1();
+ pDevice->${fesaFieldName}.set(pRegister->getRef${regType}Array(dim1), dim1, pContext);
+ }
"""
cGetArray2DReg = """
- pRegister = pPLCDevice->getRegister("%s");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pDevice->%s.set(pRegister->getRef%sArray2D(dim1, dim2), dim1, dim2, pContext);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("${regName}");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ pDevice->${fesaFieldName}.set(pRegister->getRef${regType}Array2D(dim1, dim2), dim1, dim2, pContext);
+ }
"""
+
cGetUnsignedArrayReg = """
- pRegister = pPLCDevice->getRegister("%s");
- dim1 = pRegister->getDimension1();
- %s* %s = (%s*)calloc(dim1, sizeof(%s));
- pRegister->getVal%sArray(%s, dim1);\t//use automatic conversion for JAVA non-supported type
- pDevice->%s.set(%s, dim1, pContext);
- free(%s);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("${regName}");
+ uint32_t dim1 = pRegister->getDimension1();
+ ${regType}* ${regName} = (${regType}*)calloc(dim1, sizeof(${regType}));
+ pRegister->getVal${regType}Array(${regName}, dim1);\t//use automatic conversion for JAVA non-supported type
+ pDevice->${fesaFieldName}.set(${regName}, dim1, pContext);
+ free(${regName});
+ }
"""
cGetUnsignedArray2DReg = """
- pRegister = pPLCDevice->getRegister("%s");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- %s* %s = (%s*)calloc(dim1*dim2, sizeof(%s));
- pRegister->getVal%sArray2D(%s, dim1, dim2);\t//use automatic conversion for JAVA non-supported type
- pDevice->%s.set(%s, dim1, dim2, pContext);
- free(%s);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("${regName}");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ ${fesaType}* ${regName} = (${fesaType}*)calloc(dim1*dim2, sizeof(${fesaType}));
+ pRegister->getVal${regType}Array2D(${regName}, dim1, dim2);\t//use automatic conversion for JAVA non-supported type
+ pDevice->${fesaFieldName}.set(${regName}, dim1, dim2, pContext);
+ free(${regName});
+ }
"""
cCommonSet = """
- void %s_Type::setOneDevice(Device* pDevice, const bool sendNow, MultiplexingContext* pContext)
+ void ${blockName}_Type::setOneDevice(Device* pDevice, const bool sendNow, MultiplexingContext* pContext)
{
if( !isInitialized_ )
{
- throw fesa::FesaException(__FILE__, __LINE__, "SILECS-Service not initialized yet - %s::setup needs to be called before any plc-interaction can be done");
+ throw fesa::FesaException(__FILE__, __LINE__, "SILECS-Service not initialized yet - ${className}::setup needs to be called before any plc-interaction can be done");
}
Silecs::PLC* pPLC = pCluster_->getPLC(pDevice->plcHostName.get(),pDevice->parameterFile.get());
Silecs::Device* pPLCDevice = pPLC->getDevice(pDevice->plcDeviceLabel.get());
@@ -540,117 +541,121 @@ cSend = """
"""
cDatatypeSet = """
- void %s_Type::setOneDevice(Device* pDevice, %sPropertyData& data, bool sendNow, MultiplexingContext* pContext)
+ void ${blockName}_Type::setOneDevice(Device* pDevice, ${propName}PropertyData& data, bool sendNow, MultiplexingContext* pContext)
{
if( !isInitialized_ )
{
- throw fesa::FesaException(__FILE__, __LINE__, "SILECS-Service not initialized yet - %s::setup needs to be called before any plc-interaction can be done");
+ throw fesa::FesaException(__FILE__, __LINE__, "SILECS-Service not initialized yet - ${className}::setup needs to be called before any plc-interaction can be done");
}
Silecs::PLC* pPLC = pCluster_->getPLC(pDevice->plcHostName.get(),pDevice->parameterFile.get());
Silecs::Device* pPLCDevice = pPLC->getDevice(pDevice->plcDeviceLabel.get());
"""
cSetStringReg = """
- pPLCDevice->getRegister("%s")->setValString(pDevice->%s.get(pContext));
+ pPLCDevice->getRegister("${regName}")->setValString(pDevice->${fesaFieldName}.get(pContext));
"""
cSetStringArrayReg = """
{
- pRegister = pPLCDevice->getRegister("%s");
- dim1 = pRegister->getDimension1();
- std::string stdStringArray[dim1];
- const char** cStringArray = pDevice->%s.get(fesaDim1, pContext);
- for (unsigned int i=0; i<dim1; i++) stdStringArray[i] = (const char*)cStringArray[i];
- pRegister->setValStringArray(stdStringArray, dim1);
+ Silecs::Register* pRegister = pPLCDevice->getRegister("${regName}");
+ uint32_t dim1 = pRegister->getDimension1();
+ std::string stdStringArray[dim1];
+ uint32_t fesaDim1;
+ const char** cStringArray = pDevice->${fesaFieldName}.get(fesaDim1, pContext);
+ for (unsigned int i=0; i<dim1; i++) stdStringArray[i] = (const char*)cStringArray[i];
+ pRegister->setValStringArray(stdStringArray, dim1);
}
"""
cSetScalarReg = """
- pPLCDevice->getRegister("%s")->setVal%s( pDevice->%s.get(pContext));"""
+ pPLCDevice->getRegister("${regName}")->setVal${regType}( pDevice->${fesaFieldName}.get(pContext));"""
cSetScalarUReg = """
- pPLCDevice->getRegister("%s")->setVal%s( (%s)pDevice->%s.get(pContext));"""
+ pPLCDevice->getRegister("${regName}")->setVal${regType}( (${cType})pDevice->${fesaFieldName}.get(pContext));"""
cSetArrayReg = """
- pRegister = pPLCDevice->getRegister("%s");
- dim1 = pRegister->getDimension1();
- pRegister->setVal%sArray(pDevice->%s.get(fesaDim1, pContext), dim1);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("${regName}");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ pRegister->setVal${regType}Array(pDevice->${fesaFieldName}.get(fesaDim1, pContext), dim1);
+ }
"""
cSetArray2DReg = """
- pRegister = pPLCDevice->getRegister("%s");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pRegister->setVal%sArray2D(pDevice->%s.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("${regName}");
+ uint32_t dim1 = pRegister->getDimension1();
+ dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ pRegister->setVal${regType}Array2D(pDevice->${fesaFieldName}.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
"""
cSetUnsignedArrayReg = """
- pRegister = pPLCDevice->getRegister("%s");
- dim1 = pRegister->getDimension1();
- pRegister->setVal%sArray(pDevice->%s.get(fesaDim1, pContext), dim1);\t//use automatic conversion for JAVA non-supported type
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("${regName}");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ pRegister->setVal${regType}Array(pDevice->${fesaFieldName}.get(fesaDim1, pContext), dim1);\t//use automatic conversion for JAVA non-supported type
+ }
"""
cSetUnsignedArray2DReg = """
- pRegister = pPLCDevice->getRegister("%s");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pRegister->setVal%sArray2D( pDevice->%s.get(fesaDim1, fesaDim2, pContext), dim1, dim2);\t//use automatic conversion for JAVA non-supported type
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("${regName}");
+ uint32_t dim1 = pRegister->getDimension1();
+ dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ pRegister->setVal${regType}Array2D( pDevice->${fesaFieldName}.get(fesaDim1, fesaDim2, pContext), dim1, dim2);\t//use automatic conversion for JAVA non-supported type
+ }
"""
cSetStringRegData = """
- (data.is%sAvailable()) ? pPLCDevice->getRegister("%s")->setValString(data.%s.get()) :
- pPLCDevice->getRegister("%s")->setValString(pDevice->%s.get(pContext));"""
+ (data.is${fesaFieldName_upper}Available()) ? pPLCDevice->getRegister("${regName}")->setValString(data.${fesaFieldName}.get()) :
+ pPLCDevice->getRegister("${regName}")->setValString(pDevice->${fesaFieldName}.get(pContext));"""
cSetStringArrayRegData = """
{
- pRegister = pPLCDevice->getRegister("%s");
- dim1 = pRegister->getDimension1();
- std::string stdStringArray[dim1];
- const char** cStringArray = (data.is%sAvailable() ? data.%s.get(fesaDim1) : pDevice->%s.get(fesaDim1, pContext));
- for (unsigned int i=0; i<dim1; i++) stdStringArray[i] = (const char*)cStringArray[i];
- pRegister->setValStringArray(stdStringArray, dim1);
+ Silecs::Register* pRegister = pPLCDevice->getRegister("${regName}");
+ uint32_t dim1 = pRegister->getDimension1();
+ std::string stdStringArray[dim1];
+ uint32_t fesaDim1;
+ const char** cStringArray = (data.is${fesaFieldName_upper}Available() ? data.${fesaFieldName}.get(fesaDim1) : pDevice->${fesaFieldName}.get(fesaDim1, pContext));
+ for (unsigned int i=0; i<dim1; i++) stdStringArray[i] = (const char*)cStringArray[i];
+ pRegister->setValStringArray(stdStringArray, dim1);
}
"""
+
cSetScalarRegData = """
- (data.is%sAvailable()) ? pPLCDevice->getRegister("%s")->setVal%s( data.%s.get()) :
- pPLCDevice->getRegister("%s")->setVal%s( pDevice->%s.get(pContext));"""
+ (data.is${fesaFieldName_upper}Available()) ? pPLCDevice->getRegister("${regName}")->setVal${regType}( data.${fesaFieldName}.get()) :
+ pPLCDevice->getRegister("${regName}")->setVal${regType}( pDevice->${fesaFieldName}.get(pContext));"""
cSetScalarURegData = """
- (data.is%sAvailable()) ? pPLCDevice->getRegister("%s")->setVal%s( (%s)data.%s.get()) :
- pPLCDevice->getRegister("%s")->setVal%s( (%s)pDevice->%s.get(pContext));"""
-
+ (data.is${fesaFieldName_upper}Available()) ? pPLCDevice->getRegister("${regName}")->setVal${regType}( (${cType})data.${fesaFieldName}.get()) :
+ pPLCDevice->getRegister("${regName}")->setVal${regType}( (${cType})pDevice->${fesaFieldName}.get(pContext));"""
cSetArrayRegData = """
- pRegister = pPLCDevice->getRegister("%s");
- dim1 = pRegister->getDimension1();
- (data.is%sAvailable()) ? pRegister->setVal%sArray( data.%s.get(fesaDim1), dim1) :
- pRegister->setVal%sArray( pDevice->%s.get(fesaDim1, pContext), dim1);
- """
-
-cSetUnsignedArrayRegData = """
- pRegister = pPLCDevice->getRegister("%s");
- dim1 = pRegister->getDimension1();
- (data.is%sAvailable()) ? pRegister->setVal%sArray( data.%s.get(fesaDim1), dim1) :
- pRegister->setVal%sArray( pDevice->%s.get(fesaDim1, pContext), dim1);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("${regName}");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ (data.is${fesaFieldName_upper}Available()) ? pRegister->setVal${regType}Array( data.${fesaFieldName}.get(fesaDim1), dim1) :
+ pRegister->setVal${regType}Array( pDevice->${fesaFieldName}.get(fesaDim1, pContext), dim1);
+ }
"""
-
cSetArray2DRegData = """
- pRegister = pPLCDevice->getRegister("%s");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (data.is%sAvailable()) ? pRegister->setVal%sArray2D(data.%s.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setVal%sArray2D(pDevice->%s.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-"""
-
-cSetUnsignedArray2DRegData = """
- pRegister = pPLCDevice->getRegister("%s");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (data.is%sAvailable()) ? pRegister->setVal%sArray2D(data.%s.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setVal%sArray2D(pDevice->%s.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("${regName}");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ (data.is${fesaFieldName_upper}Available()) ? pRegister->setVal${regType}Array2D(data.${fesaFieldName}.get(fesaDim1, fesaDim2), dim1, dim2) :
+ pRegister->setVal${regType}Array2D(pDevice->${fesaFieldName}.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
"""
makeDesign = """# Include SILECS library path
-SILECS_PATH ?= %s
+SILECS_PATH ?= ${centralMakefilePath}
# Additional compiler warning flags
override WARNFLAGS +=
@@ -662,13 +667,11 @@ LINKER_FLAGS +=
# Additional headers (Custom.h Specific.h ...) which need to be installed
EXTRA_HEADERS +=
-
- """
-
+"""
makeDeploy = """# Include SILECS library path
-SILECS_PATH ?= %s
+SILECS_PATH ?= ${silecsBasePath}
-SNAP7_BASE = %s
+SNAP7_BASE = ${snap7BasePath}
# Additional compiler warning flags
override WARNFLAGS +=
@@ -691,9 +694,8 @@ LINKER_SERVER_FLAGS +=
# Additional headers (Custom.h Specific.h ...) which need to be released
EXTRA_HEADERS +=
-
- """
-
+"""
+
#=========================================================================
# FESA .cproject file
#=========================================================================
@@ -703,138 +705,134 @@ def genCProject():
#=========================================================================
# Header file (.h) code generation sub-functions
-#=========================================================================
+#================ =========================================================
+
def genHTop(className):
- return hTop %(className, className, className, className, className, className)
+ return htop.replace('${className}', className )
def genHTopBlock(className, blockName):
- return hTopBlock %(className, blockName)
+ return hTopBlock.replace('${className}', className).replace('${blockName}', blockName)
def genHTop2(className):
- return hTop2 %(className, className, className, className, className, className, className, className, className, className, className)
-
-def genHBlock(mode, blockName):
- return hBlock %(mode, blockName)
+ return hTop2.replace('${className}', className)
+
+def genHBlock(mode, blockName, propName):
+ return hBlock.replace('${mode}', mode).replace('${blockName}', blockName).replace('${propName}', propName)
def genHBottom(className):
- return hBottom %(className, className, className, className, className)
+ return hBottom.replace('${className}', className)
def genHDeclBlocks(className):
- return hDeclBlocks %(className, className)
+ return hDeclBlocks.replace('${className}', className)
def genHClosing(className):
- return hClosing %(className, className)
+ return hClosing.replace('${className}', className)
#=========================================================================
# C++ file (.cpp) code generation sub-functions
#=========================================================================
def genCTop(className):
- return cTop %(className, className, className, className, className, className, className)
+ return cTop.replace('${className}', className)
def genCGlobal(className, blockName):
- return cGlobal %(blockName, className, blockName, blockName)
+ return cGlobal.replace('${className}', className).replace('${blockName}', blockName)
def genCPart1(className):
- return cPart1 %(className, className, className, className)
+ return cPart1.replace('${className}', className)
def genCBlockConstr(blockName, className):
- return cBlockConstr %(blockName, blockName, className, blockName, blockName)
+ return cBlockConstr.replace('${className}', className).replace('${blockName}', blockName)
def genCPart2(className):
- return cPart2 %(className, className, className, className, className)
+ return cPart2.replace('${className}', className)
def genCSetPLC(className, blockName):
- return cSetPLC %(className, blockName)
+ return cSetPLC.replace('${className}', className).replace('${blockName}', blockName)
def genCCommonGet(blockName,className):
- return cCommonGet %(blockName,className)
+ return cCommonGet.replace('${className}', className).replace('${blockName}', blockName)
def genCPart3(className):
- return cPart3 %(className)
+ return cPart3.replace('${className}', className)
def genCGetPLC(className, blockName):
- return cGetPLC %(className, blockName)
+ return cGetPLC.replace('${className}', className).replace('${blockName}', blockName)
def genCPart4(className):
- return cPart4 %(className, className, className, className, className, className, className, className)
-
-def genCGetStringReg(regName):
- return cGetStringReg %(regName, regName)
+ return cPart4.replace('${className}', className)
-def genCGetStringArrayReg(regName):
- return cGetStringArrayReg %(regName, regName)
+def genCGetStringReg(register):
+ return cGetStringReg.replace('${regName}', register.name).replace('${fesaFieldName}', register.getFesaFieldName())
-def genCGetScalarReg(regName, regType):
- return cGetScalarReg %(regName, regName, regType)
+def genCGetStringArrayReg(register):
+ return cGetStringArrayReg.replace('${regName}', register.name).replace('${fesaFieldName}', register.getFesaFieldName())
-def genCGetArrayReg(regName, regType):
- return cGetArrayReg %(regName, regName, regType)
+def genCGetScalarReg(register):
+ return cGetScalarReg.replace('${regName}', register.name).replace('${regType}', register.getSilecsTypeCapitalized()).replace('${fesaFieldName}', register.getFesaFieldName())
-def genCGetArray2DReg(regName, regType):
- return cGetArray2DReg %(regName, regName, regType)
+def genCGetArrayReg(register):
+ if register.isUnsigned():
+ return cGetUnsignedArrayReg.replace('${regName}', register.name).replace('${regType}', register.getSilecsTypeCapitalized()).replace('${fesaFieldName}', register.getFesaFieldName()).replace('${fesaType}', register.getFesaType())
+ else:
+ return cGetArrayReg.replace('${regName}', register.name).replace('${regType}', register.getSilecsTypeCapitalized()).replace('${fesaFieldName}', register.getFesaFieldName())
-def genCGetUnsignedArrayReg(regName, fesaType, regType):
- return cGetUnsignedArrayReg %(regName, fesaType, regName, fesaType, fesaType, regType, regName, regName, regName, regName)
-
-def genCGetUnsignedArray2DReg(regName, fesaType, regType):
- return cGetUnsignedArray2DReg %(regName, fesaType, regName, fesaType, fesaType, regType, regName, regName, regName, regName)
+def genCGetArray2DReg(register):
+ if register.isUnsigned():
+ return cGetUnsignedArray2DReg.replace('${regName}', register.name).replace('${regType}', register.getSilecsTypeCapitalized()).replace('${fesaType}', register.getFesaType()).replace('${fesaFieldName}', register.getFesaFieldName())
+ else:
+ return cGetArray2DReg.replace('${regName}', register.name).replace('${regType}', register.getSilecsTypeCapitalized()).replace('${fesaFieldName}', register.getFesaFieldName())
def genCCommonSet(blockName,className):
- return cCommonSet %(blockName,className)
-
-def genCDatatypeSet(blockName,className):
- return cDatatypeSet %(blockName, blockName,className)
-
-def genCSetStringReg(regName):
- return cSetStringReg %(regName, regName)
-
-def genCSetStringArrayReg(regName):
- return cSetStringArrayReg %(regName, regName)
-
-def genCSetScalarReg(regName, regType):
- return cSetScalarReg %(regName, regType, regName)
-
-def genCSetScalarUReg(regName, regType, lowerType):
- return cSetScalarUReg %(regName, regType, lowerType, regName)
-
-def genCSetArrayReg(regName, regType):
- return cSetArrayReg %(regName, regType, regName)
-
-def genCSetUnsignedArrayReg(regName, regType):
- return cSetUnsignedArrayReg %(regName, regType, regName)
+ return cCommonSet.replace('${className}', className).replace('${blockName}', blockName)
-def genCSetArray2DReg(regName, regType):
- return cSetArray2DReg %(regName, regType, regName)
+def genCDatatypeSet(blockName,propName,className):
+ return cDatatypeSet.replace('${className}', className).replace('${blockName}', blockName).replace('${propName}', propName)
-def genCSetUnsignedArray2DReg(regName, regType):
- return cSetUnsignedArray2DReg %(regName, regType, regName)
+def genCSetStringReg(register):
+ return cSetStringReg.replace('${regName}', register.name).replace('${fesaFieldName}', register.getFesaFieldName())
-def genCSetStringRegData(regName):
- return cSetStringRegData %(iecommon.capitalizeString(regName), regName, regName, regName, regName)
+def genCSetStringArrayReg(register):
+ return cSetStringArrayReg.replace('${regName}', register.name).replace('${fesaFieldName}', register.getFesaFieldName())
-def genCSetStringArrayRegData(regName):
- return cSetStringArrayRegData %(regName, iecommon.capitalizeString(regName), regName, regName)
+def genCSetScalarReg(register):
+ if register.isUnsigned():
+ return cSetScalarUReg.replace('${regName}', register.name).replace('${regType}', register.getSilecsTypeCapitalized()).replace('${cType}', register.getCType()).replace('${fesaFieldName}', register.getFesaFieldName())
+ else:
+ return cSetScalarReg.replace('${regName}', register.name).replace('${regType}', register.getSilecsTypeCapitalized()).replace('${fesaFieldName}', register.getFesaFieldName())
+
-def genCSetScalarRegData(regName, regType):
- return cSetScalarRegData %(iecommon.capitalizeString(regName), regName, regType, regName, regName, regType, regName)
+def genCSetArrayReg(register):
+ if register.isUnsigned():
+ return cSetUnsignedArrayReg.replace('${regName}', register.name).replace('${regType}', register.getSilecsTypeCapitalized()).replace('${fesaFieldName}', register.getFesaFieldName())
+ else:
+ return cSetArrayReg.replace('${regName}', register.name).replace('${regType}', register.getSilecsTypeCapitalized()).replace('${fesaFieldName}', register.getFesaFieldName())
-def genCSetScalarURegData(regName, regType, lowerType):
- return cSetScalarURegData %(iecommon.capitalizeString(regName), regName, regType, lowerType, regName, regName, regType, lowerType, regName)
+def genCSetArray2DReg(register):
+ if register.isUnsigned():
+ return cSetUnsignedArray2DReg.replace('${regName}', register.name).replace('${regType}', register.getSilecsTypeCapitalized()).replace('${fesaFieldName}', register.getFesaFieldName())
+ else:
+ return cSetArray2DReg.replace('${regName}', register.name).replace('${regType}', register.getSilecsTypeCapitalized()).replace('${fesaFieldName}', register.getFesaFieldName())
+
+def genCSetStringRegData(register):
+ return cSetStringRegData.replace('${regName}', register.name).replace('${fesaFieldName_upper}', register.getFesaFieldNameCapitalized()).replace('${fesaFieldName}', register.getFesaFieldName())
-def genCSetUnsignedArrayRegData(regName, regType):
- return cSetUnsignedArrayRegData %(regName, iecommon.capitalizeString(regName), regType, regName, regType, regName)
+def genCSetStringArrayRegData(register):
+ return cSetStringArrayRegData.replace('${regName}', register.name).replace('${fesaFieldName_upper}', register.getFesaFieldNameCapitalized()).replace('${fesaFieldName}', register.getFesaFieldName())
-def genCSetUnsignedArray2DRegData(regName, fesaType, regType):
- return cSetUnsignedArray2DRegData %(regName, iecommon.capitalizeString(regName), regType, regName, regType, regName)
+def genCSetScalarRegData(register):
+ if register.isUnsigned():
+ return cSetScalarURegData.replace('${regName}', register.name).replace('${fesaFieldName_upper}', register.getFesaFieldNameCapitalized()).replace('${regType}', register.getSilecsTypeCapitalized()).replace('${fesaFieldName}', register.getFesaFieldName()).replace('${cType}', register.getCType())
+ else:
+ return cSetScalarRegData.replace('${regName}', register.name).replace('${fesaFieldName_upper}', register.getFesaFieldNameCapitalized()).replace('${regType}', register.getSilecsTypeCapitalized()).replace('${fesaFieldName}', register.getFesaFieldName())
-def genCSetArrayRegData(regName, regType):
- return cSetArrayRegData %(regName, iecommon.capitalizeString(regName), regType, regName, regType, regName)
+def genCSetArrayRegData(register):
+ return cSetArrayRegData.replace('${regName}', register.name).replace('${fesaFieldName_upper}', register.getFesaFieldNameCapitalized()).replace('${regType}', register.getSilecsTypeCapitalized()).replace('${fesaFieldName}', register.getFesaFieldName())
-def genCSetArray2DRegData(regName, fesaType, regType):
- return cSetArray2DRegData %(regName, iecommon.capitalizeString(regName), regType, regName, regType, regName)
+def genCSetArray2DRegData(register):
+ return cSetArray2DRegData.replace('${regName}', register.name).replace('${fesaFieldName_upper}', register.getFesaFieldNameCapitalized()).replace('${regType}', register.getSilecsTypeCapitalized()).replace('${fesaFieldName}', register.getFesaFieldName())
-def genMakeDesign(CentralMakefilePath):
- return makeDesign %(CentralMakefilePath)
+def genMakeDesign(centralMakefilePath):
+ return makeDesign.replace('${centralMakefilePath}', centralMakefilePath)
def genMakeDeploy(silecsBasePath,snap7BasePath):
- return makeDeploy %(silecsBasePath,snap7BasePath)
+ return makeDeploy.replace('${silecsBasePath}', silecsBasePath).replace('${snap7BasePath}', snap7BasePath)
diff --git a/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateFesaDesign.py b/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateFesaDesign.py
index 9aa76a346333523b0aa827eae5a55cf99268382c..4ff978c9d138f611acd25a1b17890c3a2d3e06c1 100644
--- a/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateFesaDesign.py
+++ b/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateFesaDesign.py
@@ -30,6 +30,9 @@ import fesaTemplates
import iefiles
from iecommon import *
+from model.Register import DesignRegister
+from model.Block import DesignBlock
+from model.Class import DesignClass
import libxml2
@@ -39,7 +42,7 @@ class FESADesignGenerator3_0_0(object):
#=========================================================================
# Sub-functions
#=========================================================================
-
+
def isGSITemplate(self,parent):
if isChildElement(parent,"GSI-Status-Property"):
return True
@@ -47,72 +50,59 @@ class FESADesignGenerator3_0_0(object):
return True
return False
-
- def getSilecsStringLength(self,register):
- strlen = '64'# check if custom length exists for string, otherwise use default length (64)
- if(register.hasProp('string-len')):
- strlen = str(register.prop('string-len'))
- return strlen
-
def getOrCreateStringArrayType(self,fieldNode,register):
array2DNode = getOrCreateChildElement(fieldNode,'array2D')
- fillAttributes(array2DNode, {'type': iecommon.getFesaDataType(register.prop('format'))})
+ fillAttributes(array2DNode, {'type': register.getFesaType()})
dim1Node = getOrCreateChildElement(array2DNode,'dim1')
dim2Node = getOrCreateChildElement(array2DNode,'dim2')
- dim1Node.setContent(register.prop('array-dim1')) # first dimension is the dimension of the array
- dim2Node.setContent(self.getSilecsStringLength(register)) # first dimension is the dimension of the array
+ dim1Node.setContent(str(register.dim1)) # first dimension is the dimension of the array
+ dim2Node.setContent(str(register.stringLength))
return array2DNode
def getOrCreateStringType(self,fieldNode,register):
stringNode = getOrCreateChildElement(fieldNode,'array')
- fillAttributes(stringNode, {'type': iecommon.getFesaDataType(register.prop('format'))})
+ fillAttributes(stringNode, {'type': register.getFesaType()})
dimNode = getOrCreateChildElement(stringNode,'dim')
- dimNode.setContent(self.getSilecsStringLength(register)) # first dimension is the dimension of the array
+ dimNode.setContent(str(register.stringLength)) # first dimension is the dimension of the array
return stringNode
def getOrCreate2DArrayType(self,fieldNode,register):
array2DNode = getOrCreateChildElement(fieldNode,'array2D')
- fillAttributes(array2DNode, {'type': iecommon.getFesaDataType(register.prop('format'))})
+ fillAttributes(array2DNode, {'type': register.getFesaType()})
dim1Node = getOrCreateChildElement(array2DNode,'dim1')
dim2Node = getOrCreateChildElement(array2DNode,'dim2')
- dim1Node.setContent(register.prop('array-dim1'))
- dim2Node.setContent(register.prop('array-dim2'))
+ dim1Node.setContent(str(register.dim1))
+ dim2Node.setContent(str(register.dim2))
return array2DNode
def getOrCreateArrayType(self,fieldNode,register):
arrayNode = getOrCreateChildElement(fieldNode,'array')
- fillAttributes(arrayNode, {'type': iecommon.getFesaDataType(register.prop('format'))})
+ fillAttributes(arrayNode, {'type': register.getFesaType()})
dimNode = getOrCreateChildElement(arrayNode,'dim')
- dimNode.setContent(register.prop('array-dim1'))
+ dimNode.setContent(str(register.dim1))
return arrayNode
- def getOrCreateScalarType(self,fieldNode,scalarType):
+ def getOrCreateScalarType(self,fieldNode,register):
scalarNode = getOrCreateChildElement(fieldNode,'scalar')
- fillAttributes(scalarNode, {'type': iecommon.getFesaDataType(scalarType)})
+ fillAttributes(scalarNode, {'type': register.getFesaType()})
return scalarNode
- def getOrCreateStringTypeBase(self,fieldNode,register):
- if(register.prop('array-dim2')) and int(register.prop('array-dim2')) > 1:
- iecommon.logError('ERROR: In register '+register.prop('name')+' - 2D array of strings not supported in FESA.', True, {'errorlog': True})
- return null
- elif (register.prop('array-dim1')) and int(register.prop('array-dim1')) > 1:
- return self.getOrCreateStringArrayType(fieldNode,register)
- else:
- return self.getOrCreateStringType(fieldNode,register)
-
- def getOrCreateBaseType(self,fieldNode,register):
- if (register.prop('array-dim2')) and int(register.prop('array-dim2')) > 1:
- return self.getOrCreate2DArrayType(fieldNode,register)
- elif (register.prop('array-dim1')) and int(register.prop('array-dim1')) > 1:
- return self.getOrCreateArrayType(fieldNode,register)
- else:
- return self.getOrCreateScalarType(fieldNode,register.prop('format'))
-
def getOrCreateType(self,fieldNode,register):
- if(register.prop('format') == 'string'):
- return self.getOrCreateStringTypeBase(fieldNode,register)
+ if register.valueType == "scalar":
+ return self.getOrCreateScalarType(fieldNode,register)
+ elif register.valueType == "array":
+ return self.getOrCreateArrayType(fieldNode,register)
+ elif register.valueType == "array2D":
+ return self.getOrCreate2DArrayType(fieldNode,register)
+ elif register.valueType == "string":
+ return self.getOrCreateStringType(fieldNode,register)
+ elif register.valueType == "stringArray":
+ return self.getOrCreateStringArrayType(fieldNode,register)
+ elif register.valueType == "stringArray2D":
+ iecommon.logError('ERROR: In register '+register.name+' - 2D array of strings not supported in FESA.', True, {'errorlog': True})
else:
- return self.getOrCreateBaseType(fieldNode,register)
+ iecommon.logError('ERROR: Unknown data-type:' + register.valueType, True, {'errorlog': True})
+ return None
def getOrCreateFieldRef(self,valueItemNode,FieldNameRef):
fieldRefNode = getOrCreateNamedChildElement(valueItemNode,'data-field-ref',FieldNameRef,'field-name-ref')
@@ -201,11 +191,11 @@ class FESADesignGenerator3_0_0(object):
fillAttributes(getActionNode, {'implementation': implementation})
def getOrCreateFieldNode(self,parent,register): #in order to place them before any GSI-specifc fields (order matters!)
- iecommon.logDebug('Generating Data-Field for register: ' + register.prop('name'), {'debuglog': True})
+ iecommon.logDebug('Generating Data-Field for register: ' + register.name, {'debuglog': True})
if( hasChildren(parent) ):
- return getOrCreateNamedPreviousSiblingElement(parent,getFirstChild(parent),'field',register.prop('name'))
+ return getOrCreateNamedPreviousSiblingElement(parent,getFirstChild(parent),'field',register.getFesaFieldName())
else:
- return getOrCreateNamedChildElement(parent,'field',register.prop('name'))
+ return getOrCreateNamedChildElement(parent,'field',register.getFesaFieldName())
def getOrCreatePLCHostNameField(self,configurationNode):
fieldNode = getOrCreateNamedFirstChild(configurationNode,'field','plcHostName')
@@ -252,98 +242,103 @@ class FESADesignGenerator3_0_0(object):
return fieldNode
def getOrCreateRegisterValueItems(self,prop,block,isSetting):
- for register in block.xpathEval('Register'):
- if register.prop('generateFesaValueItem') == 'true':
+ for register in block.getDesignRegisters():
+ if register.generateFesaValueItem:
self.getOrCreateValueItem(prop,register,isSetting)
- def getOrCreateSettingProperty(self,parent,block):
- iecommon.logDebug('Generating SettingProperty for Block: ' + block.prop('name'), {'debuglog': True})
+ def getOrCreateSettingProperty(self,parent,actionsNode,block):
+ iecommon.logDebug('Generating SettingProperty for Block: ' + block.name, {'debuglog': True})
if( hasChildren(parent)):
propsAfterCommand = parent.xpathEval("*[not(name()='command-property')]")
- prop = getOrCreateNamedPreviousSiblingElement(parent,propsAfterCommand[0], 'setting-property',block.prop('name'))
+ prop = getOrCreateNamedPreviousSiblingElement(parent,propsAfterCommand[0], 'setting-property',block.getFesaName())
else:
- prop = getOrCreateNamedChildElement(parent,'setting-property',block.prop('name'))
+ prop = getOrCreateNamedChildElement(parent,'setting-property',block.getFesaName())
+ fillAttributes(prop, {'visibility': 'development', 'multiplexed': 'false'})
self.getOrCreateRegisterValueItems(prop,block,True)
self.getOrCreateUpdateFlagItem(prop)
self.getOrCreateCyleNameItem(prop)
+ self.getOrCreateAction(prop,block.fesaSetServerActionName,'set',actionsNode,'custom')
+ self.getOrCreateAction(prop,block.fesaGetServerActionName,'get',actionsNode,'custom')
return prop
def getOrCreateAcquisitionProperty(self,parent,actionsNode,block):
- iecommon.logDebug('Generating AcquisitionProperty for Block: ' + block.prop('name'), {'debuglog': True})
+ iecommon.logDebug('Generating AcquisitionProperty for Block: ' + block.name, {'debuglog': True})
prop = ""
if( hasChildren(parent)):
- prop = getOrCreateNamedPreviousSiblingElement(parent,getFirstChild(parent), 'acquisition-property',block.prop('name'))
+ prop = getOrCreateNamedPreviousSiblingElement(parent,getFirstChild(parent), 'acquisition-property',block.getFesaName())
else:
- prop = getOrCreateNamedChildElement(parent,'acquisition-property',block.prop('name'))
+ prop = getOrCreateNamedChildElement(parent,'acquisition-property',block.getFesaName())
fillAttributes(prop, {'visibility': 'development', 'subscribable': 'true', 'multiplexed': 'false', 'on-change': 'true'})
self.getOrCreateRegisterValueItems(prop,block,False)
self.getOrCreateAcqStampItem(prop)
self.getOrCreateUpdateFlagItem(prop)
self.getOrCreateCyleNameItem(prop)
self.getOrCreateCyleStampItem(prop)
- self.getOrCreateAction(prop,'Get'+block.prop('name'),'get',actionsNode,'default')
+ self.getOrCreateAction(prop,block.fesaGetServerActionName,'get',actionsNode,'custom')
return prop
- def getOrCreateGSISettingProperty(self,parent,block):
- iecommon.logDebug('Generating GSISettingProperty for Block: ' + block.prop('name'), {'debuglog': True})
+ def getOrCreateGSISettingProperty(self,parent,actionsNode,block):
+ iecommon.logDebug('Generating GSISettingProperty for Block: ' + block.name, {'debuglog': True})
powerProp = parent.xpathEval('GSI-Power-Property')[0] # template is used --> there has to be a power prop
- prop = getOrCreateNamedPreviousSiblingElement(parent,powerProp, 'GSI-Setting-Property',block.prop('name'))
+ prop = getOrCreateNamedPreviousSiblingElement(parent,powerProp, 'GSI-Setting-Property',block.getFesaName())
+ fillAttributes(prop, {'visibility': 'development', 'multiplexed': 'false'})
self.getOrCreateRegisterValueItems(prop,block,True)
self.getOrCreateUpdateFlagItem(prop)
self.getOrCreateCyleNameItem(prop)
+ self.getOrCreateAction(prop,block.fesaSetServerActionName,'set',actionsNode,'custom')
+ self.getOrCreateAction(prop,block.fesaGetServerActionName,'get',actionsNode,'custom')
return prop
def getOrCreateGSIAcquisitionProperty(self,parent,actionsNode,block):
- iecommon.logDebug('Generating GSIAcquisitionProperty for Block: ' + block.prop('name'), {'debuglog': True})
+ iecommon.logDebug('Generating GSIAcquisitionProperty for Block: ' + block.name, {'debuglog': True})
versionProp = parent.xpathEval('GSI-Version-Property')[0] # template is used --> there has to be a version prop
- prop = getOrCreateNamedPreviousSiblingElement(parent,versionProp, 'GSI-Acquisition-Property',block.prop('name'))
+ prop = getOrCreateNamedPreviousSiblingElement(parent,versionProp, 'GSI-Acquisition-Property',block.getFesaName())
fillAttributes(prop, {'visibility': 'development', 'subscribable': 'true', 'multiplexed': 'false', 'on-change': 'true'})
self.getOrCreateRegisterValueItems(prop,block,False)
self.getOrCreateAcqStampItem(prop)
self.getOrCreateUpdateFlagItem(prop)
self.getOrCreateCyleNameItem(prop)
self.getOrCreateCyleStampItem(prop)
- self.getOrCreateAction(prop,'Get'+block.prop('name'),'get',actionsNode,'default')
+ self.getOrCreateAction(prop,block.fesaGetServerActionName,'get',actionsNode,'custom')
self.getOrCreateAcquisitionContextItem(prop)
return prop
# propertyType only used during creation ! If named property already exists, it is just returned, no matter which type
def getOrCreateFESAProperty(self,parent,actionsNode,block):
- properties = parent.xpathEval("*")
if self.isGSITemplate(parent):
if parent.get_name() == 'setting':
- return self.getOrCreateGSISettingProperty(parent,block)
+ return self.getOrCreateGSISettingProperty(parent,actionsNode,block)
else:
return self.getOrCreateGSIAcquisitionProperty(parent,actionsNode,block)
else:
if parent.get_name() == 'setting':
- return self.getOrCreateSettingProperty(parent,block)
+ return self.getOrCreateSettingProperty(parent,actionsNode,block)
else:
return self.getOrCreateAcquisitionProperty(parent,actionsNode,block)
def getOrCreateValueItem(self,propertyNode,register,isSetting):
- iecommon.logDebug('Generating ValueItem for Register: ' + register.prop('name'), {'debuglog': True})
- result = propertyNode.xpathEval("value-item[@name='" + register.prop('name') + "']")
+ iecommon.logDebug('Generating ValueItem for Register: ' + register.name, {'debuglog': True})
+ result = propertyNode.xpathEval("value-item[@name='" + register.getFesaFieldName() + "']")
if len(result):
return result[0]
if( hasChildren(propertyNode)):
result = propertyNode.xpathEval("*[not(name()='description') and not(name()='export') and not(name()='filter-item')]") # skip possible first elements to get right position
- valueItemNode = getOrCreateNamedPreviousSiblingElement(propertyNode,result[0],'value-item',register.prop('name'))
+ valueItemNode = getOrCreateNamedPreviousSiblingElement(propertyNode,result[0],'value-item',register.getFesaFieldName())
else:
- valueItemNode = getOrCreateNamedChildElement(propertyNode,'value-item',register.prop('name'))
+ valueItemNode = getOrCreateNamedChildElement(propertyNode,'value-item',register.getFesaFieldName())
if isSetting:
fillAttributes(valueItemNode, {'direction': 'INOUT'})
else:
fillAttributes(valueItemNode, {'direction': 'OUT'})
self.getOrCreateType(valueItemNode,register)
- self.getOrCreateFieldRef(valueItemNode,register.prop('name'))
+ self.getOrCreateFieldRef(valueItemNode,register.getFesaFieldName())
#-------------------------------------------------------------------------
# Generates the data node of the FESA design document
# parsing the SILECS class document
#-------------------------------------------------------------------------
- def genData(self,silecsRoot, doc,logTopics):
+ def genData(self,designClass, doc,logTopics):
iecommon.logDebug("Creating data fields", logTopics)
dataNode = doc.xpathEval('/equipment-model/data')[0]
@@ -354,44 +349,20 @@ class FESADesignGenerator3_0_0(object):
acquisitionNode = getOrCreateChildElement(deviceDataNode,'acquisition')
self.getOrCreatePLCHostNameField(configurationNode)
self.getOrCreatePLCDeviceLabelField(configurationNode)
- classNode = silecsRoot.xpathEval('//SILECS-Class')[0]
self.getOrCreateParameterFileField(configurationNode)
- # parse the SILECS design document to find the blocks
- for block in silecsRoot.xpathEval("//Block"): # loop over the blocks
- iecommon.logDebug('Analysing block '+block.prop('name'), logTopics)
- # Check that every register in the block has the same value for synchro
- regList = block.xpathEval("Register")
- for r in range (0, len(regList)-1):
- if regList[r].prop('synchro') != regList[r+1].prop('synchro'):
- # Return error and exit
- iecommon.logError('ERROR: In block '+block.prop('name')+' registers have different synchronisation values.', True, logTopics)
-
- if block.prop('mode') == 'READ-ONLY':
- for reg in regList:
- fieldNode = self.getOrCreateFieldNode(acquisitionNode,reg)
- if reg.prop('synchro') == 'MASTER': # the value of a master register never change, consistency is not required
- fillAttributes(fieldNode, {'multiplexed': 'false', 'persistent': 'false'})
- elif reg.prop('synchro') == 'NONE':
- fillAttributes(fieldNode, {'multiplexed': 'false', 'persistent': 'false'})
- self.getOrCreateType(fieldNode,reg)
-
- elif block.prop('mode') == 'WRITE-ONLY':
- for reg in regList:
+
+ for block in designClass.getDesignBlocks():
+ for reg in block.getDesignRegisters():
+ if reg.isSetting():
fieldNode = self.getOrCreateFieldNode(settingNode,reg)
- if reg.prop('synchro') == 'SLAVE':
- fillAttributes(fieldNode, {'multiplexed': 'false', 'persistent': 'true', 'shared': 'true'})
- elif reg.prop('synchro') == 'NONE':
- fillAttributes(fieldNode, {'multiplexed': 'false', 'persistent': 'false', 'shared': 'true'})
- self.getOrCreateType(fieldNode,reg)
-
- else: # READ-WRITE block
- for reg in regList:
+ fillAttributes(fieldNode, {'multiplexed': 'false', 'persistent': 'true'})
+ elif reg.isAcquisition():
+ fieldNode = self.getOrCreateFieldNode(acquisitionNode,reg)
+ fillAttributes(fieldNode, {'multiplexed': 'false', 'persistent': 'false'})
+ else: #volatile#
fieldNode = self.getOrCreateFieldNode(settingNode,reg)
- if reg.prop('synchro') == 'NONE':
- fillAttributes(fieldNode, {'multiplexed': 'false', 'persistent': 'false'})
- else: #synchro SLAVE and MASTER
- fillAttributes(fieldNode, {'multiplexed': 'false', 'persistent': 'true'})
- self.getOrCreateType(fieldNode,reg)
+ fillAttributes(fieldNode, {'multiplexed': 'false', 'persistent': 'false'})
+ self.getOrCreateType(fieldNode,reg)
globalDataNode = getOrCreateChildElement(dataNode,'global-data')
globalConfigurationNode = ""
@@ -402,13 +373,13 @@ class FESADesignGenerator3_0_0(object):
globalConfigurationNode = getOrCreatePreviousSiblingElement(getFirstChild(globalDataNode),'configuration')
else:
globalConfigurationNode = globalDataNode.xpathEval("configuration")[0]
- self.getOrCreatePLCClassVersionField(globalConfigurationNode,classNode.prop('version'))
+ self.getOrCreatePLCClassVersionField(globalConfigurationNode,designClass.version)
#-------------------------------------------------------------------------
# Generates the interface/device-interface node of the
# FESA design document parsing the SILECS class document
#-------------------------------------------------------------------------
- def genDeviceInterface(self,silecsRoot, doc,logTopics):
+ def genDeviceInterface(self,designClass, doc,logTopics):
# parse the FESA design document to find the device-interface node and create children
interfaceNode = doc.xpathEval('/equipment-model/interface')[0]
globalInterfaceNode = getOrCreateChildElement(interfaceNode,'global-interface')
@@ -416,55 +387,14 @@ class FESADesignGenerator3_0_0(object):
settingNode = getOrCreateChildElement(deviceInterfaceNode,'setting')
acquisitionNode = getOrCreateChildElement(deviceInterfaceNode,'acquisition')
actionsNode = doc.xpathEval('/equipment-model/actions')[0]
- for block in silecsRoot.xpathEval("//Block"):
-
- if block.prop('generateFesaProperty') == 'false':
+ for block in designClass.getDesignBlocks():
+ if not block.generateFesaProperty:
continue #skip this block
-
- if block.prop('mode') in ('READ-ONLY'):
- self.getOrCreateFESAProperty(acquisitionNode,actionsNode,block)
- rtAction = getOrCreateNamedChildElement(actionsNode,'rt-action','Recv'+block.prop('name'))
- notifiedProperty = getOrCreateNamedChildElement(rtAction,'notified-property',block.prop('name'),'property-name-ref')
- fillAttributes(notifiedProperty, {'automatic': 'true'})
- self.genEvent(block,doc,logTopics)
- self.genSchedulingUnit(block,doc,logTopics)
- else: # setting property for both WO and RW blocks, w/get+set server action
- settingPropertyNode = self.getOrCreateFESAProperty(settingNode, actionsNode, block)
- fillAttributes(settingPropertyNode, {'visibility': 'development', 'multiplexed': 'false'})
- self.getOrCreateAction(settingPropertyNode,'Send'+block.prop('name'),'set',actionsNode,'custom')
- if block.prop('mode') == 'READ-WRITE':
- self.getOrCreateAction(settingPropertyNode,'Recv'+block.prop('name'),'get',actionsNode,'custom')
- else: # WRITE-ONLY
- self.getOrCreateAction(settingPropertyNode,'Get'+block.prop('name'),'get',actionsNode,'default')
-
- #-------------------------------------------------------------------------
- # Generates the logical-events node of the FESA design
- # document parsing the SILECS class document
- #-------------------------------------------------------------------------
- def genEvent(self,block, fesaRoot,logTopics):
- iecommon.logDebug('Generating event', logTopics)
- eqpModelNode = fesaRoot.xpathEval("/equipment-model")[0]
- eventsNode = getOrCreateChildElement(eqpModelNode,'events')
- sourcesNode = getOrCreateChildElement(eventsNode,'sources')
- timingSourceNode = getOrCreateNamedChildElement(sourcesNode,'timing-event-source','Timing')
- timerSourceNode = getOrCreateNamedChildElement(sourcesNode,'timer-event-source','Timer')
- logicalEventsNode = getOrCreateChildElement(eventsNode,'logical-events')
- logicalEventNode = getOrCreateNamedChildElement(logicalEventsNode,'logical-event','Recv'+block.prop('name')+'Event')
- fillAttributes(logicalEventNode, {'type': 'timer', 'use': 'required'})
+ if block.isWritable():
+ propertyNode = self.getOrCreateFESAProperty(settingNode, actionsNode, block)
+ else:
+ propertyNode = self.getOrCreateFESAProperty(acquisitionNode,actionsNode,block)
- #-------------------------------------------------------------------------
- # Generates the scheduling-units node of the FESA design
- # document parsing the SILECS class document
- #-------------------------------------------------------------------------
- def genSchedulingUnit(self,block, fesaRoot,logTopics):
- iecommon.logDebug('Generating scheduling unit', logTopics)
- eqpModelNode = fesaRoot.xpathEval("/equipment-model")[0]
- schedulingUnitsNode = getOrCreateChildElement(eqpModelNode,'scheduling-units')
- schedulingUnitNode = getOrCreateNamedChildElement(schedulingUnitsNode,'scheduling-unit','Recv'+block.prop('name')+'Unit')
- rtActionRefNode = getOrCreateChildElement(schedulingUnitNode,'rt-action-ref')
- fillAttributes(rtActionRefNode, {'rt-action-name-ref': 'Recv'+block.prop('name')})
- logicalEventRefNode = getOrCreateChildElement(schedulingUnitNode,'logical-event-ref')
- fillAttributes(logicalEventRefNode, {'logical-event-name-ref': 'Recv'+block.prop('name')+'Event'})
#-------------------------------------------------------------------------
# Generates the scheduling-units node of the FESA design
@@ -504,12 +434,12 @@ class FESADesignGenerator3_0_0(object):
owner = silecsRoot.xpathEval('//Information/Owner')[0]
creatorNode.setProp('login', owner.prop('user-login')) # == Owner in SILECS design document
-
+ designClass = DesignClass.getDesignClassFromRootNode(silecsRoot)
# Generate data fields
- self.genData(silecsRoot, fesaRoot,logTopics)
+ self.genData(designClass, fesaRoot,logTopics)
# Generate properties, Actions, Events, Scheduling Units
- self.genDeviceInterface(silecsRoot, fesaRoot,logTopics)
+ self.genDeviceInterface(designClass, fesaRoot,logTopics)
self.addDesignFileId(fesaRoot,logTopics)
return fesaRoot
diff --git a/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateSourceCode.py b/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateSourceCode.py
index 2b520a933ce43726168a3e529d2713b38a7956be..75d9a874b61890d7c50160c6d1603f330ac5ed0c 100644
--- a/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateSourceCode.py
+++ b/silecs-codegen/src/xml/fesa/fesa_3_0_0/generateSourceCode.py
@@ -28,13 +28,16 @@ import fesaTemplates
import iefiles
from iecommon import *
+from model.Register import DesignRegister
+from model.Block import DesignBlock
+from model.Class import DesignClass
import libxml2
-def findBlockServerSetActionName(fesaRoot, blockName):
- properties = fesaRoot.xpathEval("/equipment-model/interface/device-interface/*/*[@name='" + blockName + "']")
+def findBlockServerSetActionName(fesaRoot, propName):
+ properties = fesaRoot.xpathEval("/equipment-model/interface/device-interface/*/*[@name='" + propName + "']")
for property in properties:
return property.xpathEval("set-action/server-action-ref")[0].prop("server-action-name-ref")
- raise Exception("Error: Server Action for Block '" + blockName + "' not found")
+ raise Exception("Error: Server Action for Property '" + propName + "' not found")
#-------------------------------------------------------------------------
# Generates the H source file containing general methods
@@ -42,27 +45,28 @@ def findBlockServerSetActionName(fesaRoot, blockName):
# of the FESA server
#-------------------------------------------------------------------------
def genHSource(className, silecsRoot, fesaRoot, sourcePath,logTopics):
+ designClass = DesignClass.getDesignClassFromRootNode(silecsRoot)
source = fesaTemplates.genHTop(className)
- for block in silecsRoot.xpathEval('//Block'):
- if block.prop('mode') == 'WRITE-ONLY' or block.prop('mode') == 'READ-WRITE':
- serverActionName = findBlockServerSetActionName(fesaRoot,block.prop('name'))
+ for block in designClass.getDesignBlocks():
+ if block.isWritable():
+ serverActionName = findBlockServerSetActionName(fesaRoot,block.getFesaName())
source += fesaTemplates.genHTopBlock(className, serverActionName)
source += fesaTemplates.genHTop2(className)
- for block in silecsRoot.xpathEval('//Block'):
- if block.prop('mode') == 'READ-ONLY':
- source += fesaTemplates.genHBlock('RO', block.prop('name'))
- elif block.prop('mode') == 'WRITE-ONLY':
- source += fesaTemplates.genHBlock('WO', block.prop('name'))
- else: # READ-WRITE
- source += fesaTemplates.genHBlock('RW', block.prop('name'))
+ for block in designClass.getDesignBlocks():
+ if block.isAcquisition():
+ source += fesaTemplates.genHBlock('RO', block.name,block.getFesaName() )
+ elif block.isCommand():
+ source += fesaTemplates.genHBlock('WO', block.name,block.getFesaName())
+ else: # Setting
+ source += fesaTemplates.genHBlock('RW', block.name,block.getFesaName())
source += fesaTemplates.genHBottom(className)
- for block in silecsRoot.xpathEval('//Block'):
- source += fesaTemplates.genHDeclBlocks(block.prop('name'))
+ for block in designClass.getDesignBlocks():
+ source += fesaTemplates.genHDeclBlocks(block.name)
source += fesaTemplates.genHClosing(className)
@@ -84,249 +88,91 @@ def genHSource(className, silecsRoot, fesaRoot, sourcePath,logTopics):
# Generates the C++ source file containing general
# methods to synchronise the FESA fields and related PLC
# registers of the FESA server
-#-------------------------------------------------------------------------
+#-------------------------------------------------------------------------
+
def genCppSource(className, silecsRoot, fesaRoot, sourcePath,logTopics):
+ designClass = DesignClass.getDesignClassFromRootNode(silecsRoot)
finalSource = fesaTemplates.genCTop(className)
- blockList = silecsRoot.xpathEval('//Block')
+ blockList = designClass.getDesignBlocks()
for block in blockList:
- finalSource += fesaTemplates.genCGlobal(className, block.prop('name'))
+ finalSource += fesaTemplates.genCGlobal(className, block.name)
finalSource += fesaTemplates.genCPart1(className)
for block in blockList:
- finalSource += fesaTemplates.genCBlockConstr(block.prop('name'), className)
+ finalSource += fesaTemplates.genCBlockConstr(block.name, className)
finalSource += fesaTemplates.genCPart2(className)
for block in blockList:
- regList = block.xpathEval('Register')
- if (block.prop('mode') == 'WRITE-ONLY' or block.prop('mode') == 'READ-WRITE') and regList[0].prop('synchro') == 'SLAVE':
- # just set the fields if block is WO or RW and register synchronisation is SLAVE
+ if (block.isWritable()):
# WARNING: In order to have multiplexed FESA fields, the corresponding SILECS registers' synchro mode must be 'NONE'
- finalSource += fesaTemplates.genCSetPLC(className, block.prop('name'))
+ finalSource += fesaTemplates.genCSetPLC(className, block.name)
finalSource += fesaTemplates.genCPart3(className)
for block in blockList:
- regList = block.xpathEval('Register')
- if (block.prop('mode') == 'READ-ONLY' or block.prop('mode') == 'READ-WRITE') and regList[0].prop('synchro') == 'MASTER':
- # just get the fields if block is RO or RW and register synchronisation is MASTER
+ if (block.isReadable()):
# WARNING: In order to have multiplexed FESA fields, the corresponding SILECS registers' synchro mode must be 'NONE'
- finalSource += fesaTemplates.genCGetPLC(className, block.prop('name'))
+ finalSource += fesaTemplates.genCGetPLC(className, block.name)
finalSource += fesaTemplates.genCPart4(className)
for block in blockList:
-
- source = '' #compute one source at a time
- flagReg = False
- flagDim1 = False
- flagDim2 = False
-
- if block.prop('mode') != 'WRITE-ONLY':
- finalSource += fesaTemplates.genCCommonGet(block.prop('name'),className)
-
- regList = block.xpathEval('Register')
- source += fesaTemplates.cRecv
-
- for reg in regList:
- type = reg.prop('format')
- if type == 'string': # string register
- flagReg = True
- if (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # string array
- flagDim1 = True
- source += fesaTemplates.genCGetStringArrayReg(reg.prop('name'))
- else: # simple string
- source += fesaTemplates.genCGetStringReg(reg.prop('name'))
-
- else: # not string register
- # uppercasing of type
- fesaType = iecommon.getFesaDataType(type)
- type = iecommon.getSilecsDataType(type)
- if type[0] == 'u':
- type = type[:2].upper() + type[2:] # first two characters if unsigned
-
- if reg.prop('array-dim2') and int(reg.prop('array-dim2')) > 1: # 2D array
- flagReg = True
- flagDim2 = True
- flagDim1 = True
- source += fesaTemplates.genCGetUnsignedArray2DReg(reg.prop('name'), fesaType, type)
- elif (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # array
- flagReg = True
- flagDim1 = True
- source += fesaTemplates.genCGetUnsignedArrayReg(reg.prop('name'), fesaType, type)
- else: # scalar
- source += fesaTemplates.genCGetScalarReg(reg.prop('name'), type)
-
- elif type[0] == 'd': # date type
- if reg.prop('array-dim2') and int(reg.prop('array-dim2')) > 1:
- flagReg = True
- flagDim2 = True
- flagDim1 = True
- source += fesaTemplates.genCGetArray2DReg(reg.prop('name'), 'Date')
- elif (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # array
- flagReg = True
- flagDim1 = True
- source += fesaTemplates.genCGetArrayReg(reg.prop('name'), 'Date')
- else: # scalar
- source += fesaTemplates.genCGetScalarReg(reg.prop('name'), 'Date')
-
- else:
- type = type[:1].upper() + type[1:] # only first character if not unsigned
- if reg.prop('array-dim2') and int(reg.prop('array-dim2')) > 1: # 2D array
- flagReg = True
- flagDim2 = True
- flagDim1 = True
- source += fesaTemplates.genCGetArray2DReg(reg.prop('name'), type)
- elif (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # array
- flagReg = True
- flagDim1 = True
- source += fesaTemplates.genCGetArrayReg(reg.prop('name'), type)
- else: # scalar
- source += fesaTemplates.genCGetScalarReg(reg.prop('name'), type)
-
- source += '\n\t}' # closing bracket for block
-
- #Add data declatation on top if needed and append the final source
- if flagReg == True:
- finalSource += fesaTemplates.cRegVar
- if flagDim1 == True:
- finalSource += fesaTemplates.cGetArrayVar
- if flagDim2 == True:
- finalSource += fesaTemplates.cGetArray2DVar
-
- finalSource += '\n' + source
-
- source = '' #compute one source at a time
- flagReg = False
- flagDim1 = False
- flagDim2 = False
-
- if block.prop('mode') != 'READ-ONLY':
- finalSource += fesaTemplates.genCCommonSet(block.prop('name'),className)
-
- regList = block.xpathEval('Register')
-
- for reg in regList:
- type = reg.prop('format')
- if type == 'string':
- flagReg = True
- if (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # string array
- flagDim1 = True
- source += fesaTemplates.genCSetStringArrayReg(reg.prop('name'))
- else: # simple string
- source += fesaTemplates.genCSetStringReg(reg.prop('name'))
-
- else: # not string register
- # uppercasing of type
- type = iecommon.getSilecsDataType(type)
- lowerType = type+'_t' # store lowercase type for unsigned registers (fesa type)
- if type[0] == 'u': # unsigned type
- type = type[:2].upper() + type[2:] # first two characters if unsigned
-
- if reg.prop('array-dim2') and int(reg.prop('array-dim2')) > 1: # 2D array
- flagReg = True
- flagDim2 = True
- flagDim1 = True
- source += fesaTemplates.genCSetUnsignedArray2DReg(reg.prop('name'), type)
- elif (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # array
- flagReg = True
- flagDim1 = True
- source += fesaTemplates.genCSetUnsignedArrayReg(reg.prop('name'), type)
- else: # scalar
- source += fesaTemplates.genCSetScalarUReg(reg.prop('name'), type, lowerType)
-
- else: # signed type
- type = type[:1].upper() + type[1:] # only first character if not unsigned
- if reg.prop('array-dim2') and int(reg.prop('array-dim2')) > 1: # 2D array
- flagReg = True
- flagDim2 = True
- flagDim1 = True
- source += fesaTemplates.genCSetArray2DReg(reg.prop('name'), type)
- elif (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # array
- flagReg = True
- flagDim1 = True
- source += fesaTemplates.genCSetArrayReg(reg.prop('name'), type)
- else: # scalar
- source += fesaTemplates.genCSetScalarReg(reg.prop('name'), type)
-
- source += fesaTemplates.cSend
- source += '\n\t}' # closing bracket for block
-
- #Add data declatation on top if needed and append the final source
- if flagReg == True:
- finalSource += fesaTemplates.cRegVar
- if flagDim1 == True:
- finalSource += fesaTemplates.cSetArrayVar
- if flagDim2 == True:
- finalSource += fesaTemplates.cSetArray2DVar
-
- finalSource += '\n' + source
-
- source = '' #compute one source at a time
- flagReg = False
- flagDim1 = False
- flagDim2 = False
-
- finalSource += fesaTemplates.genCDatatypeSet(block.prop('name'),className)
-
- regList = block.xpathEval('Register')
-
- for reg in regList:
- type = reg.prop('format')
- if type == 'string':
- flagReg = True
- if (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # string array
- flagDim1 = True
- source += fesaTemplates.genCSetStringArrayRegData(reg.prop('name'))
- else: # simple string
- source += fesaTemplates.genCSetStringRegData(reg.prop('name'))
-
- else: # not string register
- # uppercasing of type
- fesaType = iecommon.getFesaDataType(type)
- type = iecommon.getSilecsDataType(type)
- lowerType = type+'_t' # store lowercase type for unsigned registers (fesa type)
- if type[0] == 'u': # unsigned type
- type = type[:2].upper() + type[2:] # first two characters if unsigned
- if reg.prop('array-dim2') and int(reg.prop('array-dim2')) > 1: # 2D array
- flagReg = True
- flagDim2 = True
- flagDim1 = True
- source += fesaTemplates.genCSetUnsignedArray2DRegData(reg.prop('name'), fesaType, type)
- elif (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # array
- flagReg = True
- flagDim1 = True
- source += fesaTemplates.genCSetUnsignedArrayRegData(reg.prop('name'), type)
- else: # scalar
- source += fesaTemplates.genCSetScalarURegData(reg.prop('name'), type, lowerType)
-
- else: # signed type
- type = type[:1].upper() + type[1:] # only first character if not unsigned
- if reg.prop('array-dim2') and int(reg.prop('array-dim2')) > 1: # 2D array
- flagReg = True
- flagDim2 = True
- flagDim1 = True
- source += fesaTemplates.genCSetArray2DRegData(reg.prop('name'), fesaType, type)
- elif (reg.prop('array-dim1')) and int(reg.prop('array-dim1')) > 1: # array
- flagReg = True
- flagDim1 = True
- source += fesaTemplates.genCSetArrayRegData(reg.prop('name'), type)
- else: # scalar
- source += fesaTemplates.genCSetScalarRegData(reg.prop('name'), type)
-
- source += fesaTemplates.cSend
- source += '\n\t}' # closing bracket for block
-
- #Add data declatation on top if needed and append the final source
- if flagReg == True:
- finalSource += fesaTemplates.cRegVar
- if flagDim1 == True:
- finalSource += fesaTemplates.cSetArrayVar
- if flagDim2 == True:
- finalSource += fesaTemplates.cSetArray2DVar
+ if block.isReadable():
+ finalSource += fesaTemplates.genCCommonGet(block.name,className)
+ finalSource += '\n'
+ finalSource += fesaTemplates.cRecv
+ for register in block.getDesignRegisters():
+ if register.valueType == 'string':
+ finalSource += fesaTemplates.genCGetStringReg(register)
+ elif register.valueType == 'stringArray':
+ finalSource += fesaTemplates.genCGetStringArrayReg(register)
+ elif register.valueType == 'stringArray2D':
+ iecommon.logError('ERROR: In register '+register.name+' - 2D array of strings not supported in FESA.', True, {'errorlog': True})
+ elif register.valueType == 'scalar':
+ finalSource += fesaTemplates.genCGetScalarReg(register)
+ elif register.valueType == 'array':
+ finalSource += fesaTemplates.genCGetArrayReg(register)
+ elif register.valueType == 'array2D':
+ finalSource += fesaTemplates.genCGetArray2DReg(register)
+ finalSource += '\n }\n'
+
+ if block.isWritable():
+ finalSource += fesaTemplates.genCCommonSet(block.name,className)
+ for register in block.getDesignRegisters():
+ if register.valueType == 'string':
+ finalSource += fesaTemplates.genCSetStringReg(register)
+ elif register.valueType == 'stringArray':
+ finalSource += fesaTemplates.genCSetStringArrayReg(register)
+ elif register.valueType == 'stringArray2D':
+ iecommon.logError('ERROR: In register '+register.name+' - 2D array of strings not supported in FESA.', True, {'errorlog': True})
+ elif register.valueType == 'scalar':
+ finalSource += fesaTemplates.genCSetScalarReg(register)
+ elif register.valueType == 'array':
+ finalSource += fesaTemplates.genCSetArrayReg(register)
+ elif register.valueType == 'array2D':
+ finalSource += fesaTemplates.genCSetArray2DReg(register)
+ finalSource += fesaTemplates.cSend
+ finalSource += ' }\n'
+ finalSource += fesaTemplates.genCDatatypeSet(block.name,block.getFesaName(), className)
- finalSource += '\n' + source
+ for register in block.getDesignRegisters():
+ if register.valueType == 'string':
+ finalSource += fesaTemplates.genCSetStringRegData(register)
+ elif register.valueType == 'stringArray':
+ finalSource += fesaTemplates.genCSetStringArrayRegData(register)
+ elif register.valueType == 'stringArray2D':
+ iecommon.logError('ERROR: In register '+register.name+' - 2D array of strings not supported in FESA.', True, {'errorlog': True})
+ elif register.valueType == 'array2D':
+ finalSource += fesaTemplates.genCSetArray2DRegData(register)
+ elif register.valueType == 'array':
+ finalSource += fesaTemplates.genCSetArrayRegData(register)
+ elif register.valueType == 'scalar':
+ finalSource += fesaTemplates.genCSetScalarRegData(register)
+
+ finalSource += fesaTemplates.cSend
+ finalSource += '\n }\n' # closing bracket for block
finalSource += '\n}\n' # closing bracket for class
diff --git a/silecs-codegen/src/xml/genduwrapper.py b/silecs-codegen/src/xml/genduwrapper.py
index c42a32a7e054fd75903f80c4a7985849831f80e7..dc8036b1ab3c6e3576cc1161d219eee4e365666c 100644
--- a/silecs-codegen/src/xml/genduwrapper.py
+++ b/silecs-codegen/src/xml/genduwrapper.py
@@ -24,73 +24,36 @@ import iefiles
import genduwrappertemplate
from iecommon import *
-
-#=========================================================================
-# Sub-functions
-#=========================================================================
-
-def extractBlockList(designDOM):
- blockList = []
- for blockNode in designDOM.xpathEval("//Block"):
- blockList.append([blockNode.prop("name"), blockNode.prop("mode")])
- return blockList
-
-def getRegisterList(designFile,blockName):
- '''Return the list of register included in a given block.
- for each register a the following tuple is returned: [name,format,dim1,dim2]
- '''
- registerList = []
- dom = libxml2.parseFile(designFile)
- blockNodeList = dom.xpathEval("//Block")
- for blockNode in blockNodeList:
- if blockNode.prop("name")==blockName:
- break #after the loop blockNode will point to the good node
-
- registerNodeList=blockNode.xpathEval("Register")
- for registerNode in registerNodeList:
- name = registerNode.prop("name")
- format = registerNode.prop("format")
- dim1 = 1
- dim2 = 1
- try:
- dim1 = int(registerNode.prop("array-dim1"))
- except:
- pass #use 1 as default dimention
- try:
- dim2 = int(registerNode.prop("array-dim2"))
- except:
- pass #use 1 as default dimention
- registerList.append([name,format,dim1,dim2])
- return registerList
+from model.Register import DesignRegister
+from model.Block import DesignBlock
+from model.Class import DesignClass
def genClassHeader(workspacePath, deployName, classNode, funcGetSilecsDesignFilePath, funcGetDuDesignWrapperFile, logTopics):
designName = classNode.prop("silecs-design-name")
designVersion = classNode.prop("silecs-design-version")
designFile = funcGetSilecsDesignFilePath(workspacePath, designName)
designDOM = libxml2.parseFile(designFile)
+ designClass = DesignClass.getDesignClassFromRootNode(designDOM)
if(not os.path.isfile(designFile)):
raise Exception("File not found: " + designFile)
- blockList = extractBlockList(designDOM)
- classDeclarations = ""
+ classDeclarations = ""
#construct Block class
- for [blockName,blockMode] in blockList:
- registerList = getRegisterList(designFile,blockName)
- registerInitializerList = genduwrappertemplate.getBlockInitializerList(registerList)
- registerGetterSetter = genduwrappertemplate.getRegisterGetterSetter(blockName,blockMode,registerList)
- registersDimentionsDeclaration = genduwrappertemplate.getRegistersDimetionsDeclaration(registerList)
- registersDeclaration = genduwrappertemplate.getRegistersDeclaration(registerList)
- classDeclarations += genduwrappertemplate.getBlockClass(blockName,registerInitializerList,registerGetterSetter,registersDimentionsDeclaration,registersDeclaration)
+ for block in designClass.getDesignBlocks():
+ registerInitializerList = genduwrappertemplate.getBlockInitializerList(block)
+ registerGetterSetter = genduwrappertemplate.getRegisterGetterSetter(block)
+ registersDimentionsDeclaration = genduwrappertemplate.getRegistersDimetionsDeclaration(block)
+ registersDeclaration = genduwrappertemplate.getRegistersDeclaration(block)
+ classDeclarations += genduwrappertemplate.getBlockClass(block,registerInitializerList,registerGetterSetter,registersDimentionsDeclaration,registersDeclaration)
blockGetters = ""
- sendRecvBlocks = genduwrappertemplate.getDeviceSendRecvBlocks(blockList)
- for [blockName,mode] in blockList:
- registerList = getRegisterList(designFile,blockName)
- blockGetters += genduwrappertemplate.getDeviceBlockGetterSetter(blockName, mode, registerList)
+ sendRecvBlocks = genduwrappertemplate.getDeviceSendRecvBlocks(designClass.getBlockNodes())
+ for block in designClass.getDesignBlocks():
+ blockGetters += genduwrappertemplate.getDeviceBlockGetterSetter(block)
classDeclarations += genduwrappertemplate.getDeviceClass(blockGetters,sendRecvBlocks)
- sendRecvBlocks = genduwrappertemplate.getControllerSendRecvBlocks(blockList)
+ sendRecvBlocks = genduwrappertemplate.getControllerSendRecvBlocks(designClass.getBlockNodes())
classDeclarations = genduwrappertemplate.getDesignClass(designName, designVersion)
designWrapper = genduwrappertemplate.designFileTemplate.substitute({'designNameCapitalized' : iecommon.capitalizeString(designName),'designNameUpper' : designName.upper(),'classDeclarations' : classDeclarations})
@@ -102,7 +65,6 @@ def genClassHeader(workspacePath, deployName, classNode, funcGetSilecsDesignFile
def genDuWrapperBase(deployFile,funcGetDuWrapperFile,workspacePath,funcGetSilecsDesignFilePath, funcGetDuDesignWrapperFile,deployName,deployVersion,logTopics={'errorlog': True}):
deployDOM = libxml2.parseFile(deployFile)
-
for controllerNode in deployDOM.xpathEval("/SILECS-Deploy/Controller"):
controllerName = controllerNode.prop("host-name")
controllerDomain = "" # GSI-Hack - No Support for domains at GSI
diff --git a/silecs-codegen/src/xml/genduwrappertemplate.py b/silecs-codegen/src/xml/genduwrappertemplate.py
index 8f5814902a33717a3e4fa572ce11afe9c13bfb57..af7cf950d9fd644e022ae3bef26d7ca69f0bbc44 100644
--- a/silecs-codegen/src/xml/genduwrappertemplate.py
+++ b/silecs-codegen/src/xml/genduwrappertemplate.py
@@ -16,6 +16,8 @@
import string
import iecommon
+from model.Register import DesignRegister
+from model.Block import DesignBlock
#=================================================================
# Deploy Unit Class
@@ -233,12 +235,13 @@ designSendTemplate = string.Template("""\
def getDesignSendRecvBlocks(blockList):
text = ""
- for [blockName,mode] in blockList:
- map = {'blockName' : blockName,
- 'blockNameCapitalized' : iecommon.capitalizeString(blockName)}
- if mode == 'READ-ONLY' or mode == 'READ-WRITE':
+ for blockNode in blockList:
+ block = DesignBlock(blockNode)
+ map = {'blockName' : block.name,
+ 'blockNameCapitalized' : block.getNameCapitalized()}
+ if block.isReadable():
text += designReceiveTemplate.substitute(map)
- if mode == 'WRITE-ONLY' or mode == 'READ-WRITE':
+ if block.isWritable():
text += designSendTemplate.substitute(map)
return text
@@ -336,12 +339,13 @@ controllerSendTemplate = string.Template("""\
def getControllerSendRecvBlocks(blockList):
text = ""
- for [blockName,mode] in blockList:
- map = {'blockName' : blockName,
- 'blockNameCapitalized' : iecommon.capitalizeString(blockName)}
- if mode == 'READ-ONLY' or mode == 'READ-WRITE':
+ for blockNode in blockList:
+ block = DesignBlock(blockNode)
+ map = {'blockName' : block.name,
+ 'blockNameCapitalized' : block.getNameCapitalized()}
+ if block.isReadable():
text += controllerReceiveTemplate.substitute(map)
- if mode == 'WRITE-ONLY' or mode == 'READ-WRITE':
+ if block.isWritable():
text += controllerSendTemplate.substitute(map)
return text
@@ -436,61 +440,43 @@ scalarRegisterAssignementSetter = string.Template("""\
getSilecsDevice()->getRegister("${regName}")->setVal${silecsTypeCapitalized}(block.get${regNameCapitalized}());
""")
-def getDeviceBlockGetterSetter(blockName, blockMode, registerList):
+def getDeviceBlockGetterSetter(block):
text = ""
- if blockMode == 'READ-ONLY' or blockMode == 'READ-WRITE':
+ if block.isReadable():
blockInitialization = ""
- for [name,format,dim1,dim2] in registerList:
- silecsType = iecommon.getSilecsDataType(format)
- if silecsType[0] == 'u':
- silecsTypeCapitalized = silecsType[:2].upper() + silecsType[2:]
- else:
- silecsTypeCapitalized = iecommon.capitalizeString(silecsType)
-
- map = {'regName' : name,
- 'regNameCapitalized' : iecommon.capitalizeString(name),
- 'silecsTypeCapitalized' : silecsTypeCapitalized,
- 'cType' : iecommon.getCDataType(format)}
- if dim2 > 1:
- #matrix
+ for register in block.getDesignRegisters():
+ map = {'regName' : register.name,
+ 'regNameCapitalized' : register.getNameCapitalized(),
+ 'silecsTypeCapitalized' : register.getSilecsTypeCapitalized(),
+ 'cType' : register.getCType()}
+ if register.isArray2D():
blockInitialization += matrixRegisterAssignementGetter.substitute(map)
- elif dim1 > 1:
- #array
+ elif register.isArray():
blockInitialization += arrayRegisterAssignementGetter.substitute(map)
- else:
- #scalar
+ else: #scalar
blockInitialization += scalarRegisterAssignementGetter.substitute(map)
- blockMap = {'blockName' : blockName,
+ blockMap = {'blockName' : block.name,
'blockInitialization' : blockInitialization,
- 'blockNameCapitalized' : iecommon.capitalizeString(blockName)}
+ 'blockNameCapitalized' : block.getNameCapitalized()}
text += blockGetterTemplate.substitute(blockMap)
- if blockMode == 'WRITE-ONLY' or blockMode == 'READ-WRITE':
+ if block.isWritable():
blockInitialization = ""
- for [name,format,dim1,dim2] in registerList:
- silecsType = iecommon.getSilecsDataType(format)
- if silecsType[0] == 'u':
- silecsTypeCapitalized = silecsType[:2].upper() + silecsType[2:]
- else:
- silecsTypeCapitalized = iecommon.capitalizeString(silecsType)
-
- map = {'regName' : name,
- 'regNameCapitalized' : iecommon.capitalizeString(name),
- 'silecsTypeCapitalized' : silecsTypeCapitalized,
- 'cType' : iecommon.getCDataType(format)}
- if dim2 > 1:
- #matrix
+ for register in block.getDesignRegisters():
+ map = {'regName' : register.name,
+ 'regNameCapitalized' : register.getNameCapitalized(),
+ 'silecsTypeCapitalized' : register.getSilecsTypeCapitalized(),
+ 'cType' : register.getCType()}
+ if register.isArray2D():
blockInitialization += matrixRegisterAssignementSetter.substitute(map)
- elif dim1 > 1:
- #array
+ elif register.isArray():
blockInitialization += arrayRegisterAssignementSetter.substitute(map)
- else:
- #scalar
+ else: #scalar
blockInitialization += scalarRegisterAssignementSetter.substitute(map)
- blockMap = {'blockName' : blockName,
+ blockMap = {'blockName' : block.name,
'blockInitialization' : blockInitialization,
- 'blockNameCapitalized' : iecommon.capitalizeString(blockName)}
+ 'blockNameCapitalized' : block.getNameCapitalized()}
text += blockSetterTemplate.substitute(blockMap)
return text
@@ -518,12 +504,13 @@ deviceSendTemplate = string.Template("""\
def getDeviceSendRecvBlocks(blockList):
text = ""
- for [blockName,mode] in blockList:
- map = {'blockName' : blockName,
- 'blockNameCapitalized' : iecommon.capitalizeString(blockName)}
- if mode == 'READ-ONLY' or mode == 'READ-WRITE':
+ for blockNode in blockList:
+ block = DesignBlock(blockNode)
+ map = {'blockName' : block.name,
+ 'blockNameCapitalized' : block.getNameCapitalized()}
+ if block.isReadable():
text += deviceReceiveTemplate.substitute(map)
- if mode == 'WRITE-ONLY' or mode == 'READ-WRITE':
+ if block.isWritable():
text += deviceSendTemplate.substitute(map)
return text
@@ -553,10 +540,10 @@ ${registersDeclaration}
};
""")
-def getBlockClass(blockName,registerInitializerList,registerGetterSetter,registersDimentionsDeclaration,registersDeclaration):
- map = {'blockName' : blockName,
+def getBlockClass(block,registerInitializerList,registerGetterSetter,registersDimentionsDeclaration,registersDeclaration):
+ map = {'blockName' : block.name,
'registerInitializerList' : registerInitializerList,
- 'blockNameCapitalized' : iecommon.capitalizeString(blockName),
+ 'blockNameCapitalized' : block.getNameCapitalized(),
'registerGetterSetter' : registerGetterSetter,
'registersDimentionsDeclaration' : registersDimentionsDeclaration,
'registersDeclaration' : registersDeclaration}
@@ -566,11 +553,11 @@ registerInitializerListTemplate = string.Template("""\
,
${registerName}(0)""")
-def getBlockInitializerList(regList):
+def getBlockInitializerList(block):
text = ""
- for [name,format,dim1,dim2] in regList:
- if format != 'string' and dim1 == 1 and dim2 == 1:
- text += registerInitializerListTemplate.substitute({'registerName' : name})
+ for register in block.getDesignRegisters():
+ if register.isScalar():
+ text += registerInitializerListTemplate.substitute({'registerName' : register.name})
return text
@@ -668,26 +655,25 @@ scalarRegisterSetterTemplate = string.Template("""
}
""")
-def getRegisterGetterSetter(blockName,blockMode,regList):
+def getRegisterGetterSetter(block):
text = ""
- for [name,format,dim1,dim2] in regList:
- cType = iecommon.getCDataType(format)
- map = {'registerName' : name,
- 'registerNameCapitalized' : iecommon.capitalizeString(name),
- 'cType' : iecommon.getCDataType(format)}
+ for register in block.getDesignRegisters():
+ map = {'registerName' : register.name,
+ 'registerNameCapitalized' : register.getNameCapitalized(),
+ 'cType' : register.getCType()}
- if dim2 > 1:
+ if register.isArray2D():
text += matrixRegisterGetterTemplate.substitute(map)
text += matrixRegisterSetterTemplate.substitute(map)
- elif dim1 > 1:
- if format == 'string':
+ elif register.isArray():
+ if register.isStringType():
text += stringArrayRegisterGetterTemplate.substitute(map)
text += stringArrayRegisterSetterTemplate.substitute(map)
else:
text += arrayRegisterGetterTemplate.substitute(map)
text += arrayRegisterSetterTemplate.substitute(map)
else:
- if format == 'string':
+ if register.isStringType():
map['cType'] = "const std::string&"
text += scalarRegisterGetterTemplate.substitute(map)
text += scalarRegisterSetterTemplate.substitute(map)
@@ -697,20 +683,20 @@ registersDimetionsDeclarationTemplate = string.Template("""\
static const std::size_t ${registerName}Dim${index} = ${dimention};
""")
-def getRegistersDimetionsDeclaration(regList):
+def getRegistersDimetionsDeclaration(block):
text = ""
- for [name,format,dim1,dim2] in regList:
- map = {'registerName' : name}
- if dim2 > 1:
+ for register in block.getDesignRegisters():
+ map = {'registerName' : register.name}
+ if register.isArray2D():
map['index'] = "2"
- map['dimention'] = dim2
+ map['dimention'] = register.dim2
text += registersDimetionsDeclarationTemplate.substitute(map)
map['index'] = "1"
- map['dimention'] = dim1
+ map['dimention'] = register.dim1
text += registersDimetionsDeclarationTemplate.substitute(map)
- elif dim1 > 1:
+ elif register.isArray():
map['index'] = "1"
- map['dimention'] = dim1
+ map['dimention'] = register.dim1
text += registersDimetionsDeclarationTemplate.substitute(map)
return text
@@ -726,14 +712,14 @@ scalarRegistersDeclarationTemplate = string.Template("""\
${cType} ${registerName};
""")
-def getRegistersDeclaration(regList):
+def getRegistersDeclaration(block):
text = ""
- for [name,format,dim1,dim2] in regList:
- map = {'registerName' : name,
- 'cType' : iecommon.getCDataType(format)}
- if dim2 > 1:
+ for register in block.getDesignRegisters():
+ map = {'registerName' : register.name,
+ 'cType' : register.getCType()}
+ if register.isArray2D():
text += matrixRegistersDeclarationTemplate.substitute(map)
- elif dim1 > 1:
+ elif register.isArray():
text += arrayRegistersDeclarationTemplate.substitute(map)
else:
text += scalarRegistersDeclarationTemplate.substitute(map)
diff --git a/silecs-codegen/src/xml/genparam.py b/silecs-codegen/src/xml/genparam.py
index c7cf9068e1618159430d6b95e47bf2a3a260a0b6..4dfecb5eb7f15da12e8d2fe1b79b8c0568ce5b87 100644
--- a/silecs-codegen/src/xml/genparam.py
+++ b/silecs-codegen/src/xml/genparam.py
@@ -28,6 +28,9 @@ import xmltemplate
import iefiles
from iecommon import *
+from model.Register import *
+from model.Block import *
+from model.Class import *
#-------------------------------------------------------------------------
# Global definitions
@@ -39,7 +42,7 @@ deviceMemSize = 0 # global memory-size of one class instance (sum of b
nbBlock = 0 # number of block of the class
plcSize = 0
plcLast = 0
-classMem = 0
+classMem = ""
instAddr = 0
blockCounter = 0 # used for NI block address generation
@@ -481,38 +484,15 @@ def computeChecksumController( workspacePath, controllerNode, silecsVersion, PLC
return CRC32
def computeChecksumClass(designDOM, CRC32, logTopics={'errorlog': True}):
- blockList = designDOM.xpathEval("Block")
- for blockNode in blockList:
- blockName = blockNode.prop('name')
- blockMode = blockNode.prop('mode')
- registerList = blockNode.xpathEval("Register")
- for register in registerList:
- regName = register.prop("name")
- CRC32 = zlib.crc32(trim(regName),CRC32)& 0xffffffff
-
- regFormat = register.prop("format")
- CRC32 = zlib.crc32(trim(regFormat),CRC32)& 0xffffffff
-
- try:
- # array-dim1 is an optional attribute!!!
- regDim1 = register.prop("array-dim1")
- except:
- regDim1 = "1"
- CRC32 = zlib.crc32(trim(regDim1),CRC32)& 0xffffffff
-
- try:
- # array-dim2 is an optional attribute!!!
- regDim2 = register.prop("array-dim2")
- except:
- regDim2 = "1"
- CRC32 = zlib.crc32(trim(regDim2),CRC32)& 0xffffffff
-
- try:
- # string-len is an optional attribute!!!
- stringLength = register.prop("string-len")
- CRC32 = zlib.crc32(trim(stringLength),CRC32)& 0xffffffff
- except:
- pass
+ designClass = DesignClass.getDesignClassFromRootNode(designDOM)
+ for block in designClass.getDesignBlocks():
+ CRC32 = zlib.crc32(trim(block.name),CRC32)& 0xffffffff
+ for register in block.getDesignRegisters():
+ CRC32 = zlib.crc32(trim(register.name),CRC32)& 0xffffffff
+ CRC32 = zlib.crc32(trim(register.format),CRC32)& 0xffffffff
+ CRC32 = zlib.crc32(trim(str(register.dim1)),CRC32)& 0xffffffff
+ CRC32 = zlib.crc32(trim(str(register.dim2)),CRC32)& 0xffffffff
+ CRC32 = zlib.crc32(trim(str(register.stringLength)),CRC32)& 0xffffffff
return CRC32
#-------------------------------------------------------------------------
@@ -673,7 +653,7 @@ def loadSilecsDesignDOM(workspacePath, classNode, silecsVersion, funcGetSilecsDe
return libxml2.parseFile(designPath)
# Needed to encapsulate "genParam" in order to allow unit-testing (fake all file interactions)
-def genParamBase( funcGetSilecsDesignFilePath, funcGetParameterFile, funcGetSilecsDeployFilePath, funcGetParameterFileDirectory, workspacePath, deployName, deployVersion, silecsVersion, logTopics={'errorlog': True}):
+def genParamBase( funcGetSilecsDesignFilePath, funcGetParameterFile, funcGetSilecsDeployFilePath, funcGetParameterFileDirectory, workspacePath, deployName, deployVersion, silecsVersion, logTopics={'debuglog': True}):
# Global variable links
global plcModel, plcBrand, plcSystem, plcProtocol, plcSize, plcLast
global PLCbaseAddress, checksumRef, owner, deviceMemSize, blkAddr, nbBlock, msize
@@ -810,23 +790,23 @@ def genParamBase( funcGetSilecsDesignFilePath, funcGetParameterFile, funcGetSile
outputRoot.addChild(paramSilecsMappingNode)
classNodes = controllerNode.xpathEval('SilecsDesign')
+
for classNode in classNodes:
iecommon.logDebug("-----------------------------------------",logTopics)
iecommon.logDebug("------ Analysing Class %s ------"%classNode.prop("silecs-design-name"),logTopics)
iecommon.logDebug("-----------------------------------------",logTopics)
designDOM = loadSilecsDesignDOM(workspacePath, classNode, silecsVersion, funcGetSilecsDesignFilePath)
-
+ designClass = DesignClass.getDesignClassFromRootNode(designDOM)
+ paramClass = ParamClass()
+ paramClass.initWithDesignClass(designClass)
+ paramSilecsMappingNode.addChild(paramClass.xmlNode)
+
# Extract the number of devices ------------------------------------------
-
deviceLabelList=classNode.xpathEval('Device')
nbDevice = len(deviceLabelList)
iecommon.logDebug("Class %s uses device-list and has %s devices" %(classNode,nbDevice),logTopics)
-
- paramClassNode = libxml2.newNode("SILECS-Class")
- paramSilecsMappingNode.addChild(paramClassNode)
- paramClassNode.setProp("name", classNode.prop("silecs-design-name"))
- paramClassNode.setProp("version", classNode.prop("silecs-design-version"))
+
#-------------------------------------------------------------------------
# Generate section <Block></Block>
@@ -840,11 +820,11 @@ def genParamBase( funcGetSilecsDesignFilePath, funcGetParameterFile, funcGetSile
computeBlkAddress = whichBlkAddressFunction[plcBrand + plcProtocol]
# INNER LOOP TO ACCESS AT BLOCK LEVEL (LOOP-2)
- for block in designDOM.xpathEval("//Block"): #LOOP-2
- element3 = libxml2.newNode("Block")
- element3.setProp("name", block.prop("name"))
- element3.setProp("mode", block.prop("mode"))
- iecommon.logDebug("----- Processing Block "+block.prop('name')+" from design -----",logTopics)
+ for designBlock in designClass.getDesignBlocks(): #LOOP-2
+ paramBlock = ParamBlock()
+ paramBlock.initWithDesignBlock(designBlock)
+
+ iecommon.logDebug("----- Processing Block "+ designBlock.name + " from design -----",logTopics)
# Initialization for inner loop local variables
regAddress = 0 # memory address of the register (using byte addressing)
blockSize = 0 # block size (sum of the register size)
@@ -857,68 +837,38 @@ def genParamBase( funcGetSilecsDesignFilePath, funcGetParameterFile, funcGetSile
# Generate section <Register></Register>
#-------------------------------------------------------------------------
# INNER LOOP TO ACCESS AT REGISTER LEVEL (LOOP-3)
- for register in block.xpathEval("Register"):
- iecommon.logDebug("------ Processing Register "+register.prop('name')+" ------")
- element4 = libxml2.newNode("Register")
- # Set register name
- element4.setProp("name", register.prop("name"))
- # Set register format
- regFormat = register.prop("format")
- element4.setProp("format", regFormat)
-
- # Just get the register dimensions for next computation
- regDimension1 = '1' #by default
- if register.prop('array-dim1'): #possibly single array
- regDimension1 = register.prop("array-dim1")
- regDimension2 = '1' #by default
- if register.prop('array-dim2'): #possibly double array
- regDimension2 = register.prop('array-dim2')
-
+ for designRegister in designBlock.getDesignRegisters():
+ iecommon.logDebug("------ Processing Register " + designRegister.name + " ------",logTopics)
# Set length attribute only for string registers
- strLen = '1' #not a string by default (no impact on data total-size)
- if regFormat == 'string':
- strLen = register.prop('string-len')
- if strLen: #is string length defined?
- if plcBrand == 'RABBIT':
- # RABBIT has 8bit memory alignment but uses 16bit word communication protocol (MODBUS).
- # String buffer (8bit elements) must have even number of bytes.
- if ((int(regDimension1)*int(regDimension2)*int(strLen)) % 2 == 1): #XML CliX cannot check that constraint!
- iecommon.logError("String length of %s register must be an even value." %register.prop("name"), False,logTopics)
- sys.exit(2)
- else: # if length not given, set default length for string (=64)
- strLen = '64'
- element4.setProp('string-len', strLen)
+ if designRegister.format == 'string':
+ if plcBrand == 'RABBIT':
+ # RABBIT has 8bit memory alignment but uses 16bit word communication protocol (MODBUS).
+ # String buffer (8bit elements) must have even number of bytes.
+ if ((int(designRegister.dim1)*int(designRegister.dim2)*int(designRegister.stringLength)) % 2 == 1): #XML CliX cannot check that constraint!
+ iecommon.logError("String length of %s designRegister must be an even value." %designRegister.name, False,logTopics)
+ sys.exit(2)
- # Set register dimensions
- element4.setProp("array-dim1", regDimension1)
- element4.setProp("array-dim2", regDimension2)
# Set register size
- regSize = whichDataSize[regFormat]
- element4.setProp("size", regSize)
+ regSize = whichDataSize[designRegister.format]
# Set register address
- regAddress = alignRegAddress(regAddress, regFormat, regSize, regDimension1, regDimension2, strLen)
- element4.setProp("address", str(regAddress))
+ regAddress = alignRegAddress(regAddress, designRegister.format, regSize, designRegister.dim1, designRegister.dim2, designRegister.stringLength)
regCounter = regCounter + 1 # used for NI register address generation
# Set register mem-size
- element4.setProp("mem-size", str(msize))
+ paramRegister = ParamRegister()
+ paramRegister.initWithDesignRegister(designRegister,regSize,regAddress,msize)
# Compute address for the next register
- regAddress = computeAnyNextRegAddress(plcBrand, regAddress, regDimension1, regDimension2)
- # Set register synchro
- element4.setProp("synchro", register.prop("synchro"))
- # Append register
- element3.addChild(element4)
+ regAddress = computeAnyNextRegAddress(plcBrand, regAddress, designRegister.dim1, designRegister.dim2)
+ paramBlock.xmlNode.addChild(paramRegister.xmlNode)
+ #paramRegister.xmlNode.shellPrintNode()
#iterativelly compute the block size (accumulator initialized outside the loop)
- blockSize = blockSize + (int(regSize) * int(regDimension1) * int(regDimension2))
+ blockSize = blockSize + (int(regSize) * designRegister.dim1 * designRegister.dim2)
# END OF INNER LOOP TO ACCESS AT REGISTER LEVEL (LOOP-3)
- # Set block size
- element3.setProp("size", str(blockSize))
- # Set block address
- element3.setProp("address",str(computeBlkAddress(regAddress, int(classBaseAddress) , nbDevice)))
- # Set block mem-size
- element3.setProp("mem-size", str(blkMemSize))
+ paramBlock.setSize(blockSize)
+ paramBlock.setAddress(computeBlkAddress(regAddress, int(classBaseAddress),nbDevice))
+ paramBlock.setMemSize(blkMemSize)
# Append block
- paramClassNode.addChild(element3)
+ paramClass.xmlNode.addChild(paramBlock.xmlNode)
# Count the number of devices
nbBlock = nbBlock+1
# Accumulate blkMemSize to compute the total deviceMemSize
@@ -926,25 +876,21 @@ def genParamBase( funcGetSilecsDesignFilePath, funcGetParameterFile, funcGetSile
# END OF INNER LOOP TO ACCESS AT BLOCK LEVEL (LOOP-2)
# Set block Address
- paramClassNode.setProp("address", str(classBaseAddress))
+ paramClass.setAddress(classBaseAddress)
- #-------------------------------------------------------------------------
- # Devices
- #-------------------------------------------------------------------------
computeInstAddress = whichInstAddressFunction[ plcBrand + plcProtocol ]
-
for device in deviceLabelList:
- element3 = libxml2.newNode("Instance")
- element3.setProp("label", device.prop("device-name"))
- element3.setProp("address", str(computeInstAddress(classBaseAddress, deviceMemSize)))
- paramClassNode.addChild(element3)
+ instance = libxml2.newNode("Instance")
+ instance.setProp("label", device.prop("device-name"))
+ instance.setProp("address", str(computeInstAddress(classBaseAddress, deviceMemSize)))
+ paramClass.xmlNode.addChild(instance)
# Compute the memory address for the next class
computeBaseAddress = whichBaseAddressFunction [plcBrand+plcProtocol]
classBaseAddress = computeBaseAddress(classBaseAddress, nbBlock, nbDevice, deviceMemSize);
# Set class used-memory
- paramClassNode.setProp("used-mem", str(classMem))
+ paramClass.setUsedMemory(classMem)
iecommon.logInfo("Used-memory for Class "+classNode.prop("silecs-design-version")+": "+str(classMem),logTopics)
#------------------------------------------------------
diff --git a/silecs-codegen/src/xml/genplcsrc.py b/silecs-codegen/src/xml/genplcsrc.py
index 0c86eb8b64391200656d6840bb741500721dc050..005156fb7a8237b33720e9117d8095e02f285427 100644
--- a/silecs-codegen/src/xml/genplcsrc.py
+++ b/silecs-codegen/src/xml/genplcsrc.py
@@ -28,6 +28,10 @@ import virtualS7Template
import rabbitTemplate
from iecommon import *
+from model.Register import ParamRegister
+from model.Block import ParamBlock
+from model.Class import ParamClass
+
#=========================================================================
# General remarks
#=========================================================================
@@ -111,27 +115,27 @@ beckhoffRegInit = """ %s_%04x_%s AT %%MW%s: %s:= %s;\r\n\r\n"""
# Schneider registers
#-------------------------------------------------------------------------
-def xsyRegister(regFormat, regDim, regDim2, regLen=1):
- if regLen > 1: # register is a string or an array of strings
- strLen= whichUnityFormat[regFormat]+'['+str(regLen)+']'
- if regDim == 1 and regDim2 ==1: # string
+def xsyRegister(register):
+ if register.isStringType():
+ strLen = whichUnityFormat[register.format]+'['+str(register.stringLength)+']'
+ if register.isString():
return strLen
- elif regDim > 1 and regDim2 == 1: # string array
- return schneiderRegArray %(regDim-1, strLen)
- else: # dim1>=1 and for whatever dim2, use double array syntax
- return schneiderRegArray2d %(regDim-1, regDim2-1, strLen)
+ elif register.isStringArray():
+ return schneiderRegArray %(register.dim1-1, strLen)
+ else: #2D-Array
+ return schneiderRegArray2d %(register.dim1-1, register.dim2-1, strLen)
else:
- if regDim == 1 and regDim2 ==1: # scalar
- return whichUnityFormat[regFormat]
- elif regDim > 1 and regDim2 == 1: # array
- return schneiderRegArray %(regDim-1, whichUnityFormat[regFormat])
- else: # dim1>=1 and for whatever dim2, use double array syntax
- return schneiderRegArray2d %(regDim-1, regDim2-1, whichUnityFormat[regFormat])
+ if register.isScalar():
+ return whichUnityFormat[register.format]
+ elif register.isArray():
+ return schneiderRegArray %(register.dim1-1, whichUnityFormat[register.format])
+ else: #2D-Array
+ return schneiderRegArray2d %(register.dim1-1, register.dim2-1, whichUnityFormat[register.format])
def getDateTime():
dt = time.localtime(time.time())
return "DT#%s-%s-%s-%s:%s:%s" %(dt[0],dt[1],dt[2],dt[3],dt[4],dt[5])
-
+
#-------------------------------------------------------------------------
# SIEMENS PLC code generation
#-------------------------------------------------------------------------
@@ -146,71 +150,53 @@ def generateSiemensSources(paramDOM, sourceFolderPath ,logTopics):
UDTnumber = long(deploy.address) #use base data-block address for UDT number as well (to be reserved by the developer)
# Generate sources for each class that is deployed in the PLC
- classNodes = paramDOM.xpathEval("/SILECS-Param/SILECS-Mapping/SILECS-Class")
- for classNode in classNodes:
- blockDOMList = classNode.xpathEval("Block") # get Blocks elements of that class
- deviceDOMList = classNode.xpathEval("Instance") # get Device instances of that class
-
- className = classNode.prop('name')
- classVersion = classNode.prop('version')
-
+ for paramClass in ParamClass.getParamClassesFromRootNode(paramDOM):
+ deviceDOMList = paramClass.getDeviceInstanceNodes() # get Device instances of that class
deviceNumber = len(deviceDOMList)
# Generate the Blocks definition
- for blockIndex, blockDOM in enumerate(blockDOMList):
+ for blockIndex, block in enumerate(paramClass.getParamBlocks()):
registerList = ''
- blockName = blockDOM.prop('name')
- registerDOMList = blockDOM.xpathEval("Register") # get registers of the current block
- for registerIndex, registerDOM in enumerate(registerDOMList):
- registerName = registerDOM.prop('name')
- registerFormat = registerDOM.prop('format')
-
+ for register in block.getParamRegisters():
# If PLC does not supports this register format abort this generation and log the error
- if(registerFormat in ['uint64','int64','float64']):
+ if(register.format in ['uint64','int64','float64']):
iecommon.logError('ERROR: In design %s_%s register %s, %s format not supported for current controller model.'
- %(className, classVersion, registerName, registerFormat)
+ %(paramClass.name, paramClass.version, register.name, register.format)
, True,logTopics)
#create register value if required (diagnostic registers assignment in particular)
- registerValue = s7template.stlRegisterValue(registerName, deploy.owner, getDateTime(), deploy.checksum,deploy.silecsVersion)
+ registerValue = s7template.stlRegisterValue(register.name, deploy.owner, getDateTime(), deploy.checksum,deploy.silecsVersion)
- # Read register dimensions
- registerDimension1 = long(registerDOM.prop('array-dim1'))
- registerDimension2 = long(registerDOM.prop('array-dim2'))
-
- if registerFormat == 'string':
- registerList += s7template.stlRegister(registerName, registerFormat, registerDimension1, registerDimension2, registerValue, long(registerDOM.prop('string-len')))
+ if register.format == 'string':
+ registerList += s7template.stlRegister(register.name, register.format, register.dim1, register.dim2, registerValue, long(register.stringLength))
else:
- registerList += s7template.stlRegister(registerName, registerFormat, registerDimension1, registerDimension2, registerValue)
+ registerList += s7template.stlRegister(register.name, register.format, register.dim1, register.dim2, registerValue)
- stlString += s7template.stlBlockUDT(deploy.owner, className, classVersion, blockName, registerList, (blockIndex == 0))
- symString += s7template.symBlockUDT(className, classVersion, blockName, UDTnumber, (blockIndex == 0))
+ stlString += s7template.stlBlockUDT(deploy.owner, paramClass.name, paramClass.version, block.name, registerList, (blockIndex == 0))
+ symString += s7template.symBlockUDT(paramClass.name, paramClass.version, block.name, UDTnumber, (blockIndex == 0))
UDTnumber += 1
if deploy.plcProtocol == 'DEVICE_MODE':
# Generate the Data-Blocks: one DB per Device instance
for deviceIndex, deviceDOM in enumerate(deviceDOMList):
blockList = ''
- for blockDOM in blockDOMList:
- blockName = blockDOM.prop('name')
- blockList += s7template.stlBlock(className, blockName)
+ for block in paramClass.getParamBlocks():
+ blockList += s7template.stlBlock(paramClass.name, block.name)
deviceLabel = deviceDOM.prop('label')
- stlString += s7template.generateBlock(deploy.owner, className, classVersion, deploy.plcSystem, DBnumber, deviceLabel, blockList, (deviceIndex == 0),deploy.plcProtocol)
- symString += s7template.symDeviceDB(className, classVersion, deviceLabel, DBnumber, (deviceIndex == 0))
+ stlString += s7template.generateBlock(deploy.owner, paramClass.name, paramClass.version, deploy.plcSystem, DBnumber, deviceLabel, blockList, (deviceIndex == 0),deploy.plcProtocol)
+ symString += s7template.symDeviceDB(paramClass.name, paramClass.version, deviceLabel, DBnumber, (deviceIndex == 0))
DBnumber += 1
else: # BLOCK_MODE
# Generate the Data-Blocks: one DB per Block of registers
- for blockIndex, blockDOM in enumerate(blockDOMList):
- blockName = blockDOM.prop('name')
-
+ for blockIndex, block in enumerate(paramClass.getParamBlocks()):
deviceList = ''
for deviceDOM in deviceDOMList:
deviceLabel = deviceDOM.prop('label')
- deviceList += s7template.stlDevice(deviceLabel, className, blockName)
+ deviceList += s7template.stlDevice(deviceLabel, paramClass.name, block.name)
- stlString += s7template.generateBlock(deploy.owner, className, classVersion, deploy.plcSystem, DBnumber, blockName, deviceList, (blockIndex == 0),deploy.plcProtocol)
- symString += s7template.symBlockDB(className, classVersion, blockName, DBnumber, (blockIndex == 0))
+ stlString += s7template.generateBlock(deploy.owner, paramClass.name, paramClass.version, deploy.plcSystem, DBnumber, block.name, deviceList, (blockIndex == 0),deploy.plcProtocol)
+ symString += s7template.symBlockDB(paramClass.name, paramClass.version, block.name, DBnumber, (blockIndex == 0))
DBnumber += 1
# write the String PLC generated code
@@ -224,65 +210,53 @@ def generateSiemensSources(paramDOM, sourceFolderPath ,logTopics):
#-------------------------------------------------------------------------
# ----------------------------------------------------
-def generateSchneiderRegisters(xsydoc, classDOM, deviceDOM, blockDOM, deviceIndex, modeDevice, deploy, logTopics):
+def generateSchneiderRegisters(xsydoc, paramClass, deviceDOM, block, deviceIndex, modeDevice, deploy, logTopics):
- className = classDOM.prop('name')
deviceLabel = deviceDOM.prop('label')
- blockName = blockDOM.prop('name')
#Device and Block adresses come from the generated Paramerers file. Depends on the protocol mode:
#DEVICE_MODE: relative address of the element within it parent node
#BLOCK_MODE : absolute address in the entire PLC memory
deviceAddress = long(deviceDOM.prop('address'))
- blockAddress = long(blockDOM.prop('address'))
- blockMemSize = long(blockDOM.prop('mem-size'))
- registerDOMList = blockDOM.xpathEval("Register") # get Registers of the current block
- for registerIndex,registerDOM in enumerate(registerDOMList):
- registerName = registerDOM.prop('name')
- registerFormat = registerDOM.prop('format')
- registerDimension1 = long(registerDOM.prop('array-dim1'))
- registerDimension2 = long(registerDOM.prop('array-dim2'))
+ for register in block.getParamRegisters():
# If PLC does not supports this register format abort this generation and log the error
- if(registerFormat in ['uint64','int64','float64']):
- iecommon.logError('ERROR: In register '+registerName+', '+registerFormat+' format not supported for current controller model.', True,logTopics)
-
- #register has relative address irrespective of the protocol mode.
- registerOffset = long(registerDOM.prop('address'))
+ if(register.format in ['uint64','int64','float64']):
+ iecommon.logError('ERROR: In register '+register.name+', '+register.format+' format not supported for current controller model.', True,logTopics)
# Compute the Register address relying on the Class Parameters file data
# Attention! Schneider uses WORD addressing while Parameters data are expressed in bytes to be PLC independent
if modeDevice:
- registerAddress = (deviceAddress + blockAddress + registerOffset)/2
+ totalAddress = (deviceAddress + block.address + register.address)/2
else:
- registerAddress = (blockAddress + (deviceIndex * blockMemSize) + registerOffset)/2
+ totalAddress = (block.address + (deviceIndex * block.memSize) + register.address)/2
# then insert the corresponding DOM element
dataElt = xsydoc.xpathEval("//dataBlock")[0] #only one dataBlock node has been inserted so far
regElt = libxml2.newNode('variables')
# Compute the base checksum of the class name
- classNameCRC = zlib.crc32(className,0) & 0xffff
+ classNameCRC = zlib.crc32(paramClass.name,0) & 0xffff
# Create register name = regname_crc32(classname)_deviceid
# 24 char (register name) + 1 (underscore) + 4 char (CRC classname) + 1 (underscore) + n (device id) = 30 + n (device id)
# possible problem when device id (n)> 99 --> string > 32 not compatible with Schneider PLCs
- regElt.setProp("name", "%s_%04x_%s" %(registerName, classNameCRC, deviceLabel))
+ regElt.setProp("name", "%s_%04x_%s" %(register.name, classNameCRC, deviceLabel))
- if registerFormat == 'string':
- regElt.setProp("typeName", "%s" %xsyRegister(registerFormat, registerDimension1, registerDimension2, registerDOM.prop('string-len')))
+ if register.format == 'string':
+ regElt.setProp("typeName", "%s" %xsyRegister(register))
else:
- regElt.setProp("typeName", "%s" %xsyRegister(registerFormat, registerDimension1, registerDimension2))
+ regElt.setProp("typeName", "%s" %xsyRegister(register))
- regElt.setProp("topologicalAddress", "%%MW%ld" %registerAddress)
- if blockName == 'hdrBlk':
+ regElt.setProp("topologicalAddress", "%%MW%ld" %totalAddress)
+ if block.name == 'hdrBlk':
initElt = libxml2.newNode('variableInit')
- if registerName == '_version': initElt.setProp("value", deploy.silecsVersion )
- if registerName == '_user' : initElt.setProp("value", deploy.owner)
- if registerName == '_checksum': initElt.setProp("value", "%s" %deploy.checksum)
- if registerName == '_date' : initElt.setProp("value", getDateTime())
+ if register.name == '_version': initElt.setProp("value", deploy.silecsVersion )
+ if register.name == '_user' : initElt.setProp("value", deploy.owner)
+ if register.name == '_checksum': initElt.setProp("value", "%s" %deploy.checksum)
+ if register.name == '_date' : initElt.setProp("value", getDateTime())
regElt.addChild(initElt)
commElt = libxml2.newNode('comment')
- commElt.setContent(className+"/"+deviceLabel+"/"+blockName)
+ commElt.setContent(paramClass.name+"/"+deviceLabel+"/"+block.name)
regElt.addChild(commElt)
dataElt.addChild(regElt)
@@ -300,19 +274,16 @@ def generateSchneiderSources(paramDOM,sourceFolderPath,logTopics):
xsyDoc.addChild(rootElt)
dataElt = libxml2.newNode('dataBlock')
rootElt.addChild(dataElt)
-
- classNodes = paramDOM.xpathEval("/SILECS-Param/SILECS-Mapping/SILECS-Class")
- for classNode in classNodes:
- address = int(classNode.prop('address')) #address of the first register of the configuration
- blockDOMList = classNode.xpathEval("Block") # get Blocks elements of that class
- deviceDOMList = classNode.xpathEval("Instance") # get Device instances of that class
+
+ for paramClass in ParamClass.getParamClassesFromRootNode(paramDOM):
+ deviceDOMList = paramClass.getDeviceInstanceNodes() # get Device instances of that class
- for blockDOM in blockDOMList:
+ for block in paramClass.getParamBlocks():
for deviceIndex,deviceDOM in enumerate(deviceDOMList):
if deploy.plcProtocol == 'DEVICE_MODE': #-------------------
- generateSchneiderRegisters(xsyDoc, classNode, deviceDOM, blockDOM, deviceIndex, True, deploy, logTopics)
+ generateSchneiderRegisters(xsyDoc, paramClass, deviceDOM, block, deviceIndex, True, deploy, logTopics)
else:
- generateSchneiderRegisters(xsyDoc, classNode, deviceDOM, blockDOM, deviceIndex, False, deploy, logTopics)
+ generateSchneiderRegisters(xsyDoc, paramClass, deviceDOM, block, deviceIndex, False, deploy, logTopics)
# Finally, write the DOM object (PLC generated code) into the XSY source file
generateControllerFiles(sourceFolderPath,deploy,".xsy",rootElt.serialize(format = True),logTopics);
@@ -334,49 +305,35 @@ def generateRabbitSources(paramDOM,sourceFolderPath,logTopics):
classList = ''
NBdeviceDefinitionList = ''
- classNodes = paramDOM.xpathEval("/SILECS-Param/SILECS-Mapping/SILECS-Class")
- for classNode in classNodes:
- blockDOMList = classNode.xpathEval("Block") # get Blocks elements of that class
- deviceDOMList = classNode.xpathEval("Instance") # get Device instances of that class
-
- className = classNode.prop('name')
- classVersion = classNode.prop('version')
-
+ for paramClass in ParamClass.getParamClassesFromRootNode(paramDOM):
+ deviceDOMList = paramClass.getDeviceInstanceNodes() # get Device instances of that class
deviceNumber = len(deviceDOMList)
#==== Generate the Blocks definition ====
- for blockIndex, blockDOM in enumerate(blockDOMList):
+ for blockIndex, block in enumerate(paramClass.getParamBlocks()):
registerList = ''
- blockName = blockDOM.prop('name')
- registerDOMList = blockDOM.xpathEval("Register") # get Registers of the current block
- for registerIndex, registerDOM in enumerate(registerDOMList):
- registerName = registerDOM.prop('name')
- registerFormat = registerDOM.prop('format')
- registerDimension1 = long(registerDOM.prop('array-dim1'))
- registerDimension2 = long(registerDOM.prop('array-dim2'))
-
+ for register in block.getParamRegisters():
# If PLC does not supports this register format abort this generation and log the error
- if(registerFormat in ['float64']):
- iecommon.logError('ERROR: In register '+registerName+', '+registerFormat+' format not supported for current controller model.', True,logTopics)
+ if(register.format in ['float64']):
+ iecommon.logError('ERROR: In register '+ register.name +', '+register.format+' format not supported for current controller model.', True,logTopics)
- if(registerFormat == 'string'):
- registerList += rabbitTemplate.cRegister(registerName, registerFormat, registerDimension1, registerDimension2, long(registerDOM.prop('string-len')))
+ if(register.format == 'string'):
+ registerList += rabbitTemplate.cRegister(register.name, register.format, register.dim1, register.dim2, long(register.stringLength))
else:
- registerList += rabbitTemplate.cRegister(registerName, registerFormat, registerDimension1, registerDimension2)
+ registerList += rabbitTemplate.cRegister(register.name, register.format, register.dim1, register.dim2)
- cTypeDefinitions += rabbitTemplate.cBlockUDT(className, classVersion, blockName, registerList, (blockIndex == 0))
+ cTypeDefinitions += rabbitTemplate.cBlockUDT(paramClass.name, paramClass.version, block.name, registerList, (blockIndex == 0))
#==== Memory allocation ====
if deploy.plcProtocol == 'DEVICE_MODE':
# Generate the List of block in the class
blockList =''
- for blockIndex, blockDOM in enumerate(blockDOMList):
- blockName = blockDOM.prop('name')
- blockList += rabbitTemplate.cDeviceModeBlockInstantiation(className, blockName)
+ for block in paramClass.getParamBlocks():
+ blockList += rabbitTemplate.cDeviceModeBlockInstantiation(paramClass.name, block.name)
deviceList = ''
for deviceDOM in deviceDOMList:
- deviceLabel = className + "_" + deviceDOM.prop('label')
+ deviceLabel = paramClass.name + "_" + deviceDOM.prop('label')
deviceList += deviceLabel + ', ';
deviceList = deviceList[:-2] # remove last comma space
classList += rabbitTemplate.cDeviceModeClass_deviceList(blockList, deviceList)
@@ -384,16 +341,13 @@ def generateRabbitSources(paramDOM,sourceFolderPath,logTopics):
else: # BLOCK_MODE
# Generate the List of block in the class
- for blockIndex, blockDOM in enumerate(blockDOMList):
- # create instantation for current block
- blockName = blockDOM.prop('name')
-
+ for block in paramClass.getParamBlocks():
deviceList = ''
for deviceDOM in deviceDOMList:
deviceLabel = deviceDOM.prop('label')
- deviceList +=rabbitTemplate.cBlockModeDeviceInstantiation_deviceList(className, blockName, deviceLabel)
+ deviceList +=rabbitTemplate.cBlockModeDeviceInstantiation_deviceList(paramClass.name, block.name, deviceLabel)
- blockList += rabbitTemplate.cBlockModeBlockInstantiation(deviceList, className, blockName)
+ blockList += rabbitTemplate.cBlockModeBlockInstantiation(deviceList, paramClass.name, block.name)
# Predefine number of devices constant
cDataAllocation += NBdeviceDefinitionList
@@ -416,7 +370,7 @@ def generateRabbitSources(paramDOM,sourceFolderPath,logTopics):
cCodeString += cInitFunction
# Generate and append sample example
- cCodeString += rabbitTemplate.cExample(deploy.plcProtocol,True,className, blockName, registerName, deviceLabel)
+ cCodeString += rabbitTemplate.cExample(deploy.plcProtocol,True,paramClass.name, block.name, register.name, deviceLabel)
# Finally, write the String C generated code into the temporal output file
generateControllerFiles(sourceFolderPath,deploy,".h",cCodeString,logTopics);
@@ -435,10 +389,8 @@ def generateVirtualS7Sources(paramDOM,sourceFolderPath,logTopics):
protocolMode = 'DeviceMode';
duConstructor = virtualS7Template.vs7DuConstructor(deploy.plcName, protocolMode, deploy.address)
- classNodes = paramDOM.xpathEval("/SILECS-Param/SILECS-Mapping/SILECS-Class")
-
# Generate sources for each class that is deployed in the PLC
- for classNode in classNodes:
+ for paramClass in ParamClass.getParamClassesFromRootNode(paramDOM):
blocksCodeString = ''
@@ -449,21 +401,17 @@ def generateVirtualS7Sources(paramDOM,sourceFolderPath,logTopics):
createDeviceCodeString = ''
deleteDeviceCodeString = ''
designCodeString = ''
-
- blockDOMList = classNode.xpathEval("Block") # get Blocks elements of that class
- deviceDOMList = classNode.xpathEval("Instance") # get Device instances of that class
- className = classNode.prop('name')
- classVersion = classNode.prop('version')
+ deviceDOMList = paramClass.getDeviceInstanceNodes() # get Device instances of that class
#DEPLOY-UNIT code generation ============================
- includeDesign += virtualS7Template.vs7DuDesignInclude(className, classVersion)
- allocDesign += virtualS7Template.vs7DuDesignAlloc(className, classVersion)
- deleteDesign += virtualS7Template.vs7DuDesignDelete(className)
- getDesign += virtualS7Template.vs7DuDesignGet(className, classVersion)
+ includeDesign += virtualS7Template.vs7DuDesignInclude(paramClass.name, paramClass.version)
+ allocDesign += virtualS7Template.vs7DuDesignAlloc(paramClass.name, paramClass.version)
+ deleteDesign += virtualS7Template.vs7DuDesignDelete(paramClass.name)
+ getDesign += virtualS7Template.vs7DuDesignGet(paramClass.name, paramClass.version)
#CLASSES code generation ================================
- for blockIndex, blockDOM in enumerate(blockDOMList):
+ for block in paramClass.getParamBlocks():
getSetCodeString = ''
dimsCodeString = ''
dataCodeString = ''
@@ -471,53 +419,39 @@ def generateVirtualS7Sources(paramDOM,sourceFolderPath,logTopics):
currentRegisterAddress = 0 #used to compute even/odd adress and insert align data by adding dummy registers
previousRegisterMemSize = 0 #...
dummyIndex = 0;
-
- blockName = blockDOM.prop('name')
- blockOffset = blockDOM.prop('address')
- registerDOMList = blockDOM.xpathEval("Register") # get Registers of the current block
- createBlockCodeString += virtualS7Template.vs7ClassCreateBlock(className, blockName)
- deleteBlockCodeString += virtualS7Template.vs7ClassDeleteBlock(className, blockName)
+ createBlockCodeString += virtualS7Template.vs7ClassCreateBlock(paramClass.name, block.name)
+ deleteBlockCodeString += virtualS7Template.vs7ClassDeleteBlock(paramClass.name, block.name)
- for registerIndex, registerDOM in enumerate(registerDOMList):
- registerName = registerDOM.prop('name')
- registerFormat = registerDOM.prop('format')
- registerDimension1 = long(registerDOM.prop('array-dim1'))
- registerDimension2 = long(registerDOM.prop('array-dim2'))
- registerMemSize = long(registerDOM.prop('mem-size')) #store the reigster mem-size for next iteration
-
- registerLength = 1 #in case string
- if(registerFormat == 'string'):
- registerLength = long(registerDOM.prop('string-len'))
-
- getSetCodeString += virtualS7Template.vs7ClassGetSet(registerName, registerFormat, registerDimension1, registerDimension2,registerLength)
- dimsCodeString += virtualS7Template.vs7ClassDimension(registerName, registerFormat, registerDimension1, registerDimension2,registerLength)
+ for register in block.getParamRegisters():
+ getSetCodeString += virtualS7Template.vs7ClassGetSet(register.name, register.format, register.dim1, register.dim2,register.stringLength)
+ dimsCodeString += virtualS7Template.vs7ClassDimension(register.name, register.format, register.dim1, register.dim2,register.stringLength)
#Specific code to force 16bit alignment if not scalar 8bit register (==> insert dummy register if needed)
- dummyCodeString = virtualS7Template.vs7ClassDummyRegister(currentRegisterAddress, previousRegisterMemSize, registerMemSize, dummyIndex)
+ dummyCodeString = virtualS7Template.vs7ClassDummyRegister(currentRegisterAddress, previousRegisterMemSize, register.memSize, dummyIndex)
dataCodeString += dummyCodeString
- currentRegisterAddress += registerMemSize
+ currentRegisterAddress += register.memSize
if dummyCodeString != "":
dummyIndex += 1
currentRegisterAddress += 1
#and now insert the normal data register
- dataCodeString += virtualS7Template.vs7ClassDataRegister(registerName, registerFormat, registerDimension1, registerDimension2, registerLength)
- previousRegisterMemSize = registerMemSize
+ dataCodeString += virtualS7Template.vs7ClassDataRegister(register.name, register.format, register.dim1, register.dim2, register.stringLength)
+ previousRegisterMemSize = register.memSize
- blocksCodeString += virtualS7Template.vs7ClassBlock(deploy.silecsVersion, deploy.owner, deploy.checksum, className, blockName, getSetCodeString, blockOffset, dimsCodeString, dataCodeString)
+ blocksCodeString += virtualS7Template.vs7ClassBlock(deploy.silecsVersion, deploy.owner, deploy.checksum, paramClass.name, block.name, getSetCodeString, block.address, dimsCodeString, dataCodeString)
for deviceIndex, deviceDOM in enumerate(deviceDOMList):
deviceLabel = deviceDOM.prop('label')
- createDeviceCodeString += virtualS7Template.vs7ClassCreateDevice(className, deviceLabel, deviceIndex)
- deleteDeviceCodeString += virtualS7Template.vs7ClassDeleteDevice(className, deviceLabel)
+ createDeviceCodeString += virtualS7Template.vs7ClassCreateDevice(paramClass.name, deviceLabel, deviceIndex)
+ deleteDeviceCodeString += virtualS7Template.vs7ClassDeleteDevice(paramClass.name, deviceLabel)
deviceCodeString = virtualS7Template.vs7ClassDevice(createBlockCodeString, deleteBlockCodeString)
- designCodeString = virtualS7Template.vs7ClassDesign(className, classVersion, createDeviceCodeString, deleteDeviceCodeString)
+ designCodeString = virtualS7Template.vs7ClassDesign(paramClass.name, paramClass.version, createDeviceCodeString, deleteDeviceCodeString)
- classCodeString = virtualS7Template.vs7ClassHeader(className, classVersion, blocksCodeString, deviceCodeString, designCodeString)
+ classCodeString = virtualS7Template.vs7ClassHeader(paramClass.name, paramClass.version, blocksCodeString, deviceCodeString, designCodeString)
# write the CLASS generated code into the temporal output file
- generateControllerFiles(sourceFolderPath,deploy, "." + className + ".h",classCodeString,logTopics);
+ generateControllerFiles(sourceFolderPath,deploy, "." + paramClass.name + ".h",classCodeString,logTopics);
# Prepare the source (<.h> file) with its diagnostic data-block header
duCodeString = virtualS7Template.vs7DuHeader(deploy.plcName, duConstructor, includeDesign, allocDesign, deleteDesign, getDesign)
@@ -532,82 +466,61 @@ def generateVirtualS7Sources(paramDOM,sourceFolderPath,logTopics):
generateControllerFiles(sourceFolderPath,deploy,".cpp",mainCodeString,logTopics);
# ----------------------------------------------------
-def generateBeckhoffRegisters(classDOM, deviceDOM, blockDOM, deviceIndex, deploy, logTopics):
+def generateBeckhoffRegisters(paramClass, deviceDOM, block, deviceIndex, deploy, logTopics):
source = ''
- className = classDOM.prop('name')
deviceLabel = deviceDOM.prop('label')
- blockName = blockDOM.prop('name')
#Device and Block adresses come from the generated Paramerers file. Depends on the protocol mode:
#DEVICE_MODE: relative address of the element within it parent node
#BLOCK_MODE : absolute address in the entire PLC memory
deviceAddress = long(deviceDOM.prop('address'))
- blockAddress = long(blockDOM.prop('address'))
- blockMemSize = long(blockDOM.prop('mem-size'))
-
- registerDOMList = blockDOM.xpathEval("Register") # get registers of the current block
-
- for registerIndex, registerDOM in enumerate(registerDOMList):
- registerName = registerDOM.prop('name')
- registerFormat = registerDOM.prop('format')
- registerDimension1 = long(registerDOM.prop('array-dim1'))
- registerDimension2 = long(registerDOM.prop('array-dim2'))
-
- if registerDOM.prop('string-len'): # only appears for string registers
- registerLength = long(registerDOM.prop('string-len'))
-
- if blockName == 'hdrBlk':
- if registerName == 'ieVersion' or registerName == 'ieUser':
- registerFormat = 'string'
- registerDimension1 = 1
+ for register in block.getParamRegisters():
# If PLC does not supports this register format abort this generation and log the error
- if(registerFormat in ['uint64','int64','float64']):
- iecommon.logError('ERROR: In register '+registerName+', '+registerFormat+' format not supported for current controller model.', True)
+ if(register.format in ['uint64','int64','float64']):
+ iecommon.logError('ERROR: In register '+register.name+', '+register.format+' format not supported for current controller model.', True)
return
- #register has relative address irrespective of the protocol mode.
- registerOffset = long(registerDOM.prop('address'))
- iecommon.logDebug("Processing: %s %s %s %s" %(className, deviceLabel, blockName, registerName))
+ iecommon.logDebug("Processing: %s %s %s %s" %(paramClass.name, deviceLabel, block.name, register.name))
# Compute the register address relying on the Class Parameters file data
# Attention! Beckhoff uses WORD addressing while Parameters data are expressed in bytes to be PLC independent
if deploy.plcModel == 'BC9020':
- registerAddress = (blockAddress - long(deploy.address) + (deviceIndex * blockMemSize) + registerOffset)/2
+ totalAddress = (block.address - long(deploy.address) + (deviceIndex * block.memSize) + register.address)/2
elif deploy.plcModel == 'CX9020':
- registerAddress = (blockAddress - long(deploy.address) + (deviceIndex * blockMemSize) + registerOffset)
+ totalAddress = (block.address - long(deploy.address) + (deviceIndex * block.memSize) + register.address)
else:
raise "PLC model not supported: " + deploy.plcModel
# add comment to source to identify block
- source += ' (*'+className+'/'+deviceLabel+'/'+blockName+' *)\r\n'
+ source += ' (*'+paramClass.name+'/'+deviceLabel+'/'+block.name+' *)\r\n'
# Compute the base checksum of the class name
- classNameCRC = zlib.crc32(className,0) & 0xffff
+ classNameCRC = zlib.crc32(paramClass.name,0) & 0xffff
- if blockName == 'hdrBlk':
- if registerName == '_version':
- source+=beckhoffRegInit %(registerName, classNameCRC, deviceLabel, registerAddress, whichTwincatFormat[registerFormat]+"(16)", deploy.silecsVersion )
- if registerName == '_user':
- source+=beckhoffRegInit %(registerName, classNameCRC, deviceLabel, registerAddress, whichTwincatFormat[registerFormat]+"(16)", "'"+deploy.owner+"'")
- if registerName == '_checksum':
- source+=beckhoffRegInit %(registerName, classNameCRC, deviceLabel, registerAddress, whichTwincatFormat[registerFormat], deploy.checksum)
- if registerName == '_date':
- source+=beckhoffRegInit %(registerName, classNameCRC, deviceLabel, registerAddress, whichTwincatFormat[registerFormat], getDateTime())
+ if block.name == 'hdrBlk':
+ if register.name == '_version':
+ source+=beckhoffRegInit %(register.name, classNameCRC, deviceLabel, totalAddress, whichTwincatFormat[register.format]+"(16)", deploy.silecsVersion )
+ if register.name == '_user':
+ source+=beckhoffRegInit %(register.name, classNameCRC, deviceLabel, totalAddress, whichTwincatFormat[register.format]+"(16)", "'"+deploy.owner+"'")
+ if register.name == '_checksum':
+ source+=beckhoffRegInit %(register.name, classNameCRC, deviceLabel, totalAddress, whichTwincatFormat[register.format], deploy.checksum)
+ if register.name == '_date':
+ source+=beckhoffRegInit %(register.name, classNameCRC, deviceLabel, totalAddress, whichTwincatFormat[register.format], getDateTime())
else: # not header block
# set data type - for string with fixed value registerLength
- if registerFormat == 'string':
- format = whichTwincatFormat[registerFormat]+'('+str(registerLength)+')'
+ if register.format == 'string':
+ format = whichTwincatFormat[register.format]+'('+str(register.stringLength)+')'
else:
- format = whichTwincatFormat[registerFormat]
+ format = whichTwincatFormat[register.format]
- if registerDimension1 == 1 and registerDimension2 == 1: # scalar
- source += beckhoffReg %(registerName, classNameCRC, deviceLabel, registerAddress, format)
- elif registerDimension1 > 1 and registerDimension2 == 1: # array
- source += beckhoffRegArray %(registerName, classNameCRC, deviceLabel, registerAddress, registerDimension1-1, format)
+ if register.dim1 == 1 and register.dim2 == 1: # scalar
+ source += beckhoffReg %(register.name, classNameCRC, deviceLabel, totalAddress, format)
+ elif register.dim1 > 1 and register.dim2 == 1: # array
+ source += beckhoffRegArray %(register.name, classNameCRC, deviceLabel, totalAddress, register.dim1-1, format)
else: # dim1>=1 and for whatever dim2, use double array syntax
- source += beckhoffRegArray2d %(registerName, classNameCRC, deviceLabel, registerAddress, registerDimension1-1, registerDimension2-1, format)
+ source += beckhoffRegArray2d %(register.name, classNameCRC, deviceLabel, totalAddress, register.dim1-1, register.dim2-1, format)
return source
# ----------------------------------------------------
@@ -626,16 +539,13 @@ def generateBeckhoffSources(paramDOM, sourceFolderPath, logTopics):
source += '\r\nVAR_GLOBAL\r\n'
- classNodes = paramDOM.xpathEval("/SILECS-Param/SILECS-Mapping/SILECS-Class")
- for classNode in classNodes:
- address = int(classNode.prop('address')) # address of the first register of the configuration
- blockDOMList = classNode.xpathEval("Block") # get Blocks elements of that class
- deviceDOMList = classNode.xpathEval("Instance") # get Device instances of that class
+ for paramClass in ParamClass.getParamClassesFromRootNode(paramDOM):
+ deviceDOMList = paramClass.getDeviceInstanceNodes() # get Device instances of that class
# Device mode is not supported for Beckhoff PLCs - Only block mode available
- for blockDOM in blockDOMList:
+ for block in paramClass.getParamBlocks():
for deviceIndex, deviceDOM in enumerate(deviceDOMList):
- source += generateBeckhoffRegisters(classNode, deviceDOM, blockDOM, deviceIndex,deploy,logTopics)
+ source += generateBeckhoffRegisters(paramClass, deviceDOM, block, deviceIndex,deploy,logTopics)
source += 'END_VAR'
diff --git a/silecs-codegen/src/xml/iecommon.py b/silecs-codegen/src/xml/iecommon.py
index ab625ffc1885e965b8166c77a6a86c62c435f51e..720e594ecb24684dca6c6f9772a4d0ccd403a5f9 100644
--- a/silecs-codegen/src/xml/iecommon.py
+++ b/silecs-codegen/src/xml/iecommon.py
@@ -61,6 +61,16 @@ def logToFile(path,msg):
#-------------------------------------------------------------------------
# General XML Parsing
#-------------------------------------------------------------------------
+
+def xsdBooleanToBoolean(value):
+ # Remove trailing and leading whitespaces
+ value = value.strip()
+ if value == 'true' or value == '1':
+ return True
+ elif value == 'false' or value == '0':
+ return False
+ raise ValueError(value + ' is not a valid xsd:boolean value')
+
def hasChildren(element):
children = element.xpathEval("*")
if len(children):
@@ -139,94 +149,6 @@ def fillAttributes(element, attrs):
element.setProp(name, value)
return element
-#-------------------------------------------------------------------------
-# Given an SILECS data type, returns the corresponding FESA data type
-# For the time being FESA does not support unsigned data types in properties
-# so here unsigned types are considered as signed to allow users to link
-# any field to properties
-#-------------------------------------------------------------------------
-def getFesaDataType(type):
- return {
- 'int8' :'int8_t',
- 'uint8' :'int16_t',
- 'int16' :'int16_t',
- 'uint16' :'int32_t',
- 'int32' :'int32_t',
- 'uint32' :'int64_t',
- 'int64' :'int64_t',
- 'uint64' :'uint64_t', # only for PXI, but not supported from Java! Not possible to use it in FESA properties
- 'float32' :'float',
- 'float64' :'double',
- 'date' :'double',
- 'char' :'int8_t',
- 'byte' :'int16_t',
- 'word' :'int32_t',
- 'dword' :'int64_t',
- 'int' :'int16_t',
- 'dint' :'int32_t',
- 'real' :'float',
- 'dt' :'double',
- 'string' :'char'
- }[type]
-
-def getCDataType(type):
- return {
- 'int8' :'int8_t',
- 'uint8' :'uint8_t',
- 'int16' :'int16_t',
- 'uint16' :'uint16_t',
- 'int32' :'int32_t',
- 'uint32' :'uint32_t',
- 'int64' :'int64_t',
- 'uint64' :'uint64_t',
- 'float32' :'float',
- 'float64' :'double',
- 'date' :'double',
- 'char' :'int8_t',
- 'byte' :'int16_t',
- 'word' :'int32_t',
- 'dword' :'int64_t',
- 'int' :'int16_t',
- 'dint' :'int32_t',
- 'real' :'float',
- 'dt' :'double',
- 'string' :'std::string'
- }[type]
-#-------------------------------------------------------------------------
-# Given data type, returns the corresponding
-# SILECS data type
-#-------------------------------------------------------------------------
-def getSilecsDataType(type):
- return {
- 'byte' :'uint8',
- 'char' :'int8',
- 'unsigned char' :'uint8',
- 'short' :'int16',
- 'unsigned short':'uint16',
- 'long' :'int32', # conversion relies on 32-bit platform (FESA 3 does not support long type anymore)
- 'unsigned long' :'uint32',
- 'double' :'float64',
- 'float' :'float32',
- 'word' :'uint16',
- 'dword' :'uint32',
- 'int' :'int16',
- 'dint' :'int32',
- 'real' :'float32',
- 'dt' :'date',
- 'uint8' :'uint8',
- 'int8' :'int8',
- 'uint16' :'uint16',
- 'int16' :'int16',
- 'uint32' :'uint32',
- 'int32' :'int32',
- 'uint64' :'uint64',
- 'int64' :'int64',
- 'float32' :'float32',
- 'float64' :'float64',
- 'date' :'date',
- 'string' : 'string'
- }[type]
-
def capitalizeString(text):
str = ""
if len(text) > 0:
diff --git a/silecs-codegen/src/xml/migration/0_10_0to1_0_0.py b/silecs-codegen/src/xml/migration/0_10_xto1_0_x.py
similarity index 67%
rename from silecs-codegen/src/xml/migration/0_10_0to1_0_0.py
rename to silecs-codegen/src/xml/migration/0_10_xto1_0_x.py
index 775ffdbf443957562a8e26c881f427774ff5ec45..eca47e5b94fbc5fda8a969ce9b8ad374bf69c3e1 100644
--- a/silecs-codegen/src/xml/migration/0_10_0to1_0_0.py
+++ b/silecs-codegen/src/xml/migration/0_10_xto1_0_x.py
@@ -41,32 +41,6 @@ class Migration(MigrationBase):
self.migrateFESAInstanceFile()
return modified
- def backupOldFESAMakeSpecific(self):
- results = self.parser.parse_args()
- silecsDocument = results.silecsDocument
- projectDir = FileUtils.getProjectDir(silecsDocument)
- makeSpecific = projectDir + "/Makefile.specific"
- if os.path.isfile(makeSpecific):
- os.rename(makeSpecific, makeSpecific + ".backup")
- print("Backed up old FESA Make.specific file: " + makeSpecific)
-
- def removeGenCode(self):
- results = self.parser.parse_args()
- silecsDocument = results.silecsDocument
- projectDir = FileUtils.getProjectDir(silecsDocument)
- clientFolder = projectDir + "/generated/client"
- controllerFolder = projectDir + "/generated/controller"
- wrapperFolder = projectDir + "/generated/wrapper"
- if os.path.isdir(clientFolder):
- shutil.rmtree(clientFolder)
- print("removed generation folder: " + clientFolder)
- if os.path.isdir(controllerFolder):
- shutil.rmtree(controllerFolder)
- print("removed generation folder: " + controllerFolder)
- if os.path.isdir(wrapperFolder):
- shutil.rmtree(wrapperFolder)
- print("removed generation folder: " + wrapperFolder)
-
def migrateFESAInstanceFile(self):
results = self.parser.parse_args()
silecsDocument = results.silecsDocument
diff --git a/silecs-codegen/src/xml/migration/0_9_0to0_10_0.py b/silecs-codegen/src/xml/migration/0_9_xto0_10_x.py
similarity index 100%
rename from silecs-codegen/src/xml/migration/0_9_0to0_10_0.py
rename to silecs-codegen/src/xml/migration/0_9_xto0_10_x.py
diff --git a/silecs-codegen/src/xml/migration/1_0_xto2_0_x.py b/silecs-codegen/src/xml/migration/1_0_xto2_0_x.py
new file mode 100644
index 0000000000000000000000000000000000000000..16d1032552de1ab25e59e82a5e708369d6978bca
--- /dev/null
+++ b/silecs-codegen/src/xml/migration/1_0_xto2_0_x.py
@@ -0,0 +1,41 @@
+#!/usr/bin/python
+# Copyright 2016 CERN and GSI
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+import os
+import sys
+
+from migrationBase import MigrationBase
+from migration1_0_Xto2_0_0.migrators import *
+
+import libxml2
+import sys
+import FileUtils
+import shutil
+
+class Migration(MigrationBase):
+ def __init__(self, arguments):
+ super(Migration, self).__init__()
+
+ def migrateClass(self, context, projectDir ):
+ modified = designValueTypeMigrator(context)
+ modified |= designBlockRegisterMigrator(context)
+ return modified
+
+
+if __name__ == "__main__":
+ migration = Migration(sys.argv)
+ migration.migrate()
+ migration.backupOldFESAMakeSpecific()
diff --git a/silecs-codegen/src/xml/migration/migration1_0_Xto2_0_0/__init__.py b/silecs-codegen/src/xml/migration/migration1_0_Xto2_0_0/__init__.py
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/silecs-codegen/src/xml/migration/migration1_0_Xto2_0_0/migrators.py b/silecs-codegen/src/xml/migration/migration1_0_Xto2_0_0/migrators.py
new file mode 100644
index 0000000000000000000000000000000000000000..ca2aa04913210a32542bb6b5f4de74d4116b2162
--- /dev/null
+++ b/silecs-codegen/src/xml/migration/migration1_0_Xto2_0_0/migrators.py
@@ -0,0 +1,91 @@
+#!/usr/bin/python
+# Copyright 2016 CERN and GSI
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+import libxml2
+
+def designValueTypeMigrator(context):
+ modified = False
+ for register in context.xpathEval("//Register"):
+ format = register.prop("format")
+ register.unsetProp("format")
+ dim1 = "1"
+ dim2 = "1"
+ stringLength ="64" #thats the default
+
+ if register.hasProp("string-len"):
+ stringLength = register.prop("string-len")
+ register.unsetProp("string-len")
+ if register.hasProp("array-dim1"):
+ dim1 = register.prop("array-dim1")
+ register.unsetProp("array-dim1")
+ if register.hasProp("array-dim2"):
+ dim2 = register.prop("array-dim2")
+ register.unsetProp("array-dim2")
+
+ valueType = None
+ if(format == 'string'):
+ if int(dim1) > 1:
+ if int(dim2) > 1:
+ valueType = libxml2.newNode("stringArray2D")
+ valueType.newProp("dim1",dim1)
+ valueType.newProp("dim2",dim2)
+ else:
+ valueType = libxml2.newNode("stringArray")
+ valueType.newProp("dim",dim1)
+ else:
+ valueType = libxml2.newNode("string")
+ valueType.newProp("string-length",stringLength)
+ else:
+ if int(dim1) > 1:
+ if int(dim2) > 1:
+ valueType = libxml2.newNode("array2D")
+ valueType.newProp("dim1",dim1)
+ valueType.newProp("dim2",dim2)
+ else:
+ valueType = libxml2.newNode("array")
+ valueType.newProp("dim",dim1)
+ else:
+ valueType = libxml2.newNode("scalar")
+ valueType.newProp("format",format)
+ register.addChild(valueType)
+ modified = True
+ return modified
+
+def designBlockRegisterMigrator(context):
+ modified = False
+ for blockNode in context.xpathEval("SILECS-Design/SILECS-Class/Block"):
+ for childNode in blockNode.get_children():
+ if childNode.get_name() == 'Register':
+ if blockNode.prop("mode") == 'READ-ONLY':
+ childNode.setName("Acquisition-Register")
+ elif blockNode.prop("mode") == 'WRITE-ONLY':
+ childNode.setName("Setting-Register")
+ else: #READ-WRITE
+ if childNode.prop("synchro") == 'SLAVE':
+ childNode.setName("Setting-Register")
+ else:
+ childNode.setName("Volatile-Register")
+ childNode.unsetProp("synchro")
+
+ if blockNode.prop("mode") == 'READ-ONLY':
+ blockNode.setName("Acquisition-Block")
+ elif blockNode.prop("mode") == 'WRITE-ONLY':
+ blockNode.setName("Command-Block")
+ else: #READ-WRITE
+ blockNode.setName("Setting-Block")
+ blockNode.unsetProp("mode")
+ modified = True
+ return modified
diff --git a/silecs-codegen/src/xml/migration/migration1_0_Xto2_0_0/testMigration.py b/silecs-codegen/src/xml/migration/migration1_0_Xto2_0_0/testMigration.py
new file mode 100644
index 0000000000000000000000000000000000000000..c9b0a8f860fc92358f74335cc98a651b203c4484
--- /dev/null
+++ b/silecs-codegen/src/xml/migration/migration1_0_Xto2_0_0/testMigration.py
@@ -0,0 +1,122 @@
+#!/usr/bin/python
+# Copyright 2016 CERN and GSI
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+from test.testBase import *
+
+import libxml2
+from migration.migration1_0_Xto2_0_0.migrators import *
+import inspect #get caller name
+
+def testdesignValueTypeMigrator():
+
+ SilecsDesignOld = '''<?xml version="1.0" encoding="UTF-8"?>
+ <SILECS-Design xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ silecs-version="0.10.0" created="03/21/16" updated="03/21/16"
+ xsi:noNamespaceSchemaLocation="/common/usr/cscofe/silecs/0.10.0/silecs-model/src/xml/DesignSchema.xsd">
+ <Information>
+ <Owner user-login="schwinn" />
+ <Editor user-login="schwinn" />
+ </Information>
+ <SILECS-Class name="PneuDrive" version="0.1.0" domain="TEST">
+ <Block name="Acq" mode="READ-ONLY">
+ <Register name="string1" synchro="MASTER" format="string" />
+ <Register name="string2" synchro="MASTER" format="string" string-len="65"/>
+ <Register name="string1D" synchro="MASTER" format="string" array-dim1="2" />
+ <Register name="string2D" synchro="MASTER" format="string" array-dim1="2" array-dim2="4"/>
+ <Register name="scalar" synchro="MASTER" format="int8" />
+ <Register name="scalar1D" synchro="MASTER" format="int8" array-dim1="2" />
+ <Register name="scalar2D" synchro="MASTER" format="int8" array-dim1="2" array-dim2="4"/>
+ </Block>
+ </SILECS-Class>
+ </SILECS-Design>'''
+ context = libxml2.parseDoc(SilecsDesignOld)
+
+ designValueTypeMigrator(context)
+ #context.shellPrintNode() #for debug
+ scalar = context.xpathEval("//Register[not(@format)]/scalar[@format='int8']")
+ array = context.xpathEval("//Register[not(@array-dim1)]/array[@dim='2' and @format='int8']")
+ array2D = context.xpathEval("//Register[not(@array-dim2)]/array2D[@dim1='2' and @dim2='4' and @format='int8']")
+ string1 = context.xpathEval("//Register/string[@format='string' and @string-length='64']")
+ string2 = context.xpathEval("//Register[not(@string-len)]/string[@format='string' and @string-length='65']")
+ stringArray = context.xpathEval("//Register/stringArray[@dim='2' and @format='string' and @string-length='64']")
+ stringArray2D = context.xpathEval("//Register/stringArray2D[@dim1='2' and @dim2='4' and @format='string' and @string-length='64']")
+
+
+ assertEqual(len(scalar),1)
+ assertEqual(len(array),1)
+ assertEqual(len(array2D),1)
+ assertEqual(len(string1),1)
+ assertEqual(len(string2),1)
+ assertEqual(len(stringArray),1)
+ assertEqual(len(stringArray2D),1)
+
+
+
+def testdesignBlockRegisterMigrator():
+ SilecsDesignOld = '''<?xml version="1.0" encoding="UTF-8"?>
+ <SILECS-Design xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+ silecs-version="0.10.0" created="03/21/16" updated="03/21/16"
+ xsi:noNamespaceSchemaLocation="/common/usr/cscofe/silecs/0.10.0/silecs-model/src/xml/DesignSchema.xsd">
+ <Information>
+ <Owner user-login="schwinn" />
+ <Editor user-login="schwinn" />
+ </Information>
+ <SILECS-Class name="PneuDrive" version="0.1.0" domain="TEST">
+ <Block name="block1" mode="READ-ONLY">
+ <Register name="b1r1" synchro="MASTER" format="string" />
+ <Register name="b1r2" synchro="NONE" format="string" array-dim1="2" />
+ </Block>
+ <Block name="block2" mode="READ-WRITE">
+ <Register name="b2r1" synchro="MASTER" format="string" />
+ <Register name="b2r2" synchro="SLAVE" format="string" />
+ <Register name="b2r3" synchro="NONE" format="string" array-dim1="2" />
+ </Block>
+ <Block name="block3" mode="WRITE-ONLY">
+ <Register name="b3r1" synchro="SLAVE" format="string" />
+ <Register name="b3r2" synchro="NONE" format="string" array-dim1="2" />
+ </Block>
+ </SILECS-Class>
+ </SILECS-Design>'''
+ context = libxml2.parseDoc(SilecsDesignOld)
+ designBlockRegisterMigrator(context)
+ context.shellPrintNode() #for debug
+
+ oldBlocks = context.xpathEval("//Block")
+ oldRegisters = context.xpathEval("//Register")
+ assertEqual(len(oldBlocks),0)
+ assertEqual(len(oldRegisters),0)
+
+ block1 = context.xpathEval("/SILECS-Design/SILECS-Class/Acquisition-Block")
+ block2 = context.xpathEval("/SILECS-Design/SILECS-Class/Setting-Block")
+ block3 = context.xpathEval("/SILECS-Design/SILECS-Class/Command-Block")
+ assertEqual(len(block1),1)
+ assertEqual(len(block2),1)
+ assertEqual(len(block3),1)
+
+ b1r1 = context.xpathEval("/SILECS-Design/SILECS-Class/Acquisition-Block/Acquisition-Register[@name='b1r1']")
+ b1r2 = context.xpathEval("/SILECS-Design/SILECS-Class/Acquisition-Block/Acquisition-Register[@name='b1r2']")
+
+ b2r1 = context.xpathEval("/SILECS-Design/SILECS-Class/Setting-Block/Volatile-Register[@name='b2r1']")
+ b2r2 = context.xpathEval("/SILECS-Design/SILECS-Class/Setting-Block/Setting-Register[@name='b2r2']") # synchro = master ? --> Missconfiguration --> We should have this reg in an acquisition-block
+ b2r3 = context.xpathEval("/SILECS-Design/SILECS-Class/Setting-Block/Volatile-Register[@name='b2r3']")
+
+ b3r2 = context.xpathEval("/SILECS-Design/SILECS-Class/Command-Block/Setting-Register[@name='b3r1']")
+ b3r2 = context.xpathEval("/SILECS-Design/SILECS-Class/Command-Block/Setting-Register[@name='b3r2']")
+
+def runTests():
+ testdesignValueTypeMigrator()
+ testdesignBlockRegisterMigrator()
+ # print deployDoc # for debugging
diff --git a/silecs-codegen/src/xml/migration/migrationBase.py b/silecs-codegen/src/xml/migration/migrationBase.py
index a35e2aa3e48875c2432e1e17d07ac8071faf7461..dd53b6067685e1e2613104ae87cbfdc13e56eb9d 100644
--- a/silecs-codegen/src/xml/migration/migrationBase.py
+++ b/silecs-codegen/src/xml/migration/migrationBase.py
@@ -44,6 +44,32 @@ class MigrationBase(object):
root.setProp("xsi:noNamespaceSchemaLocation",xmlSchema)
print("Info: Replaced old silecs-xmlSchema")
+ def backupOldFESAMakeSpecific(self):
+ results = self.parser.parse_args()
+ silecsDocument = results.silecsDocument
+ projectDir = FileUtils.getProjectDir(silecsDocument)
+ makeSpecific = projectDir + "/Makefile.specific"
+ if os.path.isfile(makeSpecific):
+ os.rename(makeSpecific, makeSpecific + ".backup")
+ print("Backed up old FESA Make.specific file: " + makeSpecific)
+
+ def removeGenCode(self):
+ results = self.parser.parse_args()
+ silecsDocument = results.silecsDocument
+ projectDir = FileUtils.getProjectDir(silecsDocument)
+ clientFolder = projectDir + "/generated/client"
+ controllerFolder = projectDir + "/generated/controller"
+ wrapperFolder = projectDir + "/generated/wrapper"
+ if os.path.isdir(clientFolder):
+ shutil.rmtree(clientFolder)
+ print("removed generation folder: " + clientFolder)
+ if os.path.isdir(controllerFolder):
+ shutil.rmtree(controllerFolder)
+ print("removed generation folder: " + controllerFolder)
+ if os.path.isdir(wrapperFolder):
+ shutil.rmtree(wrapperFolder)
+ print("removed generation folder: " + wrapperFolder)
+
def migrate(self):
results = self.parser.parse_args()
silecsDocument = results.silecsDocument
diff --git a/silecs-codegen/src/xml/migration/runTests.py b/silecs-codegen/src/xml/migration/runTests.py
index 86c7e163af06cab443ebaf5f0f2ec579fabdb7d7..f9b3568a4c2b869a5ee01df411c63ee059757ef8 100644
--- a/silecs-codegen/src/xml/migration/runTests.py
+++ b/silecs-codegen/src/xml/migration/runTests.py
@@ -17,6 +17,7 @@
from test.testBase import *
import migration.migration_0_9_0to0_10_0.testMigration
import migration.migration0_10_0to1_0_0.testMigration
+import migration.migration1_0_Xto2_0_0.testMigration
SilecsDeployOld = '''<?xml version="1.0" encoding="UTF-8"?>
<SILECS-Deploy silecs-version="oldVersion" created="03/04/16" updated="03/04/16"
@@ -46,4 +47,5 @@ def runAllTests():
# runbaseTests()
migration.migration_0_9_0to0_10_0.testMigration.runTests()
migration.migration0_10_0to1_0_0.testMigration.runTests()
+ migration.migration1_0_Xto2_0_0.testMigration.runTests()
allTestsOk()
diff --git a/silecs-codegen/src/xml/model/Block.py b/silecs-codegen/src/xml/model/Block.py
new file mode 100644
index 0000000000000000000000000000000000000000..45ed1f6e2ae83450c022db9e6d3097222464c24a
--- /dev/null
+++ b/silecs-codegen/src/xml/model/Block.py
@@ -0,0 +1,135 @@
+#!/usr/bin/python
+# Copyright 2016 CERN and GSI
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+from iecommon import *
+from model.Register import *
+import libxml2
+
+
+class Block(object):
+
+ ___settingBlockType = "Setting-Block"
+ ___acquisitionBlockType = "Acquisition-Block"
+ ___commandBlockType = "Command-Block"
+ name = ""
+ ___type = ""
+ xmlNode = None
+
+ def __init__(self, xmlNode):
+ self.xmlNode = xmlNode
+ self.name = xmlNode.prop("name")
+ self.___type = xmlNode.get_name()
+ #xmlNode.shellPrintNode()
+
+ def getNameCapitalized(self):
+ return iecommon.capitalizeString(self.name)
+
+ def isReadable(self):
+ return self.___type == self.___settingBlockType or self.___type == self.___acquisitionBlockType
+
+ def isWritable(self):
+ return self.___type == self.___settingBlockType or self.___type == self.___commandBlockType
+
+ def isAcquisition(self):
+ return self.___type == self.___acquisitionBlockType
+
+ def isSetting(self):
+ return self.___type == self.___settingBlockType
+
+ def isCommand(self):
+ return self.___type == self.___commandBlockType
+
+ def getRegisterNodes(self):
+ return self.xmlNode.xpathEval("*[name()='Acquisition-Register' or name()='Setting-Register' or name()='Volatile-Register']")
+
+#has some additionalValues
+class ParamBlock(Block):
+ def __init__(self):
+ self.size = 0
+ self.address = 0
+ self.memSize = 0
+
+
+ def initWithParamBlockNode(self, xmlNode):
+ super(ParamBlock, self).__init__(xmlNode)
+ self.size = long(self.xmlNode.prop("size"))
+ self.address = long(self.xmlNode.prop("address"))
+ self.memSize = long(self.xmlNode.prop("mem-size"))
+
+ def initWithDesignBlock(self, designBlock):
+ newNode = libxml2.newNode(designBlock.xmlNode.get_name())
+ newNode.newProp("name", designBlock.name)
+ super(ParamBlock, self).__init__(newNode)
+ newNode.newProp("size", str(self.size))
+ newNode.newProp("address", str(self.address))
+ newNode.newProp("mem-size", str(self.memSize))
+
+ def setSize(self,size):
+ self.xmlNode.setProp("size", str(size))
+ self.size = size
+
+ def setAddress(self,address):
+ self.xmlNode.setProp("address", str(address))
+ self.address = address
+
+ def setMemSize(self,memSize):
+ self.xmlNode.setProp("mem-size", str(memSize))
+ self.memSize = memSize
+
+ def getParamRegisters(self):
+ paramRegisters = []
+ for registerNode in self.getRegisterNodes():
+ paramRegister = ParamRegister()
+ paramRegister.initWithParamRegisterNode(registerNode)
+ paramRegisters.append(paramRegister)
+ return paramRegisters
+
+
+class DesignBlock(Block):
+ generateFesaProperty = False
+ fesaPropertyName = ""
+ fesaGetServerActionName = ""
+ fesaSetServerActionName = ""
+
+ def __init__(self, xmlNode):
+ super(DesignBlock, self).__init__(xmlNode)
+
+ if self.xmlNode.hasProp("fesaPropertyName"):
+ self.fesaPropertyName = xmlNode.prop("fesaPropertyName")
+ else:
+ self.fesaPropertyName = self.name
+
+ if self.xmlNode.hasProp("generateFesaProperty"): #SilecsHEader does not have this attribute
+ self.generateFesaProperty = xsdBooleanToBoolean(xmlNode.prop("generateFesaProperty"))
+
+ if self.xmlNode.hasProp("fesaGetServerActionName"):
+ self.fesaGetServerActionName = xmlNode.prop("fesaGetServerActionName")
+ else:
+ self.fesaGetServerActionName = 'Get' + self.fesaPropertyName
+
+ if self.xmlNode.hasProp("fesaSetServerActionName"):
+ self.fesaSetServerActionName = xmlNode.prop("fesaSetServerActionName")
+ else:
+ self.fesaSetServerActionName = 'Set' + self.fesaPropertyName
+
+ def getFesaName(self):
+ return self.fesaPropertyName
+
+ def getDesignRegisters(self):
+ designRegisters = []
+ for registerNode in self.getRegisterNodes():
+ designRegisters.append(DesignRegister(registerNode))
+ return designRegisters
diff --git a/silecs-codegen/src/xml/model/Class.py b/silecs-codegen/src/xml/model/Class.py
new file mode 100644
index 0000000000000000000000000000000000000000..f7fd3d0e11cbf185624af021bea18586031c5cfe
--- /dev/null
+++ b/silecs-codegen/src/xml/model/Class.py
@@ -0,0 +1,112 @@
+#!/usr/bin/python
+# Copyright 2016 CERN and GSI
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+from iecommon import *
+from model.Block import *
+import libxml2
+
+class Class(object):
+
+ name = ""
+ version = ""
+ xmlNode = None
+
+ def __init__(self, xmlNode):
+ self.xmlNode = xmlNode
+ self.name = xmlNode.prop("name")
+ self.version = xmlNode.prop("version")
+ #xmlNode.shellPrintNode()
+
+ def getNameCapitalized(self):
+ return iecommon.capitalizeString(self.name)
+
+ def getBlockNodes(self):
+ return self.xmlNode.xpathEval("*[name()='Acquisition-Block' or name()='Setting-Block' or name()='Command-Block']")
+
+class ParamClass(Class):
+ def __init__(self):
+ self.address = 0
+ self.usedMemory = ""
+
+
+ def initWithParamClassNode(self, xmlNode):
+ super(ParamClass, self).__init__(xmlNode)
+ self.address = long(self.xmlNode.prop("address"))
+ self.usedMemory = self.xmlNode.prop("usedMemory")
+
+ def initWithDesignClass(self, designClass):
+ newNode = libxml2.newNode(designClass.xmlNode.get_name())
+ newNode.newProp("name", designClass.name)
+ newNode.newProp("version", designClass.version)
+ super(ParamClass, self).__init__(newNode)
+ newNode.newProp("address", str(self.address))
+ newNode.newProp("usedMemory", self.usedMemory)
+
+ def setAddress(self,address):
+ self.xmlNode.setProp("address", str(address))
+ self.address = address
+
+ def setUsedMemory(self,usedMemory):
+ self.xmlNode.setProp("usedMemory", usedMemory)
+ self.usedMemory = usedMemory
+
+ def getParamBlocks(self):
+ paramBlocks = []
+ for blockNode in self.getBlockNodes():
+ paramBlock = ParamBlock()
+ paramBlock.initWithParamBlockNode(blockNode)
+ paramBlocks.append(paramBlock)
+ return paramBlocks
+
+ def getDeviceInstanceNodes(self):
+ deviceNodes = self.xmlNode.xpathEval("Instance")
+ return deviceNodes
+
+ @staticmethod
+ def getParamClassesFromRootNode(silecsRoot):
+ classNodes = silecsRoot.xpathEval("/SILECS-Param/SILECS-Mapping/SILECS-Class")
+ if len(classNodes) < 1:
+ raise BaseException("Error: no class-node found in design-document")
+ paramClasses = []
+ for classNode in classNodes:
+ paramClass = ParamClass()
+ paramClass.initWithParamClassNode(classNode)
+ paramClasses.append(paramClass)
+ return paramClasses
+
+
+class DesignClass(Class):
+ def __init__(self, xmlNode):
+ super(DesignClass, self).__init__(xmlNode)
+ self.fesaPropertyName = self.name
+
+ def getFesaName(self):
+ return self.fesaPropertyName
+
+ def getDesignBlocks(self):
+ designBlocks = []
+ for blockNode in self.getBlockNodes():
+ designBlocks.append(DesignBlock(blockNode))
+ return designBlocks
+
+ @staticmethod
+ def getDesignClassFromRootNode(silecsRoot):
+ classNodes = silecsRoot.xpathEval('/SILECS-Design/SILECS-Class')
+ if len(classNodes) > 1:
+ raise "Error: multiple class-nodes found in design-document"
+ if len(classNodes) < 1:
+ raise "Error: no class-node found in design-document"
+ return DesignClass(classNodes[0])
diff --git a/silecs-codegen/src/xml/model/Register.py b/silecs-codegen/src/xml/model/Register.py
new file mode 100644
index 0000000000000000000000000000000000000000..ac69f2134ce6b9c4926784a2706e66264c4e0116
--- /dev/null
+++ b/silecs-codegen/src/xml/model/Register.py
@@ -0,0 +1,291 @@
+#!/usr/bin/python
+# Copyright 2016 CERN and GSI
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+from iecommon import *
+import libxml2
+
+class Register(object):
+ ___settingRegisterType = "Setting-Register"
+ ___acquisitionRegisterType = "Acquisition-Register"
+ ___volatileRegisterType = "Volatile-Register"
+
+ ___type = ""
+ xmlNode = None
+ name = ""
+ valueTypeNode = None
+ valueType = ""
+ dim1 = 1
+ dim2 = 1
+ stringLength = 1 # ... currently needs to be default because of some old convention
+ format = ""
+
+ def __init__(self, xmlNode):
+ self.xmlNode = xmlNode
+
+ #xmlNode.shellPrintNode()
+ self.name = xmlNode.prop("name")
+ self.___type = xmlNode.get_name()
+
+ valueTypes = xmlNode.xpathEval("*[name()='scalar' or name()='array' or name()='array2D' or name()='string' or name()='stringArray' or name()='stringArray2D']")
+ if not valueTypes:
+ iecommon.logError('ERROR: The register '+ self.name +' has no valueTypes.', True, {'errorlog': True})
+ if len(valueTypes) < 1:
+ iecommon.logError('ERROR: The register '+ self.name +' has no valueTypes.', True, {'errorlog': True})
+ if len(valueTypes) > 1:
+ iecommon.logError('ERROR: The register '+ self.name +' has multiple valueTypes.', True, {'errorlog': True})
+ self.valueTypeNode = valueTypes[0]
+ self.valueType = self.valueTypeNode.get_name()
+
+ if self.valueTypeNode.hasProp("dim1"):
+ self.dim1 = long(self.valueTypeNode.prop("dim1"))
+ elif self.valueTypeNode.hasProp("dim"):
+ self.dim1 = long(self.valueTypeNode.prop("dim"))
+
+ if self.valueTypeNode.hasProp("dim2"):
+ self.dim2 = long(self.valueTypeNode.prop("dim2"))
+
+ if self.valueTypeNode.hasProp("string-length"):
+ self.stringLength = long(self.valueTypeNode.prop("string-length"))
+
+ self.format = self.valueTypeNode.prop("format")
+
+ def getNameCapitalized(self):
+ return iecommon.capitalizeString(self.name)
+
+ def isUnsigned(self):
+ type = self.getSilecsDataType()
+ if type[0] == 'u':
+ return True
+ return False
+
+ def getSilecsTypeCapitalized(self):
+ return self.getSilecsDataTypeUpperCase()
+
+ def isScalar(self):
+ return self.valueType == 'scalar'
+
+ def isString(self):
+ return self.valueType == 'string'
+
+ def isStringArray(self):
+ return self.valueType == 'stringArray'
+
+ def isArray(self):
+ return self.valueType == 'array' or self.valueType == 'stringArray'
+
+ def isArray2D(self):
+ return self.valueType == 'array2D' or self.valueType == 'stringArray2D'
+
+ def isStringType(self):
+ return self.valueType == 'string' or self.valueType == 'stringArray' or self.valueType == 'stringArray2D'
+
+ def isArrayType(self):
+ return self.isArray() or self.isArray2D()
+
+ def isAcquisition(self):
+ return self.___type == self.___acquisitionRegisterType
+
+ def isSetting(self):
+ return self.___type == self.___settingRegisterType
+
+ def isVolatile(self):
+ return self.___type == self.___volatileRegisterType
+
+ def getCType(self):
+ return {
+ 'int8' :'int8_t',
+ 'uint8' :'uint8_t',
+ 'int16' :'int16_t',
+ 'uint16' :'uint16_t',
+ 'int32' :'int32_t',
+ 'uint32' :'uint32_t',
+ 'int64' :'int64_t',
+ 'uint64' :'uint64_t',
+ 'float32' :'float',
+ 'float64' :'double',
+ 'date' :'double',
+ 'char' :'int8_t',
+ 'byte' :'int16_t',
+ 'word' :'int32_t',
+ 'dword' :'int64_t',
+ 'int' :'int16_t',
+ 'dint' :'int32_t',
+ 'real' :'float',
+ 'dt' :'double',
+ 'string' :'std::string'
+ }[self.getSilecsDataType()]
+
+ #-------------------------------------------------------------------------
+ # Given PLC data type, returns the corresponding
+ # SILECS data type
+ #-------------------------------------------------------------------------
+ def getSilecsDataType(self):
+ return {
+ 'byte' :'uint8',
+ 'char' :'int8',
+ 'unsigned char' :'uint8',
+ 'short' :'int16',
+ 'unsigned short':'uint16',
+ 'long' :'int32', # conversion relies on 32-bit platform (FESA 3 does not support long type anymore)
+ 'unsigned long' :'uint32',
+ 'double' :'float64',
+ 'float' :'float32',
+ 'word' :'uint16',
+ 'dword' :'uint32',
+ 'int' :'int16',
+ 'dint' :'int32',
+ 'real' :'float32',
+ 'dt' :'date',
+ 'uint8' :'uint8',
+ 'int8' :'int8',
+ 'uint16' :'uint16',
+ 'int16' :'int16',
+ 'uint32' :'uint32',
+ 'int32' :'int32',
+ 'uint64' :'uint64',
+ 'int64' :'int64',
+ 'float32' :'float32',
+ 'float64' :'float64',
+ 'date' :'date',
+ 'string' : 'string'
+ }[self.format]
+
+ #Needed for SilecsMethodNames
+ def getSilecsDataTypeUpperCase(self):
+ silecsType = self.getSilecsDataType()
+ typeUpperCase = ""
+ if silecsType[0] == 'u':
+ typeUpperCase = silecsType[:2].upper() + silecsType[2:] # first two characters if unsigned
+ elif silecsType == 'date':
+ typeUpperCase = 'Date'
+ else:
+ typeUpperCase = silecsType[:1].upper() + silecsType[1:] # only first character if not unsigned
+ return typeUpperCase
+
+#has some additionalValues
+class ParamRegister(Register):
+ size = 0
+ address = 0
+ memSize = 0
+
+ def __init__(self ):
+ size = 0
+
+ def initWithParamRegisterNode(self, xmlNode):
+ super(ParamRegister, self).__init__(xmlNode)
+ self.size = long(self.xmlNode.prop("size"))
+ self.address = long(self.xmlNode.prop("address"))
+ self.memSize = long(self.xmlNode.prop("mem-size"))
+
+ def initWithDesignRegister(self, designRegister,size,address,memSize):
+ newNodeTree = designRegister.xmlNode.copyNode(1) # 1 is for recursive copy
+ if ( newNodeTree == None ):
+ iecommon.logError('ERROR: Failed to copy register node: '+ designRegister.name +'.', True, {'errorlog': True})
+ super(ParamRegister, self).__init__(designRegister.xmlNode)
+ self.xmlNode = newNodeTree
+ newNodeTree.newProp("size", size)
+ self.size = long(size)
+ newNodeTree.newProp("address", str(address))
+ self.address = address
+ newNodeTree.newProp("mem-size", str(memSize))
+ self.memSize = memSize
+ #self.xmlNode.shellPrintNode()
+
+ def setSize(self,size):
+ self.xmlNode.setProp("size", str(size))
+ self.size = size
+
+ def setAddress(self,address):
+ self.xmlNode.setProp("address", str(address))
+ self.address = address
+
+ def setMemSize(self,memSize):
+ self.xmlNode.setProp("mem-size", str(memSize))
+ self.memSize = memSize
+
+
+class DesignRegister(Register):
+ fesaFieldName = ""
+ generateFesaValueItem=True
+
+ def __init__(self, xmlNode):
+ super(DesignRegister, self).__init__(xmlNode)
+ self.fesaFieldName = self.name
+ if self.xmlNode.hasProp("fesaFieldName"):
+ self.fesaFieldName = xmlNode.prop("fesaFieldName")
+ if self.xmlNode.hasProp("generateFesaValueItem"): #SilecsHEader does not have this attribute
+ self.generateFesaValueItem = xsdBooleanToBoolean(xmlNode.prop("generateFesaValueItem"))
+
+ def getFesaFieldName(self):
+ return self.fesaFieldName
+
+ #-------------------------------------------------------------------------
+ # Given an SILECS data type, returns the corresponding FESA data type
+ # For the time being FESA does not support unsigned data types in properties
+ # so here unsigned types are considered as signed to allow users to link
+ # any field to properties
+ #-------------------------------------------------------------------------
+ def getFesaType(self):
+ return {
+ 'int8' :'int8_t',
+ 'uint8' :'int16_t',
+ 'int16' :'int16_t',
+ 'uint16' :'int32_t',
+ 'int32' :'int32_t',
+ 'uint32' :'int64_t',
+ 'int64' :'int64_t',
+ 'uint64' :'uint64_t', # only for PXI, but not supported from Java! Not possible to use it in FESA properties
+ 'float32' :'float',
+ 'float64' :'double',
+ 'date' :'double',
+ 'char' :'int8_t',
+ 'byte' :'int16_t',
+ 'word' :'int32_t',
+ 'dword' :'int64_t',
+ 'int' :'int16_t',
+ 'dint' :'int32_t',
+ 'real' :'float',
+ 'dt' :'double',
+ 'string' :'char'
+ }[self.getSilecsDataType()]
+
+ def getFesaFieldNameCapitalized(self):
+ return iecommon.capitalizeString(self.fesaFieldName)
+
+ def getFesaDataType(self,silecsDataType):
+ return {
+ 'int8' :'int8_t',
+ 'uint8' :'int16_t',
+ 'int16' :'int16_t',
+ 'uint16' :'int32_t',
+ 'int32' :'int32_t',
+ 'uint32' :'int64_t',
+ 'int64' :'int64_t',
+ 'uint64' :'uint64_t', # only for PXI, but not supported from Java! Not possible to use it in FESA properties
+ 'float32' :'float',
+ 'float64' :'double',
+ 'date' :'double',
+ 'char' :'int8_t',
+ 'byte' :'int16_t',
+ 'word' :'int32_t',
+ 'dword' :'int64_t',
+ 'int' :'int16_t',
+ 'dint' :'int32_t',
+ 'real' :'float',
+ 'dt' :'double',
+ 'string' :'char'
+ }[silecsDataType]
+
diff --git a/silecs-codegen/src/xml/model/__init__.py b/silecs-codegen/src/xml/model/__init__.py
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/silecs-codegen/src/xml/runTests.py b/silecs-codegen/src/xml/runTests.py
index 47bbe88348dfa4c4b7267c02f2f98674db761738..ed9aa0cc55a91dcd003e689bf01c82f2d333f905 100644
--- a/silecs-codegen/src/xml/runTests.py
+++ b/silecs-codegen/src/xml/runTests.py
@@ -29,6 +29,7 @@ import test.general.genParamTest
import test.general.genDuWrapperTest
def runTests():
+ migration.runTests.runAllTests()
test.fesa.fillFESADeployUnitTest.runTests()
test.fesa.generateFesaDesignTest.runTests()
test.fesa.generateSourceCodeTest.runTests()
@@ -36,7 +37,7 @@ def runTests():
test.general.genParamTest.runTests()
test.general.genplcsrcTest.runTests()
test.general.genDuWrapperTest.runTests()
- migration.runTests.runAllTests()
+
print "################################################"
print "# Test suite finished - no failures detected ! #"
diff --git a/silecs-codegen/src/xml/test/AllTypes.silecsdesign b/silecs-codegen/src/xml/test/AllTypes.silecsdesign
index a92fd2ebf58548789bc609f6a72e2d270bc80339..32e28db9ac963c8eb8fa7b1ecda2f270ac0050dd 100644
--- a/silecs-codegen/src/xml/test/AllTypes.silecsdesign
+++ b/silecs-codegen/src/xml/test/AllTypes.silecsdesign
@@ -1,77 +1,177 @@
<?xml version="1.0" encoding="UTF-8"?>
-<SILECS-Design silecs-version="0.10.0" created="06/27/16" updated="06/27/16"
- xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
- xsi:noNamespaceSchemaLocation="/common/home/bel/schwinn/lnx/workspace-silecs-mars/silecs-model/src/xml/DesignSchema.xsd">
- <Information>
- <Owner user-login="schwinn"/>
- <Editor user-login="schwinn"/>
- </Information>
- <SILECS-Class name="AllTypes" version="0.1.0" domain="OPERATIONAL" >
- <Block name="MyROBlock" mode="READ-ONLY" generateFesaProperty="true">
- <Register name="RO_int8" format="int8" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_uint8" format="uint8" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_int16" format="int16" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_uint16" format="uint16" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_int32" format="int32" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_uint32" format="uint32" synchro="MASTER" generateFesaValueItem="true" />
- <!--<Register name="RO_int64" format="int64" synchro="MASTER" generateFesaValueItem="true" /> not Supported for Beckhoff, Siemens and Schneider-->
- <!--<Register name="RO_uint64" format="uint64" synchro="MASTER" generateFesaValueItem="true" /> not Supported for Beckhoff, Siemens and Schneider-->
- <Register name="RO_float32" format="float32" synchro="MASTER" generateFesaValueItem="true" />
- <!--<Register name="RO_float64" format="float64" synchro="MASTER" generateFesaValueItem="true" /> not Supported for Rabbit, Beckhoff, Siemens and Schneider-->
- <Register name="RO_string" format="string" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_date" format="date" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_char" format="char" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_byte" format="byte" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_word" format="word" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_dword" format="dword" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_int" format="int" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_dint" format="dint" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_real" format="real" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_dt" format="dt" synchro="MASTER" generateFesaValueItem="true" />
- </Block>
- <Block name="MyRWBlock" generateFesaProperty="true" mode="READ-WRITE">
- <Register name="RW_int8" format="int8" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2" />
- <Register name="RW_uint8" format="uint8" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_int16" format="int16" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_uint16" format="uint16" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_int32" format="int32" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_uint32" format="uint32" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <!-- <Register name="RW_int64" format="int64" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/> not Supported for Beckhoff, Siemens and Schneider-->
- <!--<Register name="RW_uint64" format="uint64" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/> not Supported for Beckhoff, Siemens and Schneider-->
- <Register name="RW_float32" format="float32" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <!--<Register name="RW_float64" format="float64" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider-->
- <Register name="RW_string" format="string" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_date" format="date" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_char" format="char" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_byte" format="byte" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_word" format="word" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_dword" format="dword" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_int" format="int" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_dint" format="dint" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_real" format="real" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_dt" format="dt" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- </Block>
- <Block name="MyWOBlock" generateFesaProperty="true" mode="WRITE-ONLY">
- <Register name="WO_int8" format="int8" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_uint8" format="uint8" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_int16" format="int16" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_uint16" format="uint16" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_int32" format="int32" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_uint32" format="uint32" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <!--<Register name="WO_int64" format="int64" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/> not Supported for Beckhoff, Siemens and Schneider-->
- <!--<Register name="WO_uint64" format="uint64" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/> not Supported for Beckhoff, Siemens and Schneider-->
- <Register name="WO_float32" format="float32" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <!--<Register name="WO_float64" format="float64" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider-->
- <Register name="WO_string" format="string" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_date" format="date" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_char" format="char" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_byte" format="byte" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_word" format="word" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_dword" format="dword" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_int" format="int" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_dint" format="dint" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_real" format="real" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_dt" format="dt" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- </Block>
- </SILECS-Class>
+<SILECS-Design xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" silecs-version="2.0.0" created="06/27/16" updated="06/27/16" xsi:noNamespaceSchemaLocation="/common/home/bel/schwinn/lnx/git/silecs-model/src/xml/DesignSchema.xsd">
+ <Information>
+ <Owner user-login="schwinn"/>
+ <Editor user-login="schwinn"/>
+ </Information>
+ <SILECS-Class name="AllTypes" version="0.1.0" domain="OPERATIONAL">
+ <Acquisition-Block name="MyROBlock" generateFesaProperty="true" fesaPropertyName="MyROBlockProp">
+ <Acquisition-Register name="RO_int8" generateFesaValueItem="true">
+ <scalar format="int8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint8" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa">
+ <scalar format="uint8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int16" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa">
+ <scalar format="int16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint16" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa">
+ <scalar format="uint16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int32" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa">
+ <scalar format="int32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint32" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <!--<Register name="RO_int64" format="int64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int64_fesa"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <!--<Register name="RO_uint64" format="uint64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint64_fesa"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <Acquisition-Register name="RO_float32" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa">
+ <scalar format="float32"/>
+ </Acquisition-Register>
+ <!--<Register name="RO_float64" format="float64" synchro="MASTER" generateFesaValueItem="true" esaFieldName="RO_float64_fesa"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <Acquisition-Register name="RO_string" generateFesaValueItem="true" fesaFieldName="RO_string_fesa">
+ <string string-length="64" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_date" generateFesaValueItem="true" fesaFieldName="RO_date_fesa">
+ <scalar format="date"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_char" generateFesaValueItem="true" fesaFieldName="RO_char_fesa">
+ <scalar format="char"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_byte" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa">
+ <scalar format="byte"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_word" generateFesaValueItem="true" fesaFieldName="RO_word_fesa">
+ <scalar format="word"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dword" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa">
+ <scalar format="dword"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int" generateFesaValueItem="true" fesaFieldName="RO_int_fesa">
+ <scalar format="int"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dint" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa">
+ <scalar format="dint"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_real" generateFesaValueItem="true" fesaFieldName="RO_real_fesa">
+ <scalar format="real"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dt" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
+ <Setting-Block name="MyRWBlock" generateFesaProperty="true" fesaPropertyName="MyRWBlockProp">
+ <Volatile-Register name="RW_int8" generateFesaValueItem="true">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint8" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int16" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint16" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int32" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint32" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Volatile-Register>
+ <!--<Register name="RW_int64" format="int64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int64_fesa" array-dim1="2" array-dim2="2"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <!--<Register name="RW_uint64" format="uint64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint64_fesa" array-dim1="2" array-dim2="2"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <Volatile-Register name="RW_float32" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Volatile-Register>
+ <!--<Register name="RW_float64" format="float64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float64_fesa" array-dim1="2" array-dim2="2"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <Volatile-Register name="RW_string" generateFesaValueItem="true" fesaFieldName="RW_string_fesa">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_date" generateFesaValueItem="true" fesaFieldName="RW_date_fesa">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_char" generateFesaValueItem="true" fesaFieldName="RW_char_fesa">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_byte" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_word" generateFesaValueItem="true" fesaFieldName="RW_word_fesa">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dword" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int" generateFesaValueItem="true" fesaFieldName="RW_int_fesa">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dint" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_real" generateFesaValueItem="true" fesaFieldName="RW_real_fesa">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dt" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Volatile-Register>
+ </Setting-Block>
+ <Command-Block name="MyWOBlock" generateFesaProperty="true" fesaPropertyName="MyWOBlockProp">
+ <Setting-Register name="WO_int8" generateFesaValueItem="true">
+ <array dim="10" format="int8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint8" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa">
+ <array dim="10" format="uint8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int16" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa">
+ <array dim="10" format="int16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint16" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa">
+ <array dim="10" format="uint16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int32" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa">
+ <array dim="10" format="int32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint32" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa">
+ <array dim="10" format="uint32"/>
+ </Setting-Register>
+ <!--<Register name="WO_int64" format="int64" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int64_fesa" array-dim1="10"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <!--<Register name="WO_uint64" format="uint64" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint64_fesa" array-dim1="10"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <Setting-Register name="WO_float32" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa">
+ <array dim="10" format="float32"/>
+ </Setting-Register>
+ <!--<Register name="WO_float64" format="float64" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float64_fesa" array-dim1="10"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <Setting-Register name="WO_string" generateFesaValueItem="true" fesaFieldName="WO_string_fesa">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Setting-Register>
+ <Setting-Register name="WO_date" generateFesaValueItem="true" fesaFieldName="WO_date_fesa">
+ <array dim="10" format="date"/>
+ </Setting-Register>
+ <Setting-Register name="WO_char" generateFesaValueItem="true" fesaFieldName="WO_char_fesa">
+ <array dim="10" format="char"/>
+ </Setting-Register>
+ <Setting-Register name="WO_byte" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa">
+ <array dim="10" format="byte"/>
+ </Setting-Register>
+ <Setting-Register name="WO_word" generateFesaValueItem="true" fesaFieldName="WO_word_fesa">
+ <array dim="10" format="word"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dword" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa">
+ <array dim="10" format="dword"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int" generateFesaValueItem="true" fesaFieldName="WO_int_fesa">
+ <array dim="10" format="int"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dint" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa">
+ <array dim="10" format="dint"/>
+ </Setting-Register>
+ <Setting-Register name="WO_real" generateFesaValueItem="true" fesaFieldName="WO_real_fesa">
+ <array dim="10" format="real"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dt" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa">
+ <array dim="10" format="dt"/>
+ </Setting-Register>
+ </Command-Block>
+ </SILECS-Class>
</SILECS-Design>
diff --git a/silecs-codegen/src/xml/test/AllTypesDU.silecsdeploy b/silecs-codegen/src/xml/test/AllTypesDU.silecsdeploy
index 67fe6fc6f201f4cbf09ae9158321ddb6b7eb52ba..871b51c97d85c733a48c700ab5983377ccc8247b 100644
--- a/silecs-codegen/src/xml/test/AllTypesDU.silecsdeploy
+++ b/silecs-codegen/src/xml/test/AllTypesDU.silecsdeploy
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
-<SILECS-Deploy silecs-version="0.10.0" created="06/27/16" updated="06/27/16"
+<SILECS-Deploy silecs-version="2.0.0" created="06/27/16" updated="06/27/16"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
- xsi:noNamespaceSchemaLocation="/common/home/bel/schwinn/lnx/workspace-silecs-mars/silecs-model/src/xml/DeploySchema.xsd">
+ xsi:noNamespaceSchemaLocation="/common/home/bel/schwinn/lnx/git/silecs-model/src/xml/DeploySchema.xsd">
<Information>
<Owner user-login="schwinn"/>
<Editor user-login="schwinn"/>
diff --git a/silecs-codegen/src/xml/test/AllTypesFESA.silecsdesign b/silecs-codegen/src/xml/test/AllTypesFESA.silecsdesign
index 01c9edf3530200b4dbf73506c9c5662845633003..219be566a846587d4828fd99621b4c80879c253d 100644
--- a/silecs-codegen/src/xml/test/AllTypesFESA.silecsdesign
+++ b/silecs-codegen/src/xml/test/AllTypesFESA.silecsdesign
@@ -1,77 +1,175 @@
<?xml version="1.0" encoding="UTF-8"?>
-<SILECS-Design silecs-version="0.10.0" created="06/27/16" updated="06/27/16"
- xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
- xsi:noNamespaceSchemaLocation="/common/home/bel/schwinn/lnx/workspace-silecs-mars/silecs-model/src/xml/DesignSchema.xsd">
- <Information>
- <Owner user-login="schwinn"/>
- <Editor user-login="schwinn"/>
- </Information>
- <SILECS-Class name="AllTypesFESA" version="0.1.0" domain="OPERATIONAL" >
- <Block name="MyROBlock" mode="READ-ONLY" generateFesaProperty="true">
- <Register name="RO_int8" format="int8" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_uint8" format="uint8" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_int16" format="int16" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_uint16" format="uint16" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_int32" format="int32" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_uint32" format="uint32" synchro="MASTER" generateFesaValueItem="true" />
- <!--<Register name="RO_int64" format="int64" synchro="MASTER" generateFesaValueItem="true" /> not Supported for Beckhoff, Siemens and Schneider-->
- <!--<Register name="RO_uint64" format="uint64" synchro="MASTER" generateFesaValueItem="true" /> not Supported for Beckhoff, Siemens and Schneider-->
- <Register name="RO_float32" format="float32" synchro="MASTER" generateFesaValueItem="true" />
- <!--<Register name="RO_float64" format="float64" synchro="MASTER" generateFesaValueItem="true" /> not Supported for Rabbit, Beckhoff, Siemens and Schneider-->
- <Register name="RO_string" format="string" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_date" format="date" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_char" format="char" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_byte" format="byte" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_word" format="word" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_dword" format="dword" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_int" format="int" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_dint" format="dint" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_real" format="real" synchro="MASTER" generateFesaValueItem="true" />
- <Register name="RO_dt" format="dt" synchro="MASTER" generateFesaValueItem="true" />
- </Block>
- <Block name="MyRWBlock" generateFesaProperty="true" mode="READ-WRITE">
- <Register name="RW_int8" format="int8" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2" />
- <Register name="RW_uint8" format="uint8" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_int16" format="int16" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_uint16" format="uint16" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_int32" format="int32" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_uint32" format="uint32" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <!-- <Register name="RW_int64" format="int64" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/> not Supported for Beckhoff, Siemens and Schneider-->
- <!--<Register name="RW_uint64" format="uint64" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/> not Supported for Beckhoff, Siemens and Schneider-->
- <Register name="RW_float32" format="float32" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <!--<Register name="RW_float64" format="float64" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider-->
- <!-- <Register name="RW_string" format="string" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/> 2d string arrays not supported in FESA -->
- <Register name="RW_date" format="date" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_char" format="char" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_byte" format="byte" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_word" format="word" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_dword" format="dword" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_int" format="int" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_dint" format="dint" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_real" format="real" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- <Register name="RW_dt" format="dt" synchro="MASTER" generateFesaValueItem="true" array-dim1="2" array-dim2="2"/>
- </Block>
- <Block name="MyWOBlock" generateFesaProperty="true" mode="WRITE-ONLY">
- <Register name="WO_int8" format="int8" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_uint8" format="uint8" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_int16" format="int16" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_uint16" format="uint16" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_int32" format="int32" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_uint32" format="uint32" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <!--<Register name="WO_int64" format="int64" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/> not Supported for Beckhoff, Siemens and Schneider-->
- <!--<Register name="WO_uint64" format="uint64" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/> not Supported for Beckhoff, Siemens and Schneider-->
- <Register name="WO_float32" format="float32" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <!--<Register name="WO_float64" format="float64" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider-->
- <Register name="WO_string" format="string" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_date" format="date" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_char" format="char" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_byte" format="byte" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_word" format="word" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_dword" format="dword" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_int" format="int" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_dint" format="dint" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_real" format="real" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- <Register name="WO_dt" format="dt" synchro="SLAVE" generateFesaValueItem="true" array-dim1="10"/>
- </Block>
- </SILECS-Class>
+<SILECS-Design xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" silecs-version="2.0.0" created="06/27/16" updated="06/27/16" xsi:noNamespaceSchemaLocation="/common/home/bel/schwinn/lnx/git/silecs-model/src/xml/DesignSchema.xsd">
+ <Information>
+ <Owner user-login="schwinn"/>
+ <Editor user-login="schwinn"/>
+ </Information>
+ <SILECS-Class name="AllTypesFESA" version="0.1.0" domain="OPERATIONAL">
+ <Acquisition-Block name="MyROBlock" generateFesaProperty="true" fesaPropertyName="MyROBlockProp">
+ <Acquisition-Register name="RO_int8" generateFesaValueItem="true">
+ <scalar format="int8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint8" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa">
+ <scalar format="uint8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int16" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa">
+ <scalar format="int16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint16" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa">
+ <scalar format="uint16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int32" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa">
+ <scalar format="int32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint32" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <!--<Register name="RO_int64" format="int64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_int64_fesa"/> not Supported for Beckhoff, Siemens and Schneider -->
+ <!--<Register name="RO_uint64" format="uint64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RO_uint64_fesa"/> not Supported for Beckhoff, Siemens and Schneider -->
+ <Acquisition-Register name="RO_float32" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa">
+ <scalar format="float32"/>
+ </Acquisition-Register>
+ <!--<Register name="RO_float64" format="float64" synchro="MASTER" generateFesaValueItem="true" esaFieldName="RO_float64_fesa"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <Acquisition-Register name="RO_string" generateFesaValueItem="true" fesaFieldName="RO_string_fesa">
+ <string string-length="64" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_date" generateFesaValueItem="true" fesaFieldName="RO_date_fesa">
+ <scalar format="date"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_char" generateFesaValueItem="true" fesaFieldName="RO_char_fesa">
+ <scalar format="char"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_byte" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa">
+ <scalar format="byte"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_word" generateFesaValueItem="true" fesaFieldName="RO_word_fesa">
+ <scalar format="word"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dword" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa">
+ <scalar format="dword"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int" generateFesaValueItem="true" fesaFieldName="RO_int_fesa">
+ <scalar format="int"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dint" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa">
+ <scalar format="dint"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_real" generateFesaValueItem="true" fesaFieldName="RO_real_fesa">
+ <scalar format="real"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dt" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
+ <Setting-Block name="MyRWBlock" generateFesaProperty="true" fesaPropertyName="MyRWBlockProp">
+ <Volatile-Register name="RW_int8" generateFesaValueItem="true">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint8" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int16" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint16" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int32" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint32" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Volatile-Register>
+ <!-- <Register name="RW_int64" format="int64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_int64_fesa" array-dim1="2" array-dim2="2"/> not Supported for Beckhoff, Siemens and Schneider -->
+ <!--<Register name="RW_uint64" format="uint64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_uint64_fesa" array-dim1="2" array-dim2="2"/> not Supported for Beckhoff, Siemens and Schneider -->
+ <Volatile-Register name="RW_float32" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Volatile-Register>
+ <!--<Register name="RW_float64" format="float64" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_float64_fesa" array-dim1="2" array-dim2="2"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <!-- <Register name="RW_string" format="string" synchro="MASTER" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" array-dim1="2" array-dim2="2"/> 2d string arrays not supported in FESA -->
+ <Volatile-Register name="RW_date" generateFesaValueItem="true" fesaFieldName="RW_date_fesa">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_char" generateFesaValueItem="true" fesaFieldName="RW_char_fesa">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_byte" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_word" generateFesaValueItem="true" fesaFieldName="RW_word_fesa">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dword" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int" generateFesaValueItem="true" fesaFieldName="RW_int_fesa">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dint" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_real" generateFesaValueItem="true" fesaFieldName="RW_real_fesa">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dt" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Volatile-Register>
+ </Setting-Block>
+ <Command-Block name="MyWOBlock" generateFesaProperty="true" fesaPropertyName="MyWOBlockProp">
+ <Setting-Register name="WO_int8" generateFesaValueItem="true">
+ <array dim="10" format="int8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint8" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa">
+ <array dim="10" format="uint8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int16" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa">
+ <array dim="10" format="int16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint16" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa">
+ <array dim="10" format="uint16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int32" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa">
+ <array dim="10" format="int32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint32" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa">
+ <array dim="10" format="uint32"/>
+ </Setting-Register>
+ <!--<Register name="WO_int64" format="int64" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_int64_fesa" array-dim1="10"/> not Supported for Beckhoff, Siemens and Schneider -->
+ <!--<Register name="WO_uint64" format="uint64" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_uint64_fesa" array-dim1="10"/> not Supported for Beckhoff, Siemens and Schneider -->
+ <Setting-Register name="WO_float32" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa">
+ <array dim="10" format="float32"/>
+ </Setting-Register>
+ <!--<Register name="WO_float64" format="float64" synchro="SLAVE" generateFesaValueItem="true" fesaFieldName="WO_float64_fesa" array-dim1="10"/> not Supported for Rabbit, Beckhoff, Siemens and Schneider -->
+ <Setting-Register name="WO_string" generateFesaValueItem="true" fesaFieldName="WO_string_fesa">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Setting-Register>
+ <Setting-Register name="WO_date" generateFesaValueItem="true" fesaFieldName="WO_date_fesa">
+ <array dim="10" format="date"/>
+ </Setting-Register>
+ <Setting-Register name="WO_char" generateFesaValueItem="true" fesaFieldName="WO_char_fesa">
+ <array dim="10" format="char"/>
+ </Setting-Register>
+ <Setting-Register name="WO_byte" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa">
+ <array dim="10" format="byte"/>
+ </Setting-Register>
+ <Setting-Register name="WO_word" generateFesaValueItem="true" fesaFieldName="WO_word_fesa">
+ <array dim="10" format="word"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dword" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa">
+ <array dim="10" format="dword"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int" generateFesaValueItem="true" fesaFieldName="WO_int_fesa">
+ <array dim="10" format="int"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dint" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa">
+ <array dim="10" format="dint"/>
+ </Setting-Register>
+ <Setting-Register name="WO_real" generateFesaValueItem="true" fesaFieldName="WO_real_fesa">
+ <array dim="10" format="real"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dt" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa">
+ <array dim="10" format="dt"/>
+ </Setting-Register>
+ </Command-Block>
+ </SILECS-Class>
</SILECS-Design>
diff --git a/silecs-codegen/src/xml/test/fesa/generateFesaDesignTest.py b/silecs-codegen/src/xml/test/fesa/generateFesaDesignTest.py
index 1118df7f428f2b5715632c460e1f3964e2fe40b2..e995f16f382bc531fb612ca642e3c9c16e36b733 100644
--- a/silecs-codegen/src/xml/test/fesa/generateFesaDesignTest.py
+++ b/silecs-codegen/src/xml/test/fesa/generateFesaDesignTest.py
@@ -31,12 +31,16 @@ simpleSilecsDesign = '''<?xml version="1.0" encoding="UTF-8"?>
<Editor user-login="schwinn"/>
</Information>
<SILECS-Class name="Test123" version="0.1.0" domain="OPERATIONAL">
- <Block name="Setting" mode="READ-WRITE" generateFesaProperty="true">
- <Register name="mySettingRegister" format="uint8" synchro="MASTER" generateFesaValueItem="true"/>
- </Block>
- <Block name="Acquisition" mode="READ-ONLY" generateFesaProperty="true">
- <Register name="myAcqRegister" format="uint8" synchro="MASTER" generateFesaValueItem="true"/>
- </Block>
+ <Setting-Block name="Setting" generateFesaProperty="true">
+ <Setting-Register name="mySettingRegister" generateFesaValueItem="true">
+ <scalar format="uint8"/>
+ </Setting-Register>
+ </Setting-Block>
+ <Acquisition-Block name="Acquisition" generateFesaProperty="true">
+ <Acquisition-Register name="myAcqRegister" generateFesaValueItem="true">
+ <scalar format="uint8"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
</SILECS-Class>
</SILECS-Design>'''
simpleSilecsDesignRoot = libxml2.parseDoc(simpleSilecsDesign)
@@ -51,6 +55,7 @@ def testFillXML_EmptyTemplate_3_0_0(generator):
def testFillXML_GSITemplate_3_0_0(generator):
fesaRoot = libxml2.parseFile("test/fesa/GSIClassTemplateFESA300.xml")
generator.fillXML('3.0.0', 'MyClass', fesaRoot,simpleSilecsDesignRoot,logTopics={'errorlog': True})
+
assertTrue( fesaRoot.xpathEval('/equipment-model/events') != None )
assertTrue( fesaRoot.xpathEval('/equipment-model/scheduling-units') != None )
@@ -58,6 +63,7 @@ def testFillXML_GSITemplate_3_0_0(generator):
firstGSIAcqProp = acquisition.xpathEval('GSI-Acquisition-Property')[0]
assertTrue( acquisition.xpathEval('*')[0].prop('name') != firstGSIAcqProp.prop('name') ) # check if generated at right position
assertEqual( firstGSIAcqProp.prop('name'),"Acquisition" )
+ firstGSIAcqProp.shellPrintNode() #for debug
valueItem = firstGSIAcqProp.xpathEval('value-item')[0]
assertTrue( valueItem != None )
diff --git a/silecs-codegen/src/xml/test/generated_correct/AllTypes.cpp b/silecs-codegen/src/xml/test/generated_correct/AllTypes.cpp
index 08c4d7fdeb2770c38e2a0a86015a931c653292a8..40f7be43107bd54649a792b8515c9e16aaf3035b 100644
--- a/silecs-codegen/src/xml/test/generated_correct/AllTypes.cpp
+++ b/silecs-codegen/src/xml/test/generated_correct/AllTypes.cpp
@@ -98,6 +98,7 @@ namespace AllTypes
{
fesa::NoneContext noneContext;
+ AllTypes::MyRWBlock.setPLCDevices(pPLC, serviceLocator, false, &noneContext);
AllTypes::MyWOBlock.setPLCDevices(pPLC, serviceLocator, false, &noneContext);
}
@@ -191,30 +192,32 @@ namespace AllTypes
}
Silecs::PLC* pPLC = pCluster_->getPLC(pDevice->plcHostName.get(),pDevice->parameterFile.get());
Silecs::Device* pPLCDevice = pPLC->getDevice(pDevice->plcDeviceLabel.get());
- Silecs::Register* pRegister = NULL;
if (recvNow) pPLCDevice -> recv(blockName_);
pDevice->RO_int8.set( pPLCDevice->getRegister("RO_int8")->getValInt8(), pContext);
- pDevice->RO_uint8.set( pPLCDevice->getRegister("RO_uint8")->getValUInt8(), pContext);
- pDevice->RO_int16.set( pPLCDevice->getRegister("RO_int16")->getValInt16(), pContext);
- pDevice->RO_uint16.set( pPLCDevice->getRegister("RO_uint16")->getValUInt16(), pContext);
- pDevice->RO_int32.set( pPLCDevice->getRegister("RO_int32")->getValInt32(), pContext);
- pDevice->RO_uint32.set( pPLCDevice->getRegister("RO_uint32")->getValUInt32(), pContext);
- pDevice->RO_float32.set( pPLCDevice->getRegister("RO_float32")->getValFloat32(), pContext);
- pRegister = pPLCDevice->getRegister("RO_string");
- pDevice->RO_string.set(pRegister->getValString().c_str(), pContext);
-
- pDevice->RO_date.set( pPLCDevice->getRegister("RO_date")->getValDate(), pContext);
- pDevice->RO_char.set( pPLCDevice->getRegister("RO_char")->getValInt8(), pContext);
- pDevice->RO_byte.set( pPLCDevice->getRegister("RO_byte")->getValUInt8(), pContext);
- pDevice->RO_word.set( pPLCDevice->getRegister("RO_word")->getValUInt16(), pContext);
- pDevice->RO_dword.set( pPLCDevice->getRegister("RO_dword")->getValUInt32(), pContext);
- pDevice->RO_int.set( pPLCDevice->getRegister("RO_int")->getValInt16(), pContext);
- pDevice->RO_dint.set( pPLCDevice->getRegister("RO_dint")->getValInt32(), pContext);
- pDevice->RO_real.set( pPLCDevice->getRegister("RO_real")->getValFloat32(), pContext);
- pDevice->RO_dt.set( pPLCDevice->getRegister("RO_dt")->getValDate(), pContext);
- }
+ pDevice->RO_uint8_fesa.set( pPLCDevice->getRegister("RO_uint8")->getValUInt8(), pContext);
+ pDevice->RO_int16_fesa.set( pPLCDevice->getRegister("RO_int16")->getValInt16(), pContext);
+ pDevice->RO_uint16_fesa.set( pPLCDevice->getRegister("RO_uint16")->getValUInt16(), pContext);
+ pDevice->RO_int32_fesa.set( pPLCDevice->getRegister("RO_int32")->getValInt32(), pContext);
+ pDevice->RO_uint32_fesa.set( pPLCDevice->getRegister("RO_uint32")->getValUInt32(), pContext);
+ pDevice->RO_float32_fesa.set( pPLCDevice->getRegister("RO_float32")->getValFloat32(), pContext);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RO_string");
+ pDevice->RO_string_fesa.set(pRegister->getValString().c_str(), pContext);
+ }
+
+ pDevice->RO_date_fesa.set( pPLCDevice->getRegister("RO_date")->getValDate(), pContext);
+ pDevice->RO_char_fesa.set( pPLCDevice->getRegister("RO_char")->getValInt8(), pContext);
+ pDevice->RO_byte_fesa.set( pPLCDevice->getRegister("RO_byte")->getValUInt8(), pContext);
+ pDevice->RO_word_fesa.set( pPLCDevice->getRegister("RO_word")->getValUInt16(), pContext);
+ pDevice->RO_dword_fesa.set( pPLCDevice->getRegister("RO_dword")->getValUInt32(), pContext);
+ pDevice->RO_int_fesa.set( pPLCDevice->getRegister("RO_int")->getValInt16(), pContext);
+ pDevice->RO_dint_fesa.set( pPLCDevice->getRegister("RO_dint")->getValInt32(), pContext);
+ pDevice->RO_real_fesa.set( pPLCDevice->getRegister("RO_real")->getValFloat32(), pContext);
+ pDevice->RO_dt_fesa.set( pPLCDevice->getRegister("RO_dt")->getValDate(), pContext);
+ }
+
void MyRWBlock_Type::getOneDevice(Device* pDevice, const bool recvNow, MultiplexingContext* pContext)
{
if( !isInitialized_ )
@@ -223,111 +226,141 @@ namespace AllTypes
}
Silecs::PLC* pPLC = pCluster_->getPLC(pDevice->plcHostName.get(),pDevice->parameterFile.get());
Silecs::Device* pPLCDevice = pPLC->getDevice(pDevice->plcDeviceLabel.get());
- Silecs::Register* pRegister = NULL;
- uint32_t dim1 = 1;
- uint32_t dim2 = 1;
if (recvNow) pPLCDevice -> recv(blockName_);
- pRegister = pPLCDevice->getRegister("RW_int8");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pDevice->RW_int8.set(pRegister->getRefInt8Array2D(dim1, dim2), dim1, dim2, pContext);
-
- pRegister = pPLCDevice->getRegister("RW_uint8");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- int16_t* RW_uint8 = (int16_t*)calloc(dim1*dim2, sizeof(int16_t));
- pRegister->getValUInt8Array2D(RW_uint8, dim1, dim2); //use automatic conversion for JAVA non-supported type
- pDevice->RW_uint8.set(RW_uint8, dim1, dim2, pContext);
- free(RW_uint8);
-
- pRegister = pPLCDevice->getRegister("RW_int16");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pDevice->RW_int16.set(pRegister->getRefInt16Array2D(dim1, dim2), dim1, dim2, pContext);
-
- pRegister = pPLCDevice->getRegister("RW_uint16");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- int32_t* RW_uint16 = (int32_t*)calloc(dim1*dim2, sizeof(int32_t));
- pRegister->getValUInt16Array2D(RW_uint16, dim1, dim2); //use automatic conversion for JAVA non-supported type
- pDevice->RW_uint16.set(RW_uint16, dim1, dim2, pContext);
- free(RW_uint16);
-
- pRegister = pPLCDevice->getRegister("RW_int32");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pDevice->RW_int32.set(pRegister->getRefInt32Array2D(dim1, dim2), dim1, dim2, pContext);
-
- pRegister = pPLCDevice->getRegister("RW_uint32");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- int64_t* RW_uint32 = (int64_t*)calloc(dim1*dim2, sizeof(int64_t));
- pRegister->getValUInt32Array2D(RW_uint32, dim1, dim2); //use automatic conversion for JAVA non-supported type
- pDevice->RW_uint32.set(RW_uint32, dim1, dim2, pContext);
- free(RW_uint32);
-
- pRegister = pPLCDevice->getRegister("RW_float32");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pDevice->RW_float32.set(pRegister->getRefFloat32Array2D(dim1, dim2), dim1, dim2, pContext);
-
- pRegister = pPLCDevice->getRegister("RW_date");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pDevice->RW_date.set(pRegister->getRefDateArray2D(dim1, dim2), dim1, dim2, pContext);
-
- pRegister = pPLCDevice->getRegister("RW_char");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pDevice->RW_char.set(pRegister->getRefInt8Array2D(dim1, dim2), dim1, dim2, pContext);
-
- pRegister = pPLCDevice->getRegister("RW_byte");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- int16_t* RW_byte = (int16_t*)calloc(dim1*dim2, sizeof(int16_t));
- pRegister->getValUInt8Array2D(RW_byte, dim1, dim2); //use automatic conversion for JAVA non-supported type
- pDevice->RW_byte.set(RW_byte, dim1, dim2, pContext);
- free(RW_byte);
-
- pRegister = pPLCDevice->getRegister("RW_word");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- int32_t* RW_word = (int32_t*)calloc(dim1*dim2, sizeof(int32_t));
- pRegister->getValUInt16Array2D(RW_word, dim1, dim2); //use automatic conversion for JAVA non-supported type
- pDevice->RW_word.set(RW_word, dim1, dim2, pContext);
- free(RW_word);
-
- pRegister = pPLCDevice->getRegister("RW_dword");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- int64_t* RW_dword = (int64_t*)calloc(dim1*dim2, sizeof(int64_t));
- pRegister->getValUInt32Array2D(RW_dword, dim1, dim2); //use automatic conversion for JAVA non-supported type
- pDevice->RW_dword.set(RW_dword, dim1, dim2, pContext);
- free(RW_dword);
-
- pRegister = pPLCDevice->getRegister("RW_int");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pDevice->RW_int.set(pRegister->getRefInt16Array2D(dim1, dim2), dim1, dim2, pContext);
-
- pRegister = pPLCDevice->getRegister("RW_dint");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pDevice->RW_dint.set(pRegister->getRefInt32Array2D(dim1, dim2), dim1, dim2, pContext);
-
- pRegister = pPLCDevice->getRegister("RW_real");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pDevice->RW_real.set(pRegister->getRefFloat32Array2D(dim1, dim2), dim1, dim2, pContext);
-
- pRegister = pPLCDevice->getRegister("RW_dt");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pDevice->RW_dt.set(pRegister->getRefDateArray2D(dim1, dim2), dim1, dim2, pContext);
-
- }
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_int8");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ pDevice->RW_int8.set(pRegister->getRefInt8Array2D(dim1, dim2), dim1, dim2, pContext);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_uint8");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ int16_t* RW_uint8 = (int16_t*)calloc(dim1*dim2, sizeof(int16_t));
+ pRegister->getValUInt8Array2D(RW_uint8, dim1, dim2); //use automatic conversion for JAVA non-supported type
+ pDevice->RW_uint8_fesa.set(RW_uint8, dim1, dim2, pContext);
+ free(RW_uint8);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_int16");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ pDevice->RW_int16_fesa.set(pRegister->getRefInt16Array2D(dim1, dim2), dim1, dim2, pContext);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_uint16");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ int32_t* RW_uint16 = (int32_t*)calloc(dim1*dim2, sizeof(int32_t));
+ pRegister->getValUInt16Array2D(RW_uint16, dim1, dim2); //use automatic conversion for JAVA non-supported type
+ pDevice->RW_uint16_fesa.set(RW_uint16, dim1, dim2, pContext);
+ free(RW_uint16);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_int32");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ pDevice->RW_int32_fesa.set(pRegister->getRefInt32Array2D(dim1, dim2), dim1, dim2, pContext);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_uint32");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ int64_t* RW_uint32 = (int64_t*)calloc(dim1*dim2, sizeof(int64_t));
+ pRegister->getValUInt32Array2D(RW_uint32, dim1, dim2); //use automatic conversion for JAVA non-supported type
+ pDevice->RW_uint32_fesa.set(RW_uint32, dim1, dim2, pContext);
+ free(RW_uint32);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_float32");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ pDevice->RW_float32_fesa.set(pRegister->getRefFloat32Array2D(dim1, dim2), dim1, dim2, pContext);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_date");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ pDevice->RW_date_fesa.set(pRegister->getRefDateArray2D(dim1, dim2), dim1, dim2, pContext);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_char");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ pDevice->RW_char_fesa.set(pRegister->getRefInt8Array2D(dim1, dim2), dim1, dim2, pContext);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_byte");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ int16_t* RW_byte = (int16_t*)calloc(dim1*dim2, sizeof(int16_t));
+ pRegister->getValUInt8Array2D(RW_byte, dim1, dim2); //use automatic conversion for JAVA non-supported type
+ pDevice->RW_byte_fesa.set(RW_byte, dim1, dim2, pContext);
+ free(RW_byte);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_word");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ int32_t* RW_word = (int32_t*)calloc(dim1*dim2, sizeof(int32_t));
+ pRegister->getValUInt16Array2D(RW_word, dim1, dim2); //use automatic conversion for JAVA non-supported type
+ pDevice->RW_word_fesa.set(RW_word, dim1, dim2, pContext);
+ free(RW_word);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_dword");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ int64_t* RW_dword = (int64_t*)calloc(dim1*dim2, sizeof(int64_t));
+ pRegister->getValUInt32Array2D(RW_dword, dim1, dim2); //use automatic conversion for JAVA non-supported type
+ pDevice->RW_dword_fesa.set(RW_dword, dim1, dim2, pContext);
+ free(RW_dword);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_int");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ pDevice->RW_int_fesa.set(pRegister->getRefInt16Array2D(dim1, dim2), dim1, dim2, pContext);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_dint");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ pDevice->RW_dint_fesa.set(pRegister->getRefInt32Array2D(dim1, dim2), dim1, dim2, pContext);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_real");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ pDevice->RW_real_fesa.set(pRegister->getRefFloat32Array2D(dim1, dim2), dim1, dim2, pContext);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_dt");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ pDevice->RW_dt_fesa.set(pRegister->getRefDateArray2D(dim1, dim2), dim1, dim2, pContext);
+ }
+
+ }
+
void MyRWBlock_Type::setOneDevice(Device* pDevice, const bool sendNow, MultiplexingContext* pContext)
{
if( !isInitialized_ )
@@ -336,97 +369,139 @@ namespace AllTypes
}
Silecs::PLC* pPLC = pCluster_->getPLC(pDevice->plcHostName.get(),pDevice->parameterFile.get());
Silecs::Device* pPLCDevice = pPLC->getDevice(pDevice->plcDeviceLabel.get());
- Silecs::Register* pRegister = NULL;
- uint32_t dim1 = 1;
- uint32_t fesaDim1;
- uint32_t dim2 = 1;
- uint32_t fesaDim2;
-
-
- pRegister = pPLCDevice->getRegister("RW_int8");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pRegister->setValInt8Array2D(pDevice->RW_int8.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_uint8");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pRegister->setValUInt8Array2D( pDevice->RW_uint8.get(fesaDim1, fesaDim2, pContext), dim1, dim2); //use automatic conversion for JAVA non-supported type
-
- pRegister = pPLCDevice->getRegister("RW_int16");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pRegister->setValInt16Array2D(pDevice->RW_int16.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_uint16");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pRegister->setValUInt16Array2D( pDevice->RW_uint16.get(fesaDim1, fesaDim2, pContext), dim1, dim2); //use automatic conversion for JAVA non-supported type
-
- pRegister = pPLCDevice->getRegister("RW_int32");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pRegister->setValInt32Array2D(pDevice->RW_int32.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_uint32");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pRegister->setValUInt32Array2D( pDevice->RW_uint32.get(fesaDim1, fesaDim2, pContext), dim1, dim2); //use automatic conversion for JAVA non-supported type
-
- pRegister = pPLCDevice->getRegister("RW_float32");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pRegister->setValFloat32Array2D(pDevice->RW_float32.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_date");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pRegister->setValDateArray2D(pDevice->RW_date.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_char");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pRegister->setValInt8Array2D(pDevice->RW_char.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_byte");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pRegister->setValUInt8Array2D( pDevice->RW_byte.get(fesaDim1, fesaDim2, pContext), dim1, dim2); //use automatic conversion for JAVA non-supported type
-
- pRegister = pPLCDevice->getRegister("RW_word");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pRegister->setValUInt16Array2D( pDevice->RW_word.get(fesaDim1, fesaDim2, pContext), dim1, dim2); //use automatic conversion for JAVA non-supported type
-
- pRegister = pPLCDevice->getRegister("RW_dword");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pRegister->setValUInt32Array2D( pDevice->RW_dword.get(fesaDim1, fesaDim2, pContext), dim1, dim2); //use automatic conversion for JAVA non-supported type
-
- pRegister = pPLCDevice->getRegister("RW_int");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pRegister->setValInt16Array2D(pDevice->RW_int.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_dint");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pRegister->setValInt32Array2D(pDevice->RW_dint.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_real");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pRegister->setValFloat32Array2D(pDevice->RW_real.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_dt");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- pRegister->setValDateArray2D(pDevice->RW_dt.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_int8");
+ uint32_t dim1 = pRegister->getDimension1();
+ dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ pRegister->setValInt8Array2D(pDevice->RW_int8.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_uint8");
+ uint32_t dim1 = pRegister->getDimension1();
+ dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ pRegister->setValUInt8Array2D( pDevice->RW_uint8_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2); //use automatic conversion for JAVA non-supported type
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_int16");
+ uint32_t dim1 = pRegister->getDimension1();
+ dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ pRegister->setValInt16Array2D(pDevice->RW_int16_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_uint16");
+ uint32_t dim1 = pRegister->getDimension1();
+ dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ pRegister->setValUInt16Array2D( pDevice->RW_uint16_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2); //use automatic conversion for JAVA non-supported type
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_int32");
+ uint32_t dim1 = pRegister->getDimension1();
+ dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ pRegister->setValInt32Array2D(pDevice->RW_int32_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_uint32");
+ uint32_t dim1 = pRegister->getDimension1();
+ dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ pRegister->setValUInt32Array2D( pDevice->RW_uint32_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2); //use automatic conversion for JAVA non-supported type
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_float32");
+ uint32_t dim1 = pRegister->getDimension1();
+ dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ pRegister->setValFloat32Array2D(pDevice->RW_float32_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_date");
+ uint32_t dim1 = pRegister->getDimension1();
+ dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ pRegister->setValDateArray2D(pDevice->RW_date_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_char");
+ uint32_t dim1 = pRegister->getDimension1();
+ dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ pRegister->setValInt8Array2D(pDevice->RW_char_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_byte");
+ uint32_t dim1 = pRegister->getDimension1();
+ dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ pRegister->setValUInt8Array2D( pDevice->RW_byte_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2); //use automatic conversion for JAVA non-supported type
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_word");
+ uint32_t dim1 = pRegister->getDimension1();
+ dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ pRegister->setValUInt16Array2D( pDevice->RW_word_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2); //use automatic conversion for JAVA non-supported type
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_dword");
+ uint32_t dim1 = pRegister->getDimension1();
+ dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ pRegister->setValUInt32Array2D( pDevice->RW_dword_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2); //use automatic conversion for JAVA non-supported type
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_int");
+ uint32_t dim1 = pRegister->getDimension1();
+ dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ pRegister->setValInt16Array2D(pDevice->RW_int_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_dint");
+ uint32_t dim1 = pRegister->getDimension1();
+ dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ pRegister->setValInt32Array2D(pDevice->RW_dint_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_real");
+ uint32_t dim1 = pRegister->getDimension1();
+ dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ pRegister->setValFloat32Array2D(pDevice->RW_real_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_dt");
+ uint32_t dim1 = pRegister->getDimension1();
+ dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ pRegister->setValDateArray2D(pDevice->RW_dt_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
if (sendNow) pPLCDevice->send(blockName_);
+ }
- }
- void MyRWBlock_Type::setOneDevice(Device* pDevice, MyRWBlockPropertyData& data, bool sendNow, MultiplexingContext* pContext)
+ void MyRWBlock_Type::setOneDevice(Device* pDevice, MyRWBlockPropPropertyData& data, bool sendNow, MultiplexingContext* pContext)
{
if( !isInitialized_ )
{
@@ -434,112 +509,154 @@ namespace AllTypes
}
Silecs::PLC* pPLC = pCluster_->getPLC(pDevice->plcHostName.get(),pDevice->parameterFile.get());
Silecs::Device* pPLCDevice = pPLC->getDevice(pDevice->plcDeviceLabel.get());
- Silecs::Register* pRegister = NULL;
- uint32_t dim1 = 1;
- uint32_t fesaDim1;
- uint32_t dim2 = 1;
- uint32_t fesaDim2;
-
-
- pRegister = pPLCDevice->getRegister("RW_int8");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (data.isRW_int8Available()) ? pRegister->setValInt8Array2D(data.RW_int8.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setValInt8Array2D(pDevice->RW_int8.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_uint8");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (data.isRW_uint8Available()) ? pRegister->setValUInt8Array2D(data.RW_uint8.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setValUInt8Array2D(pDevice->RW_uint8.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_int16");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (data.isRW_int16Available()) ? pRegister->setValInt16Array2D(data.RW_int16.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setValInt16Array2D(pDevice->RW_int16.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_uint16");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (data.isRW_uint16Available()) ? pRegister->setValUInt16Array2D(data.RW_uint16.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setValUInt16Array2D(pDevice->RW_uint16.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_int32");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (data.isRW_int32Available()) ? pRegister->setValInt32Array2D(data.RW_int32.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setValInt32Array2D(pDevice->RW_int32.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_uint32");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (data.isRW_uint32Available()) ? pRegister->setValUInt32Array2D(data.RW_uint32.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setValUInt32Array2D(pDevice->RW_uint32.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_float32");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (data.isRW_float32Available()) ? pRegister->setValFloat32Array2D(data.RW_float32.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setValFloat32Array2D(pDevice->RW_float32.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_date");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (data.isRW_dateAvailable()) ? pRegister->setValDateArray2D(data.RW_date.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setValDateArray2D(pDevice->RW_date.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_char");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (data.isRW_charAvailable()) ? pRegister->setValInt8Array2D(data.RW_char.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setValInt8Array2D(pDevice->RW_char.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_byte");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (data.isRW_byteAvailable()) ? pRegister->setValUInt8Array2D(data.RW_byte.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setValUInt8Array2D(pDevice->RW_byte.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_word");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (data.isRW_wordAvailable()) ? pRegister->setValUInt16Array2D(data.RW_word.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setValUInt16Array2D(pDevice->RW_word.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_dword");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (data.isRW_dwordAvailable()) ? pRegister->setValUInt32Array2D(data.RW_dword.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setValUInt32Array2D(pDevice->RW_dword.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_int");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (data.isRW_intAvailable()) ? pRegister->setValInt16Array2D(data.RW_int.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setValInt16Array2D(pDevice->RW_int.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_dint");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (data.isRW_dintAvailable()) ? pRegister->setValInt32Array2D(data.RW_dint.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setValInt32Array2D(pDevice->RW_dint.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_real");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (data.isRW_realAvailable()) ? pRegister->setValFloat32Array2D(data.RW_real.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setValFloat32Array2D(pDevice->RW_real.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
-
- pRegister = pPLCDevice->getRegister("RW_dt");
- dim1 = pRegister->getDimension1();
- dim2 = pRegister->getDimension2();
- (data.isRW_dtAvailable()) ? pRegister->setValDateArray2D(data.RW_dt.get(fesaDim1, fesaDim2), dim1, dim2) :
- pRegister->setValDateArray2D(pDevice->RW_dt.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_int8");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ (data.isRW_int8Available()) ? pRegister->setValInt8Array2D(data.RW_int8.get(fesaDim1, fesaDim2), dim1, dim2) :
+ pRegister->setValInt8Array2D(pDevice->RW_int8.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_uint8");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ (data.isRW_uint8_fesaAvailable()) ? pRegister->setValUInt8Array2D(data.RW_uint8_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ pRegister->setValUInt8Array2D(pDevice->RW_uint8_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_int16");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ (data.isRW_int16_fesaAvailable()) ? pRegister->setValInt16Array2D(data.RW_int16_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ pRegister->setValInt16Array2D(pDevice->RW_int16_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_uint16");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ (data.isRW_uint16_fesaAvailable()) ? pRegister->setValUInt16Array2D(data.RW_uint16_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ pRegister->setValUInt16Array2D(pDevice->RW_uint16_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_int32");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ (data.isRW_int32_fesaAvailable()) ? pRegister->setValInt32Array2D(data.RW_int32_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ pRegister->setValInt32Array2D(pDevice->RW_int32_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_uint32");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ (data.isRW_uint32_fesaAvailable()) ? pRegister->setValUInt32Array2D(data.RW_uint32_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ pRegister->setValUInt32Array2D(pDevice->RW_uint32_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_float32");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ (data.isRW_float32_fesaAvailable()) ? pRegister->setValFloat32Array2D(data.RW_float32_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ pRegister->setValFloat32Array2D(pDevice->RW_float32_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_date");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ (data.isRW_date_fesaAvailable()) ? pRegister->setValDateArray2D(data.RW_date_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ pRegister->setValDateArray2D(pDevice->RW_date_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_char");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ (data.isRW_char_fesaAvailable()) ? pRegister->setValInt8Array2D(data.RW_char_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ pRegister->setValInt8Array2D(pDevice->RW_char_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_byte");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ (data.isRW_byte_fesaAvailable()) ? pRegister->setValUInt8Array2D(data.RW_byte_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ pRegister->setValUInt8Array2D(pDevice->RW_byte_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_word");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ (data.isRW_word_fesaAvailable()) ? pRegister->setValUInt16Array2D(data.RW_word_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ pRegister->setValUInt16Array2D(pDevice->RW_word_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_dword");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ (data.isRW_dword_fesaAvailable()) ? pRegister->setValUInt32Array2D(data.RW_dword_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ pRegister->setValUInt32Array2D(pDevice->RW_dword_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_int");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ (data.isRW_int_fesaAvailable()) ? pRegister->setValInt16Array2D(data.RW_int_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ pRegister->setValInt16Array2D(pDevice->RW_int_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_dint");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ (data.isRW_dint_fesaAvailable()) ? pRegister->setValInt32Array2D(data.RW_dint_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ pRegister->setValInt32Array2D(pDevice->RW_dint_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_real");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ (data.isRW_real_fesaAvailable()) ? pRegister->setValFloat32Array2D(data.RW_real_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ pRegister->setValFloat32Array2D(pDevice->RW_real_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("RW_dt");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t dim2 = pRegister->getDimension2();
+ uint32_t fesaDim1,fesaDim2;
+ (data.isRW_dt_fesaAvailable()) ? pRegister->setValDateArray2D(data.RW_dt_fesa.get(fesaDim1, fesaDim2), dim1, dim2) :
+ pRegister->setValDateArray2D(pDevice->RW_dt_fesa.get(fesaDim1, fesaDim2, pContext), dim1, dim2);
+ }
if (sendNow) pPLCDevice->send(blockName_);
- }
+ }
void MyWOBlock_Type::setOneDevice(Device* pDevice, const bool sendNow, MultiplexingContext* pContext)
{
@@ -549,88 +666,133 @@ namespace AllTypes
}
Silecs::PLC* pPLC = pCluster_->getPLC(pDevice->plcHostName.get(),pDevice->parameterFile.get());
Silecs::Device* pPLCDevice = pPLC->getDevice(pDevice->plcDeviceLabel.get());
- Silecs::Register* pRegister = NULL;
- uint32_t dim1 = 1;
- uint32_t fesaDim1;
-
- pRegister = pPLCDevice->getRegister("WO_int8");
- dim1 = pRegister->getDimension1();
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_int8");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
pRegister->setValInt8Array(pDevice->WO_int8.get(fesaDim1, pContext), dim1);
+ }
- pRegister = pPLCDevice->getRegister("WO_uint8");
- dim1 = pRegister->getDimension1();
- pRegister->setValUInt8Array(pDevice->WO_uint8.get(fesaDim1, pContext), dim1); //use automatic conversion for JAVA non-supported type
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_uint8");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ pRegister->setValUInt8Array(pDevice->WO_uint8_fesa.get(fesaDim1, pContext), dim1); //use automatic conversion for JAVA non-supported type
+ }
- pRegister = pPLCDevice->getRegister("WO_int16");
- dim1 = pRegister->getDimension1();
- pRegister->setValInt16Array(pDevice->WO_int16.get(fesaDim1, pContext), dim1);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_int16");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ pRegister->setValInt16Array(pDevice->WO_int16_fesa.get(fesaDim1, pContext), dim1);
+ }
- pRegister = pPLCDevice->getRegister("WO_uint16");
- dim1 = pRegister->getDimension1();
- pRegister->setValUInt16Array(pDevice->WO_uint16.get(fesaDim1, pContext), dim1); //use automatic conversion for JAVA non-supported type
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_uint16");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ pRegister->setValUInt16Array(pDevice->WO_uint16_fesa.get(fesaDim1, pContext), dim1); //use automatic conversion for JAVA non-supported type
+ }
- pRegister = pPLCDevice->getRegister("WO_int32");
- dim1 = pRegister->getDimension1();
- pRegister->setValInt32Array(pDevice->WO_int32.get(fesaDim1, pContext), dim1);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_int32");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ pRegister->setValInt32Array(pDevice->WO_int32_fesa.get(fesaDim1, pContext), dim1);
+ }
- pRegister = pPLCDevice->getRegister("WO_uint32");
- dim1 = pRegister->getDimension1();
- pRegister->setValUInt32Array(pDevice->WO_uint32.get(fesaDim1, pContext), dim1); //use automatic conversion for JAVA non-supported type
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_uint32");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ pRegister->setValUInt32Array(pDevice->WO_uint32_fesa.get(fesaDim1, pContext), dim1); //use automatic conversion for JAVA non-supported type
+ }
- pRegister = pPLCDevice->getRegister("WO_float32");
- dim1 = pRegister->getDimension1();
- pRegister->setValFloat32Array(pDevice->WO_float32.get(fesaDim1, pContext), dim1);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_float32");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ pRegister->setValFloat32Array(pDevice->WO_float32_fesa.get(fesaDim1, pContext), dim1);
+ }
{
- pRegister = pPLCDevice->getRegister("WO_string");
- dim1 = pRegister->getDimension1();
- std::string stdStringArray[dim1];
- const char** cStringArray = pDevice->WO_string.get(fesaDim1, pContext);
- for (unsigned int i=0; i<dim1; i++) stdStringArray[i] = (const char*)cStringArray[i];
- pRegister->setValStringArray(stdStringArray, dim1);
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_string");
+ uint32_t dim1 = pRegister->getDimension1();
+ std::string stdStringArray[dim1];
+ uint32_t fesaDim1;
+ const char** cStringArray = pDevice->WO_string_fesa.get(fesaDim1, pContext);
+ for (unsigned int i=0; i<dim1; i++) stdStringArray[i] = (const char*)cStringArray[i];
+ pRegister->setValStringArray(stdStringArray, dim1);
}
- pRegister = pPLCDevice->getRegister("WO_date");
- dim1 = pRegister->getDimension1();
- pRegister->setValDateArray(pDevice->WO_date.get(fesaDim1, pContext), dim1);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_date");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ pRegister->setValDateArray(pDevice->WO_date_fesa.get(fesaDim1, pContext), dim1);
+ }
- pRegister = pPLCDevice->getRegister("WO_char");
- dim1 = pRegister->getDimension1();
- pRegister->setValInt8Array(pDevice->WO_char.get(fesaDim1, pContext), dim1);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_char");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ pRegister->setValInt8Array(pDevice->WO_char_fesa.get(fesaDim1, pContext), dim1);
+ }
- pRegister = pPLCDevice->getRegister("WO_byte");
- dim1 = pRegister->getDimension1();
- pRegister->setValUInt8Array(pDevice->WO_byte.get(fesaDim1, pContext), dim1); //use automatic conversion for JAVA non-supported type
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_byte");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ pRegister->setValUInt8Array(pDevice->WO_byte_fesa.get(fesaDim1, pContext), dim1); //use automatic conversion for JAVA non-supported type
+ }
- pRegister = pPLCDevice->getRegister("WO_word");
- dim1 = pRegister->getDimension1();
- pRegister->setValUInt16Array(pDevice->WO_word.get(fesaDim1, pContext), dim1); //use automatic conversion for JAVA non-supported type
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_word");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ pRegister->setValUInt16Array(pDevice->WO_word_fesa.get(fesaDim1, pContext), dim1); //use automatic conversion for JAVA non-supported type
+ }
- pRegister = pPLCDevice->getRegister("WO_dword");
- dim1 = pRegister->getDimension1();
- pRegister->setValUInt32Array(pDevice->WO_dword.get(fesaDim1, pContext), dim1); //use automatic conversion for JAVA non-supported type
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_dword");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ pRegister->setValUInt32Array(pDevice->WO_dword_fesa.get(fesaDim1, pContext), dim1); //use automatic conversion for JAVA non-supported type
+ }
- pRegister = pPLCDevice->getRegister("WO_int");
- dim1 = pRegister->getDimension1();
- pRegister->setValInt16Array(pDevice->WO_int.get(fesaDim1, pContext), dim1);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_int");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ pRegister->setValInt16Array(pDevice->WO_int_fesa.get(fesaDim1, pContext), dim1);
+ }
- pRegister = pPLCDevice->getRegister("WO_dint");
- dim1 = pRegister->getDimension1();
- pRegister->setValInt32Array(pDevice->WO_dint.get(fesaDim1, pContext), dim1);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_dint");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ pRegister->setValInt32Array(pDevice->WO_dint_fesa.get(fesaDim1, pContext), dim1);
+ }
- pRegister = pPLCDevice->getRegister("WO_real");
- dim1 = pRegister->getDimension1();
- pRegister->setValFloat32Array(pDevice->WO_real.get(fesaDim1, pContext), dim1);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_real");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ pRegister->setValFloat32Array(pDevice->WO_real_fesa.get(fesaDim1, pContext), dim1);
+ }
- pRegister = pPLCDevice->getRegister("WO_dt");
- dim1 = pRegister->getDimension1();
- pRegister->setValDateArray(pDevice->WO_dt.get(fesaDim1, pContext), dim1);
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_dt");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ pRegister->setValDateArray(pDevice->WO_dt_fesa.get(fesaDim1, pContext), dim1);
+ }
if (sendNow) pPLCDevice->send(blockName_);
+ }
- }
- void MyWOBlock_Type::setOneDevice(Device* pDevice, MyWOBlockPropertyData& data, bool sendNow, MultiplexingContext* pContext)
+ void MyWOBlock_Type::setOneDevice(Device* pDevice, MyWOBlockPropPropertyData& data, bool sendNow, MultiplexingContext* pContext)
{
if( !isInitialized_ )
{
@@ -638,101 +800,147 @@ namespace AllTypes
}
Silecs::PLC* pPLC = pCluster_->getPLC(pDevice->plcHostName.get(),pDevice->parameterFile.get());
Silecs::Device* pPLCDevice = pPLC->getDevice(pDevice->plcDeviceLabel.get());
- Silecs::Register* pRegister = NULL;
- uint32_t dim1 = 1;
- uint32_t fesaDim1;
-
- pRegister = pPLCDevice->getRegister("WO_int8");
- dim1 = pRegister->getDimension1();
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_int8");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
(data.isWO_int8Available()) ? pRegister->setValInt8Array( data.WO_int8.get(fesaDim1), dim1) :
- pRegister->setValInt8Array( pDevice->WO_int8.get(fesaDim1, pContext), dim1);
-
- pRegister = pPLCDevice->getRegister("WO_uint8");
- dim1 = pRegister->getDimension1();
- (data.isWO_uint8Available()) ? pRegister->setValUInt8Array( data.WO_uint8.get(fesaDim1), dim1) :
- pRegister->setValUInt8Array( pDevice->WO_uint8.get(fesaDim1, pContext), dim1);
-
- pRegister = pPLCDevice->getRegister("WO_int16");
- dim1 = pRegister->getDimension1();
- (data.isWO_int16Available()) ? pRegister->setValInt16Array( data.WO_int16.get(fesaDim1), dim1) :
- pRegister->setValInt16Array( pDevice->WO_int16.get(fesaDim1, pContext), dim1);
-
- pRegister = pPLCDevice->getRegister("WO_uint16");
- dim1 = pRegister->getDimension1();
- (data.isWO_uint16Available()) ? pRegister->setValUInt16Array( data.WO_uint16.get(fesaDim1), dim1) :
- pRegister->setValUInt16Array( pDevice->WO_uint16.get(fesaDim1, pContext), dim1);
-
- pRegister = pPLCDevice->getRegister("WO_int32");
- dim1 = pRegister->getDimension1();
- (data.isWO_int32Available()) ? pRegister->setValInt32Array( data.WO_int32.get(fesaDim1), dim1) :
- pRegister->setValInt32Array( pDevice->WO_int32.get(fesaDim1, pContext), dim1);
-
- pRegister = pPLCDevice->getRegister("WO_uint32");
- dim1 = pRegister->getDimension1();
- (data.isWO_uint32Available()) ? pRegister->setValUInt32Array( data.WO_uint32.get(fesaDim1), dim1) :
- pRegister->setValUInt32Array( pDevice->WO_uint32.get(fesaDim1, pContext), dim1);
-
- pRegister = pPLCDevice->getRegister("WO_float32");
- dim1 = pRegister->getDimension1();
- (data.isWO_float32Available()) ? pRegister->setValFloat32Array( data.WO_float32.get(fesaDim1), dim1) :
- pRegister->setValFloat32Array( pDevice->WO_float32.get(fesaDim1, pContext), dim1);
-
- {
- pRegister = pPLCDevice->getRegister("WO_string");
- dim1 = pRegister->getDimension1();
- std::string stdStringArray[dim1];
- const char** cStringArray = (data.isWO_stringAvailable() ? data.WO_string.get(fesaDim1) : pDevice->WO_string.get(fesaDim1, pContext));
- for (unsigned int i=0; i<dim1; i++) stdStringArray[i] = (const char*)cStringArray[i];
- pRegister->setValStringArray(stdStringArray, dim1);
- }
-
- pRegister = pPLCDevice->getRegister("WO_date");
- dim1 = pRegister->getDimension1();
- (data.isWO_dateAvailable()) ? pRegister->setValDateArray( data.WO_date.get(fesaDim1), dim1) :
- pRegister->setValDateArray( pDevice->WO_date.get(fesaDim1, pContext), dim1);
-
- pRegister = pPLCDevice->getRegister("WO_char");
- dim1 = pRegister->getDimension1();
- (data.isWO_charAvailable()) ? pRegister->setValInt8Array( data.WO_char.get(fesaDim1), dim1) :
- pRegister->setValInt8Array( pDevice->WO_char.get(fesaDim1, pContext), dim1);
-
- pRegister = pPLCDevice->getRegister("WO_byte");
- dim1 = pRegister->getDimension1();
- (data.isWO_byteAvailable()) ? pRegister->setValUInt8Array( data.WO_byte.get(fesaDim1), dim1) :
- pRegister->setValUInt8Array( pDevice->WO_byte.get(fesaDim1, pContext), dim1);
-
- pRegister = pPLCDevice->getRegister("WO_word");
- dim1 = pRegister->getDimension1();
- (data.isWO_wordAvailable()) ? pRegister->setValUInt16Array( data.WO_word.get(fesaDim1), dim1) :
- pRegister->setValUInt16Array( pDevice->WO_word.get(fesaDim1, pContext), dim1);
-
- pRegister = pPLCDevice->getRegister("WO_dword");
- dim1 = pRegister->getDimension1();
- (data.isWO_dwordAvailable()) ? pRegister->setValUInt32Array( data.WO_dword.get(fesaDim1), dim1) :
- pRegister->setValUInt32Array( pDevice->WO_dword.get(fesaDim1, pContext), dim1);
-
- pRegister = pPLCDevice->getRegister("WO_int");
- dim1 = pRegister->getDimension1();
- (data.isWO_intAvailable()) ? pRegister->setValInt16Array( data.WO_int.get(fesaDim1), dim1) :
- pRegister->setValInt16Array( pDevice->WO_int.get(fesaDim1, pContext), dim1);
-
- pRegister = pPLCDevice->getRegister("WO_dint");
- dim1 = pRegister->getDimension1();
- (data.isWO_dintAvailable()) ? pRegister->setValInt32Array( data.WO_dint.get(fesaDim1), dim1) :
- pRegister->setValInt32Array( pDevice->WO_dint.get(fesaDim1, pContext), dim1);
-
- pRegister = pPLCDevice->getRegister("WO_real");
- dim1 = pRegister->getDimension1();
- (data.isWO_realAvailable()) ? pRegister->setValFloat32Array( data.WO_real.get(fesaDim1), dim1) :
- pRegister->setValFloat32Array( pDevice->WO_real.get(fesaDim1, pContext), dim1);
-
- pRegister = pPLCDevice->getRegister("WO_dt");
- dim1 = pRegister->getDimension1();
- (data.isWO_dtAvailable()) ? pRegister->setValDateArray( data.WO_dt.get(fesaDim1), dim1) :
- pRegister->setValDateArray( pDevice->WO_dt.get(fesaDim1, pContext), dim1);
+ pRegister->setValInt8Array( pDevice->WO_int8.get(fesaDim1, pContext), dim1);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_uint8");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ (data.isWO_uint8_fesaAvailable()) ? pRegister->setValUInt8Array( data.WO_uint8_fesa.get(fesaDim1), dim1) :
+ pRegister->setValUInt8Array( pDevice->WO_uint8_fesa.get(fesaDim1, pContext), dim1);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_int16");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ (data.isWO_int16_fesaAvailable()) ? pRegister->setValInt16Array( data.WO_int16_fesa.get(fesaDim1), dim1) :
+ pRegister->setValInt16Array( pDevice->WO_int16_fesa.get(fesaDim1, pContext), dim1);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_uint16");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ (data.isWO_uint16_fesaAvailable()) ? pRegister->setValUInt16Array( data.WO_uint16_fesa.get(fesaDim1), dim1) :
+ pRegister->setValUInt16Array( pDevice->WO_uint16_fesa.get(fesaDim1, pContext), dim1);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_int32");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ (data.isWO_int32_fesaAvailable()) ? pRegister->setValInt32Array( data.WO_int32_fesa.get(fesaDim1), dim1) :
+ pRegister->setValInt32Array( pDevice->WO_int32_fesa.get(fesaDim1, pContext), dim1);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_uint32");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ (data.isWO_uint32_fesaAvailable()) ? pRegister->setValUInt32Array( data.WO_uint32_fesa.get(fesaDim1), dim1) :
+ pRegister->setValUInt32Array( pDevice->WO_uint32_fesa.get(fesaDim1, pContext), dim1);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_float32");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ (data.isWO_float32_fesaAvailable()) ? pRegister->setValFloat32Array( data.WO_float32_fesa.get(fesaDim1), dim1) :
+ pRegister->setValFloat32Array( pDevice->WO_float32_fesa.get(fesaDim1, pContext), dim1);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_string");
+ uint32_t dim1 = pRegister->getDimension1();
+ std::string stdStringArray[dim1];
+ uint32_t fesaDim1;
+ const char** cStringArray = (data.isWO_string_fesaAvailable() ? data.WO_string_fesa.get(fesaDim1) : pDevice->WO_string_fesa.get(fesaDim1, pContext));
+ for (unsigned int i=0; i<dim1; i++) stdStringArray[i] = (const char*)cStringArray[i];
+ pRegister->setValStringArray(stdStringArray, dim1);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_date");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ (data.isWO_date_fesaAvailable()) ? pRegister->setValDateArray( data.WO_date_fesa.get(fesaDim1), dim1) :
+ pRegister->setValDateArray( pDevice->WO_date_fesa.get(fesaDim1, pContext), dim1);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_char");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ (data.isWO_char_fesaAvailable()) ? pRegister->setValInt8Array( data.WO_char_fesa.get(fesaDim1), dim1) :
+ pRegister->setValInt8Array( pDevice->WO_char_fesa.get(fesaDim1, pContext), dim1);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_byte");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ (data.isWO_byte_fesaAvailable()) ? pRegister->setValUInt8Array( data.WO_byte_fesa.get(fesaDim1), dim1) :
+ pRegister->setValUInt8Array( pDevice->WO_byte_fesa.get(fesaDim1, pContext), dim1);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_word");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ (data.isWO_word_fesaAvailable()) ? pRegister->setValUInt16Array( data.WO_word_fesa.get(fesaDim1), dim1) :
+ pRegister->setValUInt16Array( pDevice->WO_word_fesa.get(fesaDim1, pContext), dim1);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_dword");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ (data.isWO_dword_fesaAvailable()) ? pRegister->setValUInt32Array( data.WO_dword_fesa.get(fesaDim1), dim1) :
+ pRegister->setValUInt32Array( pDevice->WO_dword_fesa.get(fesaDim1, pContext), dim1);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_int");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ (data.isWO_int_fesaAvailable()) ? pRegister->setValInt16Array( data.WO_int_fesa.get(fesaDim1), dim1) :
+ pRegister->setValInt16Array( pDevice->WO_int_fesa.get(fesaDim1, pContext), dim1);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_dint");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ (data.isWO_dint_fesaAvailable()) ? pRegister->setValInt32Array( data.WO_dint_fesa.get(fesaDim1), dim1) :
+ pRegister->setValInt32Array( pDevice->WO_dint_fesa.get(fesaDim1, pContext), dim1);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_real");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ (data.isWO_real_fesaAvailable()) ? pRegister->setValFloat32Array( data.WO_real_fesa.get(fesaDim1), dim1) :
+ pRegister->setValFloat32Array( pDevice->WO_real_fesa.get(fesaDim1, pContext), dim1);
+ }
+
+ {
+ Silecs::Register* pRegister = pPLCDevice->getRegister("WO_dt");
+ uint32_t dim1 = pRegister->getDimension1();
+ uint32_t fesaDim1;
+ (data.isWO_dt_fesaAvailable()) ? pRegister->setValDateArray( data.WO_dt_fesa.get(fesaDim1), dim1) :
+ pRegister->setValDateArray( pDevice->WO_dt_fesa.get(fesaDim1, pContext), dim1);
+ }
if (sendNow) pPLCDevice->send(blockName_);
- }
+ }
+
}
diff --git a/silecs-codegen/src/xml/test/generated_correct/AllTypes.h b/silecs-codegen/src/xml/test/generated_correct/AllTypes.h
index 3edca8fa217278bc71c97da47d4625f01426f1c3..af3396c92c66a419d80af6d9088f5c955bf687f9 100644
--- a/silecs-codegen/src/xml/test/generated_correct/AllTypes.h
+++ b/silecs-codegen/src/xml/test/generated_correct/AllTypes.h
@@ -10,9 +10,9 @@
#include <SilecsService.h>
#include <fesa-core/Synchronization/MultiplexingContext.h>
#include <AllTypes/GeneratedCode/ServiceLocator.h>
- #include <AllTypes/Server/SendMyRWBlock.h>
- #include <AllTypes/Server/SendMyWOBlock.h>
-
+#include <AllTypes/Server/SetMyRWBlockProp.h>
+#include <AllTypes/Server/SetMyWOBlockProp.h>
+
namespace AllTypes
{
@@ -56,6 +56,7 @@ namespace AllTypes
static void setup(const ServiceLocator* serviceLocator);
static void cleanup();
+ static bool isInitialized(){ return AbstractAllTypes::isInitialized_; }
static void setPLCSlaveRegisters(Silecs::PLC* pPLC, const ServiceLocator* serviceLocator);
static void getPLCMasterRegisters(Silecs::PLC* pPLC, const ServiceLocator* serviceLocator);
@@ -87,40 +88,40 @@ namespace AllTypes
};
// -------------------------------------------------------------------------------------------------
- #define BLOCK_RO( name ) \
- class name##_Type : public AbstractAllTypes \
+ #define BLOCK_RO( blockName, propName ) \
+ class blockName##_Type : public AbstractAllTypes \
{ \
public: \
- name##_Type(std::string name); \
- ~name##_Type(); \
+ blockName##_Type(std::string name); \
+ ~blockName##_Type(); \
void getOneDevice(Device* pDevice, const bool transmitNow, MultiplexingContext* pContext); \
}
- #define BLOCK_WO( name ) \
- class name##_Type : public AbstractAllTypes \
+ #define BLOCK_WO( blockName, propName ) \
+ class blockName##_Type : public AbstractAllTypes \
{ \
public: \
- name##_Type(std::string name); \
- ~name##_Type(); \
+ blockName##_Type(std::string name); \
+ ~blockName##_Type(); \
void setOneDevice(Device* pDevice, const bool transmitNow, MultiplexingContext* pContext); \
- void setOneDevice(Device* pDevice, name##PropertyData& data, const bool transmitNow, MultiplexingContext* pContext); \
+ void setOneDevice(Device* pDevice, propName##PropertyData& data, const bool transmitNow, MultiplexingContext* pContext); \
}
- #define BLOCK_RW( name ) \
- class name##_Type : public AbstractAllTypes \
+ #define BLOCK_RW( blockName, propName ) \
+ class blockName##_Type : public AbstractAllTypes \
{ \
public: \
- name##_Type(std::string name); \
- ~name##_Type(); \
+ blockName##_Type(std::string name); \
+ ~blockName##_Type(); \
void getOneDevice(Device* pDevice, const bool transmitNow, MultiplexingContext* pContext); \
void setOneDevice(Device* pDevice, const bool transmitNow, MultiplexingContext* pContext); \
- void setOneDevice(Device* pDevice, name##PropertyData& data, const bool transmitNow, MultiplexingContext* pContext); \
+ void setOneDevice(Device* pDevice, propName##PropertyData& data, const bool transmitNow, MultiplexingContext* pContext); \
}
- BLOCK_RO( MyROBlock );
- BLOCK_RW( MyRWBlock );
- BLOCK_WO( MyWOBlock );
+ BLOCK_RO( MyROBlock, MyROBlockProp );
+ BLOCK_RW( MyRWBlock, MyRWBlockProp );
+ BLOCK_WO( MyWOBlock, MyWOBlockProp );
/*---------------------------------------------------------------------------------------------------------
* INTERFACE
@@ -134,11 +135,15 @@ namespace AllTypes
static inline Silecs::Cluster* theCluster() { return AbstractAllTypes::theCluster(); }
static void setup(const ServiceLocator* serviceLocator) { AbstractAllTypes::setup(serviceLocator); }
static void cleanup() { AbstractAllTypes::cleanup(); }
-
- static MyROBlock_Type MyROBlock;
- static MyRWBlock_Type MyRWBlock;
- static MyWOBlock_Type MyWOBlock;
-
+ static bool isInitialized(){ return AbstractAllTypes::isInitialized(); }
+ static Silecs::PLC* getPLC(Device* pDevice)
+ {
+ return AbstractAllTypes::theCluster()->getPLC(pDevice->plcHostName.get(),pDevice->parameterFile.get());
+ }
+
+ static MyROBlock_Type MyROBlock;
+ static MyRWBlock_Type MyRWBlock;
+ static MyWOBlock_Type MyWOBlock;
};
}
diff --git a/silecs-codegen/src/xml/test/generated_correct/AllTypesFESA.design b/silecs-codegen/src/xml/test/generated_correct/AllTypesFESA.design
index 68ba06391b0da0070cd148dffab36d658d29c968..5d76d016bd64b791c36d830596a896bebd06fa9a 100644
--- a/silecs-codegen/src/xml/test/generated_correct/AllTypesFESA.design
+++ b/silecs-codegen/src/xml/test/generated_correct/AllTypesFESA.design
@@ -44,7 +44,7 @@
<server-action-ref server-action-name-ref="SettingGetAction"/>
</get-action>
</GSI-Setting-Property>
- <GSI-Setting-Property name="MyRWBlock" multiplexed="false" visibility="development"><value-item name="RW_dt" direction="INOUT"><array2D type="double"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_dt"/></value-item><value-item name="RW_real" direction="INOUT"><array2D type="float"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_real"/></value-item><value-item name="RW_dint" direction="INOUT"><array2D type="int32_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_dint"/></value-item><value-item name="RW_int" direction="INOUT"><array2D type="int16_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_int"/></value-item><value-item name="RW_dword" direction="INOUT"><array2D type="int64_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_dword"/></value-item><value-item name="RW_word" direction="INOUT"><array2D type="int32_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_word"/></value-item><value-item name="RW_byte" direction="INOUT"><array2D type="int16_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_byte"/></value-item><value-item name="RW_char" direction="INOUT"><array2D type="int8_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_char"/></value-item><value-item name="RW_date" direction="INOUT"><array2D type="double"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_date"/></value-item><value-item name="RW_float32" direction="INOUT"><array2D type="float"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_float32"/></value-item><value-item name="RW_uint32" direction="INOUT"><array2D type="int64_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_uint32"/></value-item><value-item name="RW_int32" direction="INOUT"><array2D type="int32_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_int32"/></value-item><value-item name="RW_uint16" direction="INOUT"><array2D type="int32_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_uint16"/></value-item><value-item name="RW_int16" direction="INOUT"><array2D type="int16_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_int16"/></value-item><value-item name="RW_uint8" direction="INOUT"><array2D type="int16_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_uint8"/></value-item><value-item name="RW_int8" direction="INOUT"><array2D type="int8_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_int8"/></value-item><update-flag-item direction="OUT" optional="true" name="updateFlags"><builtin-type-scalar data-type-name-ref="NOTIFICATION_UPDATE"/></update-flag-item><cycle-name-item direction="OUT" optional="true" name="cycleName"><array type="char"><dim>32</dim></array></cycle-name-item><set-action><server-action-ref server-action-name-ref="SendMyRWBlock"/></set-action><get-action><server-action-ref server-action-name-ref="RecvMyRWBlock"/></get-action></GSI-Setting-Property><GSI-Setting-Property name="MyWOBlock" multiplexed="false" visibility="development"><value-item name="WO_dt" direction="INOUT"><array type="double"><dim>10</dim></array><data-field-ref field-name-ref="WO_dt"/></value-item><value-item name="WO_real" direction="INOUT"><array type="float"><dim>10</dim></array><data-field-ref field-name-ref="WO_real"/></value-item><value-item name="WO_dint" direction="INOUT"><array type="int32_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_dint"/></value-item><value-item name="WO_int" direction="INOUT"><array type="int16_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_int"/></value-item><value-item name="WO_dword" direction="INOUT"><array type="int64_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_dword"/></value-item><value-item name="WO_word" direction="INOUT"><array type="int32_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_word"/></value-item><value-item name="WO_byte" direction="INOUT"><array type="int16_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_byte"/></value-item><value-item name="WO_char" direction="INOUT"><array type="int8_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_char"/></value-item><value-item name="WO_date" direction="INOUT"><array type="double"><dim>10</dim></array><data-field-ref field-name-ref="WO_date"/></value-item><value-item name="WO_string" direction="INOUT"><array2D type="char"><dim1>10</dim1><dim2>64</dim2></array2D><data-field-ref field-name-ref="WO_string"/></value-item><value-item name="WO_float32" direction="INOUT"><array type="float"><dim>10</dim></array><data-field-ref field-name-ref="WO_float32"/></value-item><value-item name="WO_uint32" direction="INOUT"><array type="int64_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_uint32"/></value-item><value-item name="WO_int32" direction="INOUT"><array type="int32_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_int32"/></value-item><value-item name="WO_uint16" direction="INOUT"><array type="int32_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_uint16"/></value-item><value-item name="WO_int16" direction="INOUT"><array type="int16_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_int16"/></value-item><value-item name="WO_uint8" direction="INOUT"><array type="int16_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_uint8"/></value-item><value-item name="WO_int8" direction="INOUT"><array type="int8_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_int8"/></value-item><update-flag-item direction="OUT" optional="true" name="updateFlags"><builtin-type-scalar data-type-name-ref="NOTIFICATION_UPDATE"/></update-flag-item><cycle-name-item direction="OUT" optional="true" name="cycleName"><array type="char"><dim>32</dim></array></cycle-name-item><set-action><server-action-ref server-action-name-ref="SendMyWOBlock"/></set-action><get-action><server-action-ref server-action-name-ref="GetMyWOBlock"/></get-action></GSI-Setting-Property><GSI-Power-Property multiplexed="false" name="Power" visibility="operational">
+ <GSI-Setting-Property name="MyRWBlockProp" multiplexed="false" visibility="development"><value-item name="RW_dt_fesa" direction="INOUT"><array2D type="double"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_dt_fesa"/></value-item><value-item name="RW_real_fesa" direction="INOUT"><array2D type="float"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_real_fesa"/></value-item><value-item name="RW_dint_fesa" direction="INOUT"><array2D type="int32_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_dint_fesa"/></value-item><value-item name="RW_int_fesa" direction="INOUT"><array2D type="int16_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_int_fesa"/></value-item><value-item name="RW_dword_fesa" direction="INOUT"><array2D type="int64_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_dword_fesa"/></value-item><value-item name="RW_word_fesa" direction="INOUT"><array2D type="int32_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_word_fesa"/></value-item><value-item name="RW_byte_fesa" direction="INOUT"><array2D type="int16_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_byte_fesa"/></value-item><value-item name="RW_char_fesa" direction="INOUT"><array2D type="int8_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_char_fesa"/></value-item><value-item name="RW_date_fesa" direction="INOUT"><array2D type="double"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_date_fesa"/></value-item><value-item name="RW_float32_fesa" direction="INOUT"><array2D type="float"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_float32_fesa"/></value-item><value-item name="RW_uint32_fesa" direction="INOUT"><array2D type="int64_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_uint32_fesa"/></value-item><value-item name="RW_int32_fesa" direction="INOUT"><array2D type="int32_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_int32_fesa"/></value-item><value-item name="RW_uint16_fesa" direction="INOUT"><array2D type="int32_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_uint16_fesa"/></value-item><value-item name="RW_int16_fesa" direction="INOUT"><array2D type="int16_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_int16_fesa"/></value-item><value-item name="RW_uint8_fesa" direction="INOUT"><array2D type="int16_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_uint8_fesa"/></value-item><value-item name="RW_int8" direction="INOUT"><array2D type="int8_t"><dim1>2</dim1><dim2>2</dim2></array2D><data-field-ref field-name-ref="RW_int8"/></value-item><update-flag-item direction="OUT" optional="true" name="updateFlags"><builtin-type-scalar data-type-name-ref="NOTIFICATION_UPDATE"/></update-flag-item><cycle-name-item direction="OUT" optional="true" name="cycleName"><array type="char"><dim>32</dim></array></cycle-name-item><set-action><server-action-ref server-action-name-ref="SetMyRWBlockProp"/></set-action><get-action><server-action-ref server-action-name-ref="GetMyRWBlockProp"/></get-action></GSI-Setting-Property><GSI-Setting-Property name="MyWOBlockProp" multiplexed="false" visibility="development"><value-item name="WO_dt_fesa" direction="INOUT"><array type="double"><dim>10</dim></array><data-field-ref field-name-ref="WO_dt_fesa"/></value-item><value-item name="WO_real_fesa" direction="INOUT"><array type="float"><dim>10</dim></array><data-field-ref field-name-ref="WO_real_fesa"/></value-item><value-item name="WO_dint_fesa" direction="INOUT"><array type="int32_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_dint_fesa"/></value-item><value-item name="WO_int_fesa" direction="INOUT"><array type="int16_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_int_fesa"/></value-item><value-item name="WO_dword_fesa" direction="INOUT"><array type="int64_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_dword_fesa"/></value-item><value-item name="WO_word_fesa" direction="INOUT"><array type="int32_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_word_fesa"/></value-item><value-item name="WO_byte_fesa" direction="INOUT"><array type="int16_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_byte_fesa"/></value-item><value-item name="WO_char_fesa" direction="INOUT"><array type="int8_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_char_fesa"/></value-item><value-item name="WO_date_fesa" direction="INOUT"><array type="double"><dim>10</dim></array><data-field-ref field-name-ref="WO_date_fesa"/></value-item><value-item name="WO_string_fesa" direction="INOUT"><array2D type="char"><dim1>10</dim1><dim2>64</dim2></array2D><data-field-ref field-name-ref="WO_string_fesa"/></value-item><value-item name="WO_float32_fesa" direction="INOUT"><array type="float"><dim>10</dim></array><data-field-ref field-name-ref="WO_float32_fesa"/></value-item><value-item name="WO_uint32_fesa" direction="INOUT"><array type="int64_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_uint32_fesa"/></value-item><value-item name="WO_int32_fesa" direction="INOUT"><array type="int32_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_int32_fesa"/></value-item><value-item name="WO_uint16_fesa" direction="INOUT"><array type="int32_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_uint16_fesa"/></value-item><value-item name="WO_int16_fesa" direction="INOUT"><array type="int16_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_int16_fesa"/></value-item><value-item name="WO_uint8_fesa" direction="INOUT"><array type="int16_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_uint8_fesa"/></value-item><value-item name="WO_int8" direction="INOUT"><array type="int8_t"><dim>10</dim></array><data-field-ref field-name-ref="WO_int8"/></value-item><update-flag-item direction="OUT" optional="true" name="updateFlags"><builtin-type-scalar data-type-name-ref="NOTIFICATION_UPDATE"/></update-flag-item><cycle-name-item direction="OUT" optional="true" name="cycleName"><array type="char"><dim>32</dim></array></cycle-name-item><set-action><server-action-ref server-action-name-ref="SetMyWOBlockProp"/></set-action><get-action><server-action-ref server-action-name-ref="GetMyWOBlockProp"/></get-action></GSI-Setting-Property><GSI-Power-Property multiplexed="false" name="Power" visibility="operational">
<update-flag-item direction="OUT" name="updateFlags" optional="true">
<builtin-type-scalar data-type-name-ref="NOTIFICATION_UPDATE"/>
</update-flag-item>
@@ -232,7 +232,7 @@
<acquisition-context-field-ref field-name-ref="acquisitionContext"/>
</acquisition-context-item>
</GSI-Acquisition-Property>
- <GSI-Acquisition-Property name="MyROBlock" subscribable="true" multiplexed="false" on-change="true" visibility="development"><value-item name="RO_dt" direction="OUT"><scalar type="double"/><data-field-ref field-name-ref="RO_dt"/></value-item><value-item name="RO_real" direction="OUT"><scalar type="float"/><data-field-ref field-name-ref="RO_real"/></value-item><value-item name="RO_dint" direction="OUT"><scalar type="int32_t"/><data-field-ref field-name-ref="RO_dint"/></value-item><value-item name="RO_int" direction="OUT"><scalar type="int16_t"/><data-field-ref field-name-ref="RO_int"/></value-item><value-item name="RO_dword" direction="OUT"><scalar type="int64_t"/><data-field-ref field-name-ref="RO_dword"/></value-item><value-item name="RO_word" direction="OUT"><scalar type="int32_t"/><data-field-ref field-name-ref="RO_word"/></value-item><value-item name="RO_byte" direction="OUT"><scalar type="int16_t"/><data-field-ref field-name-ref="RO_byte"/></value-item><value-item name="RO_char" direction="OUT"><scalar type="int8_t"/><data-field-ref field-name-ref="RO_char"/></value-item><value-item name="RO_date" direction="OUT"><scalar type="double"/><data-field-ref field-name-ref="RO_date"/></value-item><value-item name="RO_string" direction="OUT"><array type="char"><dim>64</dim></array><data-field-ref field-name-ref="RO_string"/></value-item><value-item name="RO_float32" direction="OUT"><scalar type="float"/><data-field-ref field-name-ref="RO_float32"/></value-item><value-item name="RO_uint32" direction="OUT"><scalar type="int64_t"/><data-field-ref field-name-ref="RO_uint32"/></value-item><value-item name="RO_int32" direction="OUT"><scalar type="int32_t"/><data-field-ref field-name-ref="RO_int32"/></value-item><value-item name="RO_uint16" direction="OUT"><scalar type="int32_t"/><data-field-ref field-name-ref="RO_uint16"/></value-item><value-item name="RO_int16" direction="OUT"><scalar type="int16_t"/><data-field-ref field-name-ref="RO_int16"/></value-item><value-item name="RO_uint8" direction="OUT"><scalar type="int16_t"/><data-field-ref field-name-ref="RO_uint8"/></value-item><value-item name="RO_int8" direction="OUT"><scalar type="int8_t"/><data-field-ref field-name-ref="RO_int8"/></value-item><acq-stamp-item direction="OUT" name="acqStamp"><scalar type="int64_t"/></acq-stamp-item><update-flag-item direction="OUT" optional="true" name="updateFlags"><builtin-type-scalar data-type-name-ref="NOTIFICATION_UPDATE"/></update-flag-item><cycle-name-item direction="OUT" optional="true" name="cycleName"><array type="char"><dim>32</dim></array></cycle-name-item><cycle-stamp-item direction="OUT" optional="true" name="cycleStamp"><scalar type="int64_t"/></cycle-stamp-item><get-action><server-action-ref server-action-name-ref="GetMyROBlock"/></get-action><acquisition-context-item direction="OUT"><processIndex direction="OUT" name="processIndex"><scalar type="int32_t"/></processIndex><sequenceIndex direction="OUT" name="sequenceIndex"><scalar type="int32_t"/></sequenceIndex><chainIndex direction="OUT" name="chainIndex"><scalar type="int32_t"/></chainIndex><eventNumber direction="OUT" name="eventNumber"><scalar type="int32_t"/></eventNumber><timingGroupID direction="OUT" name="timingGroupID"><scalar type="int32_t"/></timingGroupID><acquisitionStamp direction="OUT" name="acquisitionStamp"><scalar type="int64_t"/></acquisitionStamp><eventStamp direction="OUT" name="eventStamp"><scalar type="int64_t"/></eventStamp><processStartStamp direction="OUT" name="processStartStamp"><scalar type="int64_t"/></processStartStamp><sequenceStartStamp direction="OUT" name="sequenceStartStamp"><scalar type="int64_t"/></sequenceStartStamp><chainStartStamp direction="OUT" name="chainStartStamp"><scalar type="int64_t"/></chainStartStamp><acquisition-context-field-ref field-name-ref="acquisitionContext"/></acquisition-context-item></GSI-Acquisition-Property><GSI-Version-Property multiplexed="false" name="Version" on-change="false" subscribable="false" visibility="operational">
+ <GSI-Acquisition-Property name="MyROBlockProp" subscribable="true" multiplexed="false" on-change="true" visibility="development"><value-item name="RO_dt_fesa" direction="OUT"><scalar type="double"/><data-field-ref field-name-ref="RO_dt_fesa"/></value-item><value-item name="RO_real_fesa" direction="OUT"><scalar type="float"/><data-field-ref field-name-ref="RO_real_fesa"/></value-item><value-item name="RO_dint_fesa" direction="OUT"><scalar type="int32_t"/><data-field-ref field-name-ref="RO_dint_fesa"/></value-item><value-item name="RO_int_fesa" direction="OUT"><scalar type="int16_t"/><data-field-ref field-name-ref="RO_int_fesa"/></value-item><value-item name="RO_dword_fesa" direction="OUT"><scalar type="int64_t"/><data-field-ref field-name-ref="RO_dword_fesa"/></value-item><value-item name="RO_word_fesa" direction="OUT"><scalar type="int32_t"/><data-field-ref field-name-ref="RO_word_fesa"/></value-item><value-item name="RO_byte_fesa" direction="OUT"><scalar type="int16_t"/><data-field-ref field-name-ref="RO_byte_fesa"/></value-item><value-item name="RO_char_fesa" direction="OUT"><scalar type="int8_t"/><data-field-ref field-name-ref="RO_char_fesa"/></value-item><value-item name="RO_date_fesa" direction="OUT"><scalar type="double"/><data-field-ref field-name-ref="RO_date_fesa"/></value-item><value-item name="RO_string_fesa" direction="OUT"><array type="char"><dim>64</dim></array><data-field-ref field-name-ref="RO_string_fesa"/></value-item><value-item name="RO_float32_fesa" direction="OUT"><scalar type="float"/><data-field-ref field-name-ref="RO_float32_fesa"/></value-item><value-item name="RO_uint32_fesa" direction="OUT"><scalar type="int64_t"/><data-field-ref field-name-ref="RO_uint32_fesa"/></value-item><value-item name="RO_int32_fesa" direction="OUT"><scalar type="int32_t"/><data-field-ref field-name-ref="RO_int32_fesa"/></value-item><value-item name="RO_uint16_fesa" direction="OUT"><scalar type="int32_t"/><data-field-ref field-name-ref="RO_uint16_fesa"/></value-item><value-item name="RO_int16_fesa" direction="OUT"><scalar type="int16_t"/><data-field-ref field-name-ref="RO_int16_fesa"/></value-item><value-item name="RO_uint8_fesa" direction="OUT"><scalar type="int16_t"/><data-field-ref field-name-ref="RO_uint8_fesa"/></value-item><value-item name="RO_int8" direction="OUT"><scalar type="int8_t"/><data-field-ref field-name-ref="RO_int8"/></value-item><acq-stamp-item direction="OUT" name="acqStamp"><scalar type="int64_t"/></acq-stamp-item><update-flag-item direction="OUT" optional="true" name="updateFlags"><builtin-type-scalar data-type-name-ref="NOTIFICATION_UPDATE"/></update-flag-item><cycle-name-item direction="OUT" optional="true" name="cycleName"><array type="char"><dim>32</dim></array></cycle-name-item><cycle-stamp-item direction="OUT" optional="true" name="cycleStamp"><scalar type="int64_t"/></cycle-stamp-item><get-action><server-action-ref server-action-name-ref="GetMyROBlockProp"/></get-action><acquisition-context-item direction="OUT"><processIndex direction="OUT" name="processIndex"><scalar type="int32_t"/></processIndex><sequenceIndex direction="OUT" name="sequenceIndex"><scalar type="int32_t"/></sequenceIndex><chainIndex direction="OUT" name="chainIndex"><scalar type="int32_t"/></chainIndex><eventNumber direction="OUT" name="eventNumber"><scalar type="int32_t"/></eventNumber><timingGroupID direction="OUT" name="timingGroupID"><scalar type="int32_t"/></timingGroupID><acquisitionStamp direction="OUT" name="acquisitionStamp"><scalar type="int64_t"/></acquisitionStamp><eventStamp direction="OUT" name="eventStamp"><scalar type="int64_t"/></eventStamp><processStartStamp direction="OUT" name="processStartStamp"><scalar type="int64_t"/></processStartStamp><sequenceStartStamp direction="OUT" name="sequenceStartStamp"><scalar type="int64_t"/></sequenceStartStamp><chainStartStamp direction="OUT" name="chainStartStamp"><scalar type="int64_t"/></chainStartStamp><acquisition-context-field-ref field-name-ref="acquisitionContext"/></acquisition-context-item></GSI-Acquisition-Property><GSI-Version-Property multiplexed="false" name="Version" on-change="false" subscribable="false" visibility="operational">
<acq-stamp-item direction="OUT" name="acqStamp">
<scalar type="int64_t"/>
</acq-stamp-item>
@@ -586,12 +586,12 @@
</GSI-module-status-labels-field>
</configuration>
<setting>
- <field name="WO_dt" shared="true" multiplexed="false" persistent="true"><array type="double"><dim>10</dim></array></field><field name="WO_real" shared="true" multiplexed="false" persistent="true"><array type="float"><dim>10</dim></array></field><field name="WO_dint" shared="true" multiplexed="false" persistent="true"><array type="int32_t"><dim>10</dim></array></field><field name="WO_int" shared="true" multiplexed="false" persistent="true"><array type="int16_t"><dim>10</dim></array></field><field name="WO_dword" shared="true" multiplexed="false" persistent="true"><array type="int64_t"><dim>10</dim></array></field><field name="WO_word" shared="true" multiplexed="false" persistent="true"><array type="int32_t"><dim>10</dim></array></field><field name="WO_byte" shared="true" multiplexed="false" persistent="true"><array type="int16_t"><dim>10</dim></array></field><field name="WO_char" shared="true" multiplexed="false" persistent="true"><array type="int8_t"><dim>10</dim></array></field><field name="WO_date" shared="true" multiplexed="false" persistent="true"><array type="double"><dim>10</dim></array></field><field name="WO_string" shared="true" multiplexed="false" persistent="true"><array2D type="char"><dim1>10</dim1><dim2>64</dim2></array2D></field><field name="WO_float32" shared="true" multiplexed="false" persistent="true"><array type="float"><dim>10</dim></array></field><field name="WO_uint32" shared="true" multiplexed="false" persistent="true"><array type="int64_t"><dim>10</dim></array></field><field name="WO_int32" shared="true" multiplexed="false" persistent="true"><array type="int32_t"><dim>10</dim></array></field><field name="WO_uint16" shared="true" multiplexed="false" persistent="true"><array type="int32_t"><dim>10</dim></array></field><field name="WO_int16" shared="true" multiplexed="false" persistent="true"><array type="int16_t"><dim>10</dim></array></field><field name="WO_uint8" shared="true" multiplexed="false" persistent="true"><array type="int16_t"><dim>10</dim></array></field><field name="WO_int8" shared="true" multiplexed="false" persistent="true"><array type="int8_t"><dim>10</dim></array></field><field name="RW_dt" multiplexed="false" persistent="true"><array2D type="double"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_real" multiplexed="false" persistent="true"><array2D type="float"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_dint" multiplexed="false" persistent="true"><array2D type="int32_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_int" multiplexed="false" persistent="true"><array2D type="int16_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_dword" multiplexed="false" persistent="true"><array2D type="int64_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_word" multiplexed="false" persistent="true"><array2D type="int32_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_byte" multiplexed="false" persistent="true"><array2D type="int16_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_char" multiplexed="false" persistent="true"><array2D type="int8_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_date" multiplexed="false" persistent="true"><array2D type="double"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_float32" multiplexed="false" persistent="true"><array2D type="float"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_uint32" multiplexed="false" persistent="true"><array2D type="int64_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_int32" multiplexed="false" persistent="true"><array2D type="int32_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_uint16" multiplexed="false" persistent="true"><array2D type="int32_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_int16" multiplexed="false" persistent="true"><array2D type="int16_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_uint8" multiplexed="false" persistent="true"><array2D type="int16_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_int8" multiplexed="false" persistent="true"><array2D type="int8_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><GSI-power-field multiplexed="false" name="power" persistent="false">
+ <field name="WO_dt_fesa" multiplexed="false" persistent="true"><array type="double"><dim>10</dim></array></field><field name="WO_real_fesa" multiplexed="false" persistent="true"><array type="float"><dim>10</dim></array></field><field name="WO_dint_fesa" multiplexed="false" persistent="true"><array type="int32_t"><dim>10</dim></array></field><field name="WO_int_fesa" multiplexed="false" persistent="true"><array type="int16_t"><dim>10</dim></array></field><field name="WO_dword_fesa" multiplexed="false" persistent="true"><array type="int64_t"><dim>10</dim></array></field><field name="WO_word_fesa" multiplexed="false" persistent="true"><array type="int32_t"><dim>10</dim></array></field><field name="WO_byte_fesa" multiplexed="false" persistent="true"><array type="int16_t"><dim>10</dim></array></field><field name="WO_char_fesa" multiplexed="false" persistent="true"><array type="int8_t"><dim>10</dim></array></field><field name="WO_date_fesa" multiplexed="false" persistent="true"><array type="double"><dim>10</dim></array></field><field name="WO_string_fesa" multiplexed="false" persistent="true"><array2D type="char"><dim1>10</dim1><dim2>64</dim2></array2D></field><field name="WO_float32_fesa" multiplexed="false" persistent="true"><array type="float"><dim>10</dim></array></field><field name="WO_uint32_fesa" multiplexed="false" persistent="true"><array type="int64_t"><dim>10</dim></array></field><field name="WO_int32_fesa" multiplexed="false" persistent="true"><array type="int32_t"><dim>10</dim></array></field><field name="WO_uint16_fesa" multiplexed="false" persistent="true"><array type="int32_t"><dim>10</dim></array></field><field name="WO_int16_fesa" multiplexed="false" persistent="true"><array type="int16_t"><dim>10</dim></array></field><field name="WO_uint8_fesa" multiplexed="false" persistent="true"><array type="int16_t"><dim>10</dim></array></field><field name="WO_int8" multiplexed="false" persistent="true"><array type="int8_t"><dim>10</dim></array></field><field name="RW_dt_fesa" multiplexed="false" persistent="false"><array2D type="double"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_real_fesa" multiplexed="false" persistent="false"><array2D type="float"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_dint_fesa" multiplexed="false" persistent="false"><array2D type="int32_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_int_fesa" multiplexed="false" persistent="false"><array2D type="int16_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_dword_fesa" multiplexed="false" persistent="false"><array2D type="int64_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_word_fesa" multiplexed="false" persistent="false"><array2D type="int32_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_byte_fesa" multiplexed="false" persistent="false"><array2D type="int16_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_char_fesa" multiplexed="false" persistent="false"><array2D type="int8_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_date_fesa" multiplexed="false" persistent="false"><array2D type="double"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_float32_fesa" multiplexed="false" persistent="false"><array2D type="float"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_uint32_fesa" multiplexed="false" persistent="false"><array2D type="int64_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_int32_fesa" multiplexed="false" persistent="false"><array2D type="int32_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_uint16_fesa" multiplexed="false" persistent="false"><array2D type="int32_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_int16_fesa" multiplexed="false" persistent="false"><array2D type="int16_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_uint8_fesa" multiplexed="false" persistent="false"><array2D type="int16_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><field name="RW_int8" multiplexed="false" persistent="false"><array2D type="int8_t"><dim1>2</dim1><dim2>2</dim2></array2D></field><GSI-power-field multiplexed="false" name="power" persistent="false">
<custom-type-scalar data-type-name-ref="DEVICE_POWER"/>
</GSI-power-field>
</setting>
<acquisition>
- <field name="RO_dt" multiplexed="false" persistent="false"><scalar type="double"/></field><field name="RO_real" multiplexed="false" persistent="false"><scalar type="float"/></field><field name="RO_dint" multiplexed="false" persistent="false"><scalar type="int32_t"/></field><field name="RO_int" multiplexed="false" persistent="false"><scalar type="int16_t"/></field><field name="RO_dword" multiplexed="false" persistent="false"><scalar type="int64_t"/></field><field name="RO_word" multiplexed="false" persistent="false"><scalar type="int32_t"/></field><field name="RO_byte" multiplexed="false" persistent="false"><scalar type="int16_t"/></field><field name="RO_char" multiplexed="false" persistent="false"><scalar type="int8_t"/></field><field name="RO_date" multiplexed="false" persistent="false"><scalar type="double"/></field><field name="RO_string" multiplexed="false" persistent="false"><array type="char"><dim>64</dim></array></field><field name="RO_float32" multiplexed="false" persistent="false"><scalar type="float"/></field><field name="RO_uint32" multiplexed="false" persistent="false"><scalar type="int64_t"/></field><field name="RO_int32" multiplexed="false" persistent="false"><scalar type="int32_t"/></field><field name="RO_uint16" multiplexed="false" persistent="false"><scalar type="int32_t"/></field><field name="RO_int16" multiplexed="false" persistent="false"><scalar type="int16_t"/></field><field name="RO_uint8" multiplexed="false" persistent="false"><scalar type="int16_t"/></field><field name="RO_int8" multiplexed="false" persistent="false"><scalar type="int8_t"/></field><GSI-control-field multiplexed="false" name="control">
+ <field name="RO_dt_fesa" multiplexed="false" persistent="false"><scalar type="double"/></field><field name="RO_real_fesa" multiplexed="false" persistent="false"><scalar type="float"/></field><field name="RO_dint_fesa" multiplexed="false" persistent="false"><scalar type="int32_t"/></field><field name="RO_int_fesa" multiplexed="false" persistent="false"><scalar type="int16_t"/></field><field name="RO_dword_fesa" multiplexed="false" persistent="false"><scalar type="int64_t"/></field><field name="RO_word_fesa" multiplexed="false" persistent="false"><scalar type="int32_t"/></field><field name="RO_byte_fesa" multiplexed="false" persistent="false"><scalar type="int16_t"/></field><field name="RO_char_fesa" multiplexed="false" persistent="false"><scalar type="int8_t"/></field><field name="RO_date_fesa" multiplexed="false" persistent="false"><scalar type="double"/></field><field name="RO_string_fesa" multiplexed="false" persistent="false"><array type="char"><dim>64</dim></array></field><field name="RO_float32_fesa" multiplexed="false" persistent="false"><scalar type="float"/></field><field name="RO_uint32_fesa" multiplexed="false" persistent="false"><scalar type="int64_t"/></field><field name="RO_int32_fesa" multiplexed="false" persistent="false"><scalar type="int32_t"/></field><field name="RO_uint16_fesa" multiplexed="false" persistent="false"><scalar type="int32_t"/></field><field name="RO_int16_fesa" multiplexed="false" persistent="false"><scalar type="int16_t"/></field><field name="RO_uint8_fesa" multiplexed="false" persistent="false"><scalar type="int16_t"/></field><field name="RO_int8" multiplexed="false" persistent="false"><scalar type="int8_t"/></field><GSI-control-field multiplexed="false" name="control">
<custom-type-scalar data-type-name-ref="DEVICE_CONTROL"/>
</GSI-control-field>
<GSI-powerState-field multiplexed="false" name="powerState">
@@ -652,6 +652,6 @@
<get-server-action implementation="default" name="AcquisitionGetAction"/>
<get-server-action implementation="default" name="StatusGetAction"/>
<get-server-action implementation="default" name="VersionGetAction"/><get-server-action implementation="default" name="ModuleStatusGetAction"/>
- <get-server-action name="GetMyROBlock" implementation="default"/><rt-action name="RecvMyROBlock"><notified-property property-name-ref="MyROBlock" automatic="true"/></rt-action><set-server-action name="SendMyRWBlock" implementation="custom"/><get-server-action name="RecvMyRWBlock" implementation="custom"/><set-server-action name="SendMyWOBlock" implementation="custom"/><get-server-action name="GetMyWOBlock" implementation="default"/></actions>
+ <get-server-action name="GetMyROBlockProp" implementation="custom"/><set-server-action name="SetMyRWBlockProp" implementation="custom"/><get-server-action name="GetMyRWBlockProp" implementation="custom"/><set-server-action name="SetMyWOBlockProp" implementation="custom"/><get-server-action name="GetMyWOBlockProp" implementation="custom"/></actions>
-<events><sources><timing-event-source name="Timing"/><timer-event-source name="Timer"/></sources><logical-events><logical-event name="RecvMyROBlockEvent" use="required" type="timer"/></logical-events></events><scheduling-units><scheduling-unit name="RecvMyROBlockUnit"><rt-action-ref rt-action-name-ref="RecvMyROBlock"/><logical-event-ref logical-event-name-ref="RecvMyROBlockEvent"/></scheduling-unit></scheduling-units></equipment-model>
+</equipment-model>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Beckhoff_BC9020.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Beckhoff_BC9020.silecsparam
index 79e434e40e353291d2ba2ef0a1ed7994c52660d0..ca98dcf2910ad4bcfcf5657ff549181471fb4393 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Beckhoff_BC9020.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Beckhoff_BC9020.silecsparam
@@ -2,77 +2,187 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 16:03:39.957252"/>
- <Deployment checksum="2843029646"/>
+ <Generation date="2017-06-08 16:28:46.858569"/>
+ <Deployment checksum="1037751963"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Beckhoff_BC9020" plc-brand="BECKHOFF" plc-system="TWINCat" plc-model="BC9020" protocol="BLOCK_MODE" address="32768" domain="NotUsed" used-mem="TODO">
- <SILECS-Class name="SilecsHeader" version="1.0.0" address="32768" used-mem="MW16384..MW16407 / 24 words">
- <Block name="hdrBlk" mode="READ-ONLY" size="14" address="32768" mem-size="48">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="17" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="18" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="22" mem-size="17" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="40" mem-size="8" synchro="MASTER"/>
- </Block>
+ <SILECS-Class name="SilecsHeader" version="1.0.0" address="32768" usedMemory="MW16384..MW16407 / 24 words">
+ <Acquisition-Block name="hdrBlk" size="14" address="32768" mem-size="48">
+ <Acquisition-Register name="_version" size="1" address="0" mem-size="17">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_checksum" size="4" address="18" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_user" size="1" address="22" mem-size="17">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_date" size="8" address="40" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
- <SILECS-Class name="AllTypes" version="0.1.0" address="32816" used-mem="MW16408..MW18167 / 1760 words">
- <Block name="MyROBlock" mode="READ-ONLY" size="53" address="32816" mem-size="122">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="1" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="2" mem-size="1" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="6" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="8" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="12" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="65" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="86" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="94" mem-size="1" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="96" mem-size="1" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="98" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="100" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="104" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="106" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="110" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="114" mem-size="8" synchro="MASTER"/>
- </Block>
- <Block name="MyRWBlock" mode="READ-WRITE" size="212" address="33060" mem-size="468">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="4" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="4" mem-size="4" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="8" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="16" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="24" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="40" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="56" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="72" mem-size="260" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="332" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="364" mem-size="4" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="368" mem-size="4" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="372" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="380" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="396" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="404" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="420" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="436" mem-size="32" synchro="MASTER"/>
- </Block>
- <Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="33996" mem-size="1170">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="10" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="20" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="40" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="60" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="100" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="140" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="180" mem-size="650" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="830" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="910" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="920" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="930" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="950" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="990" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1010" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1050" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1090" mem-size="80" synchro="SLAVE"/>
- </Block>
+ <SILECS-Class name="AllTypes" version="0.1.0" address="32816" usedMemory="MW16408..MW18167 / 1760 words">
+ <Acquisition-Block name="MyROBlock" size="53" address="32816" mem-size="122">
+ <Acquisition-Register name="RO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="1">
+ <scalar format="int8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint8" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="2" mem-size="1">
+ <scalar format="uint8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int16" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="int16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint16" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="6" mem-size="2">
+ <scalar format="uint16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int32" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="8" mem-size="4">
+ <scalar format="int32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint32" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="12" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_float32" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="16" mem-size="4">
+ <scalar format="float32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_string" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="20" mem-size="65">
+ <string string-length="64" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_date" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="86" mem-size="8">
+ <scalar format="date"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_char" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="94" mem-size="1">
+ <scalar format="char"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_byte" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="96" mem-size="1">
+ <scalar format="byte"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_word" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="98" mem-size="2">
+ <scalar format="word"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dword" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="100" mem-size="4">
+ <scalar format="dword"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="104" mem-size="2">
+ <scalar format="int"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dint" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="106" mem-size="4">
+ <scalar format="dint"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_real" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="110" mem-size="4">
+ <scalar format="real"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dt" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="114" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
+ <Setting-Block name="MyRWBlock" size="212" address="33060" mem-size="468">
+ <Volatile-Register name="RW_int8" generateFesaValueItem="true" size="1" address="0" mem-size="4">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint8" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="4" mem-size="4">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int16" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="8" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint16" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="16" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int32" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="24" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint32" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="40" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_float32" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="56" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_string" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="72" mem-size="260">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_date" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="332" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_char" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="364" mem-size="4">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_byte" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="368" mem-size="4">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_word" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="372" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dword" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="380" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="396" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dint" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="404" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_real" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="420" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dt" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="436" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Volatile-Register>
+ </Setting-Block>
+ <Command-Block name="MyWOBlock" size="530" address="33996" mem-size="1170">
+ <Setting-Register name="WO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="10">
+ <array dim="10" format="int8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint8" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="10" mem-size="10">
+ <array dim="10" format="uint8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int16" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="20" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint16" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="40" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int32" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="60" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint32" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="100" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_float32" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="140" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_string" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="180" mem-size="650">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Setting-Register>
+ <Setting-Register name="WO_date" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="830" mem-size="80">
+ <array dim="10" format="date"/>
+ </Setting-Register>
+ <Setting-Register name="WO_char" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="910" mem-size="10">
+ <array dim="10" format="char"/>
+ </Setting-Register>
+ <Setting-Register name="WO_byte" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="920" mem-size="10">
+ <array dim="10" format="byte"/>
+ </Setting-Register>
+ <Setting-Register name="WO_word" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="930" mem-size="20">
+ <array dim="10" format="word"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dword" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="950" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="990" mem-size="20">
+ <array dim="10" format="int"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dint" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1010" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Setting-Register>
+ <Setting-Register name="WO_real" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1050" mem-size="40">
+ <array dim="10" format="real"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dt" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1090" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Setting-Register>
+ </Command-Block>
<Instance label="testDevice1" address="0"/>
<Instance label="testDevice2" address="1"/>
</SILECS-Class>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Beckhoff_CX9020.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Beckhoff_CX9020.silecsparam
index 90d7bc27743b68dff869e77e160e6a6b0a11cf82..4fcb642236de6184edf5a11df540c371b19e7d55 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Beckhoff_CX9020.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Beckhoff_CX9020.silecsparam
@@ -2,77 +2,187 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 16:03:58.791145"/>
- <Deployment checksum="427563505"/>
+ <Generation date="2017-06-08 16:28:46.893890"/>
+ <Deployment checksum="2754857673"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Beckhoff_CX9020" plc-brand="BECKHOFF" plc-system="TWINCat" plc-model="CX9020" protocol="BLOCK_MODE" address="24576" domain="NotUsed" used-mem="TODO">
- <SILECS-Class name="SilecsHeader" version="1.0.0" address="24576" used-mem="MW12288..MW12313 / 26 words">
- <Block name="hdrBlk" mode="READ-ONLY" size="14" address="24576" mem-size="52">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="17" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="20" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="24" mem-size="17" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="44" mem-size="8" synchro="MASTER"/>
- </Block>
+ <SILECS-Class name="SilecsHeader" version="1.0.0" address="24576" usedMemory="MW12288..MW12313 / 26 words">
+ <Acquisition-Block name="hdrBlk" size="14" address="24576" mem-size="52">
+ <Acquisition-Register name="_version" size="1" address="0" mem-size="17">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_checksum" size="4" address="20" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_user" size="1" address="24" mem-size="17">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_date" size="8" address="44" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
- <SILECS-Class name="AllTypes" version="0.1.0" address="24628" used-mem="MW12314..MW14081 / 1768 words">
- <Block name="MyROBlock" mode="READ-ONLY" size="53" address="24628" mem-size="128">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="1" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="2" mem-size="1" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="6" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="8" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="12" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="65" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="88" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="96" mem-size="1" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="98" mem-size="1" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="100" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="104" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="108" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="112" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="116" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="120" mem-size="8" synchro="MASTER"/>
- </Block>
- <Block name="MyRWBlock" mode="READ-WRITE" size="212" address="24884" mem-size="468">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="4" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="4" mem-size="4" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="8" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="16" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="24" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="40" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="56" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="72" mem-size="260" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="332" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="364" mem-size="4" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="368" mem-size="4" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="372" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="380" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="396" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="404" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="420" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="436" mem-size="32" synchro="MASTER"/>
- </Block>
- <Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="25820" mem-size="1172">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="10" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="20" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="40" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="60" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="100" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="140" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="180" mem-size="650" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="832" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="912" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="922" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="932" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="952" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="992" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1012" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1052" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1092" mem-size="80" synchro="SLAVE"/>
- </Block>
+ <SILECS-Class name="AllTypes" version="0.1.0" address="24628" usedMemory="MW12314..MW14081 / 1768 words">
+ <Acquisition-Block name="MyROBlock" size="53" address="24628" mem-size="128">
+ <Acquisition-Register name="RO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="1">
+ <scalar format="int8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint8" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="2" mem-size="1">
+ <scalar format="uint8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int16" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="int16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint16" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="6" mem-size="2">
+ <scalar format="uint16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int32" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="8" mem-size="4">
+ <scalar format="int32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint32" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="12" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_float32" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="16" mem-size="4">
+ <scalar format="float32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_string" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="20" mem-size="65">
+ <string string-length="64" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_date" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="88" mem-size="8">
+ <scalar format="date"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_char" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="96" mem-size="1">
+ <scalar format="char"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_byte" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="98" mem-size="1">
+ <scalar format="byte"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_word" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="100" mem-size="2">
+ <scalar format="word"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dword" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="104" mem-size="4">
+ <scalar format="dword"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="108" mem-size="2">
+ <scalar format="int"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dint" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="112" mem-size="4">
+ <scalar format="dint"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_real" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="116" mem-size="4">
+ <scalar format="real"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dt" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="120" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
+ <Setting-Block name="MyRWBlock" size="212" address="24884" mem-size="468">
+ <Volatile-Register name="RW_int8" generateFesaValueItem="true" size="1" address="0" mem-size="4">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint8" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="4" mem-size="4">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int16" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="8" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint16" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="16" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int32" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="24" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint32" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="40" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_float32" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="56" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_string" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="72" mem-size="260">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_date" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="332" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_char" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="364" mem-size="4">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_byte" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="368" mem-size="4">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_word" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="372" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dword" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="380" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="396" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dint" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="404" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_real" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="420" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dt" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="436" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Volatile-Register>
+ </Setting-Block>
+ <Command-Block name="MyWOBlock" size="530" address="25820" mem-size="1172">
+ <Setting-Register name="WO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="10">
+ <array dim="10" format="int8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint8" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="10" mem-size="10">
+ <array dim="10" format="uint8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int16" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="20" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint16" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="40" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int32" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="60" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint32" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="100" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_float32" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="140" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_string" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="180" mem-size="650">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Setting-Register>
+ <Setting-Register name="WO_date" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="832" mem-size="80">
+ <array dim="10" format="date"/>
+ </Setting-Register>
+ <Setting-Register name="WO_char" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="912" mem-size="10">
+ <array dim="10" format="char"/>
+ </Setting-Register>
+ <Setting-Register name="WO_byte" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="922" mem-size="10">
+ <array dim="10" format="byte"/>
+ </Setting-Register>
+ <Setting-Register name="WO_word" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="932" mem-size="20">
+ <array dim="10" format="word"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dword" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="952" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="992" mem-size="20">
+ <array dim="10" format="int"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dint" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1012" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Setting-Register>
+ <Setting-Register name="WO_real" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1052" mem-size="40">
+ <array dim="10" format="real"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dt" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1092" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Setting-Register>
+ </Command-Block>
<Instance label="testDevice1" address="0"/>
<Instance label="testDevice2" address="1"/>
</SILECS-Class>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Rabbit_BlockMode.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Rabbit_BlockMode.silecsparam
index f213b467592a8037d13ad4d9b9c351ecdf82ab86..023db86ce5c829c5179fe90b891ed3aebc947875 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Rabbit_BlockMode.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Rabbit_BlockMode.silecsparam
@@ -2,77 +2,187 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 16:04:28.617415"/>
- <Deployment checksum="3940683809"/>
+ <Generation date="2017-06-08 16:28:47.039562"/>
+ <Deployment checksum="308863231"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Rabbit_BlockMode" plc-brand="DIGI" plc-system="Standard-C" plc-model="Rabbit_RCM_4010" protocol="BLOCK_MODE" address="0" domain="NotUsed" used-mem="TODO">
- <SILECS-Class name="SilecsHeader" version="1.0.0" address="0" used-mem="MW0..MW21 / 22 words">
- <Block name="hdrBlk" mode="READ-ONLY" size="14" address="0" mem-size="44">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="16" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="16" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="36" mem-size="8" synchro="MASTER"/>
- </Block>
+ <SILECS-Class name="SilecsHeader" version="1.0.0" address="0" usedMemory="MW0..MW21 / 22 words">
+ <Acquisition-Block name="hdrBlk" size="14" address="0" mem-size="44">
+ <Acquisition-Register name="_version" size="1" address="0" mem-size="16">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_checksum" size="4" address="16" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_user" size="1" address="20" mem-size="16">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_date" size="8" address="36" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
- <SILECS-Class name="AllTypes" version="0.1.0" address="44" used-mem="MW22..MW1821 / 1800 words">
- <Block name="MyROBlock" mode="READ-ONLY" size="53" address="44" mem-size="120">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="2" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="6" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="8" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="12" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="64" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="84" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="92" mem-size="2" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="94" mem-size="2" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="96" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="98" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="102" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="104" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="108" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="112" mem-size="8" synchro="MASTER"/>
- </Block>
- <Block name="MyRWBlock" mode="READ-WRITE" size="212" address="284" mem-size="480">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="8" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="16" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="24" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="32" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="48" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="64" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="80" mem-size="256" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="336" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="368" mem-size="8" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="376" mem-size="8" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="384" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="392" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="408" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="416" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="432" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="448" mem-size="32" synchro="MASTER"/>
- </Block>
- <Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="1244" mem-size="1200">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="20" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="40" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="60" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="80" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="120" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="160" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="200" mem-size="640" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="840" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="920" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="940" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="960" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="980" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="1020" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1040" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1080" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1120" mem-size="80" synchro="SLAVE"/>
- </Block>
+ <SILECS-Class name="AllTypes" version="0.1.0" address="44" usedMemory="MW22..MW1821 / 1800 words">
+ <Acquisition-Block name="MyROBlock" size="53" address="44" mem-size="120">
+ <Acquisition-Register name="RO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="2">
+ <scalar format="int8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint8" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="2" mem-size="2">
+ <scalar format="uint8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int16" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="int16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint16" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="6" mem-size="2">
+ <scalar format="uint16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int32" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="8" mem-size="4">
+ <scalar format="int32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint32" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="12" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_float32" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="16" mem-size="4">
+ <scalar format="float32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_string" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="20" mem-size="64">
+ <string string-length="64" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_date" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="84" mem-size="8">
+ <scalar format="date"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_char" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="92" mem-size="2">
+ <scalar format="char"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_byte" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="94" mem-size="2">
+ <scalar format="byte"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_word" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="96" mem-size="2">
+ <scalar format="word"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dword" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="98" mem-size="4">
+ <scalar format="dword"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="102" mem-size="2">
+ <scalar format="int"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dint" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="104" mem-size="4">
+ <scalar format="dint"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_real" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="108" mem-size="4">
+ <scalar format="real"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dt" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="112" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
+ <Setting-Block name="MyRWBlock" size="212" address="284" mem-size="480">
+ <Volatile-Register name="RW_int8" generateFesaValueItem="true" size="1" address="0" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint8" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="8" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int16" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="16" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint16" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="24" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int32" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="32" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint32" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="48" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_float32" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="64" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_string" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="80" mem-size="256">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_date" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="336" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_char" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="368" mem-size="8">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_byte" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="376" mem-size="8">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_word" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="384" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dword" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="392" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="408" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dint" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="416" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_real" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="432" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dt" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="448" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Volatile-Register>
+ </Setting-Block>
+ <Command-Block name="MyWOBlock" size="530" address="1244" mem-size="1200">
+ <Setting-Register name="WO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="20">
+ <array dim="10" format="int8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint8" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="20" mem-size="20">
+ <array dim="10" format="uint8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int16" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="40" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint16" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="60" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int32" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="80" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint32" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="120" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_float32" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="160" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_string" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="200" mem-size="640">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Setting-Register>
+ <Setting-Register name="WO_date" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="840" mem-size="80">
+ <array dim="10" format="date"/>
+ </Setting-Register>
+ <Setting-Register name="WO_char" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="920" mem-size="20">
+ <array dim="10" format="char"/>
+ </Setting-Register>
+ <Setting-Register name="WO_byte" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="940" mem-size="20">
+ <array dim="10" format="byte"/>
+ </Setting-Register>
+ <Setting-Register name="WO_word" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="960" mem-size="20">
+ <array dim="10" format="word"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dword" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="980" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="1020" mem-size="20">
+ <array dim="10" format="int"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dint" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1040" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Setting-Register>
+ <Setting-Register name="WO_real" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1080" mem-size="40">
+ <array dim="10" format="real"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dt" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1120" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Setting-Register>
+ </Command-Block>
<Instance label="testDevice1" address="0"/>
<Instance label="testDevice2" address="1"/>
</SILECS-Class>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Rabbit_DeviceMode.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Rabbit_DeviceMode.silecsparam
index 73cbd938e5446cdc22fd94a3edf000b06608ebd6..62778b069921ddc86a1cdd60149b7d0015fb8b57 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Rabbit_DeviceMode.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Rabbit_DeviceMode.silecsparam
@@ -2,77 +2,187 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 16:04:38.516577"/>
- <Deployment checksum="3940683809"/>
+ <Generation date="2017-06-08 16:28:47.005686"/>
+ <Deployment checksum="308863231"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Rabbit_DeviceMode" plc-brand="DIGI" plc-system="Standard-C" plc-model="Rabbit_RCM_4010" protocol="DEVICE_MODE" address="0" domain="NotUsed" used-mem="TODO">
- <SILECS-Class name="SilecsHeader" version="1.0.0" address="0" used-mem="MW0..MW21 / 22 words">
- <Block name="hdrBlk" mode="READ-ONLY" size="14" address="0" mem-size="44">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="16" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="16" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="36" mem-size="8" synchro="MASTER"/>
- </Block>
+ <SILECS-Class name="SilecsHeader" version="1.0.0" address="0" usedMemory="MW0..MW21 / 22 words">
+ <Acquisition-Block name="hdrBlk" size="14" address="0" mem-size="44">
+ <Acquisition-Register name="_version" size="1" address="0" mem-size="16">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_checksum" size="4" address="16" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_user" size="1" address="20" mem-size="16">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_date" size="8" address="36" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
- <SILECS-Class name="AllTypes" version="0.1.0" address="44" used-mem="MW22..MW1821 / 1800 words">
- <Block name="MyROBlock" mode="READ-ONLY" size="53" address="0" mem-size="120">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="2" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="6" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="8" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="12" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="64" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="84" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="92" mem-size="2" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="94" mem-size="2" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="96" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="98" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="102" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="104" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="108" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="112" mem-size="8" synchro="MASTER"/>
- </Block>
- <Block name="MyRWBlock" mode="READ-WRITE" size="212" address="120" mem-size="480">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="8" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="16" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="24" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="32" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="48" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="64" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="80" mem-size="256" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="336" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="368" mem-size="8" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="376" mem-size="8" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="384" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="392" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="408" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="416" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="432" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="448" mem-size="32" synchro="MASTER"/>
- </Block>
- <Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="600" mem-size="1200">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="20" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="40" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="60" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="80" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="120" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="160" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="200" mem-size="640" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="840" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="920" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="940" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="960" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="980" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="1020" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1040" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1080" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1120" mem-size="80" synchro="SLAVE"/>
- </Block>
+ <SILECS-Class name="AllTypes" version="0.1.0" address="44" usedMemory="MW22..MW1821 / 1800 words">
+ <Acquisition-Block name="MyROBlock" size="53" address="0" mem-size="120">
+ <Acquisition-Register name="RO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="2">
+ <scalar format="int8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint8" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="2" mem-size="2">
+ <scalar format="uint8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int16" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="int16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint16" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="6" mem-size="2">
+ <scalar format="uint16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int32" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="8" mem-size="4">
+ <scalar format="int32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint32" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="12" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_float32" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="16" mem-size="4">
+ <scalar format="float32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_string" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="20" mem-size="64">
+ <string string-length="64" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_date" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="84" mem-size="8">
+ <scalar format="date"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_char" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="92" mem-size="2">
+ <scalar format="char"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_byte" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="94" mem-size="2">
+ <scalar format="byte"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_word" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="96" mem-size="2">
+ <scalar format="word"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dword" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="98" mem-size="4">
+ <scalar format="dword"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="102" mem-size="2">
+ <scalar format="int"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dint" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="104" mem-size="4">
+ <scalar format="dint"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_real" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="108" mem-size="4">
+ <scalar format="real"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dt" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="112" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
+ <Setting-Block name="MyRWBlock" size="212" address="120" mem-size="480">
+ <Volatile-Register name="RW_int8" generateFesaValueItem="true" size="1" address="0" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint8" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="8" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int16" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="16" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint16" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="24" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int32" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="32" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint32" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="48" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_float32" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="64" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_string" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="80" mem-size="256">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_date" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="336" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_char" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="368" mem-size="8">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_byte" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="376" mem-size="8">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_word" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="384" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dword" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="392" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="408" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dint" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="416" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_real" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="432" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dt" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="448" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Volatile-Register>
+ </Setting-Block>
+ <Command-Block name="MyWOBlock" size="530" address="600" mem-size="1200">
+ <Setting-Register name="WO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="20">
+ <array dim="10" format="int8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint8" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="20" mem-size="20">
+ <array dim="10" format="uint8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int16" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="40" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint16" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="60" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int32" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="80" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint32" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="120" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_float32" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="160" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_string" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="200" mem-size="640">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Setting-Register>
+ <Setting-Register name="WO_date" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="840" mem-size="80">
+ <array dim="10" format="date"/>
+ </Setting-Register>
+ <Setting-Register name="WO_char" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="920" mem-size="20">
+ <array dim="10" format="char"/>
+ </Setting-Register>
+ <Setting-Register name="WO_byte" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="940" mem-size="20">
+ <array dim="10" format="byte"/>
+ </Setting-Register>
+ <Setting-Register name="WO_word" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="960" mem-size="20">
+ <array dim="10" format="word"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dword" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="980" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="1020" mem-size="20">
+ <array dim="10" format="int"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dint" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1040" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Setting-Register>
+ <Setting-Register name="WO_real" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1080" mem-size="40">
+ <array dim="10" format="real"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dt" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1120" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Setting-Register>
+ </Command-Block>
<Instance label="testDevice1" address="44"/>
<Instance label="testDevice2" address="1844"/>
</SILECS-Class>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Schneider_M340.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Schneider_M340.silecsparam
index 1ea96e043c8ea9ab9ea8f56c417ae3d4faa0842e..f46258a6a501e76d7cd084f58ea86e6787bb6475 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Schneider_M340.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Schneider_M340.silecsparam
@@ -2,77 +2,187 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 16:04:09.437778"/>
- <Deployment checksum="3940683809"/>
+ <Generation date="2017-06-08 16:28:46.968837"/>
+ <Deployment checksum="308863231"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Schneider_M340" plc-brand="SCHNEIDER" plc-system="UNITY Pro" plc-model="M340" protocol="BLOCK_MODE" address="0" domain="NotUsed" used-mem="TODO">
- <SILECS-Class name="SilecsHeader" version="1.0.0" address="0" used-mem="MW0..MW21 / 22 words">
- <Block name="hdrBlk" mode="READ-ONLY" size="14" address="0" mem-size="44">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="16" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="16" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="36" mem-size="8" synchro="MASTER"/>
- </Block>
+ <SILECS-Class name="SilecsHeader" version="1.0.0" address="0" usedMemory="MW0..MW21 / 22 words">
+ <Acquisition-Block name="hdrBlk" size="14" address="0" mem-size="44">
+ <Acquisition-Register name="_version" size="1" address="0" mem-size="16">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_checksum" size="4" address="16" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_user" size="1" address="20" mem-size="16">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_date" size="8" address="36" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
- <SILECS-Class name="AllTypes" version="0.1.0" address="44" used-mem="MW22..MW1801 / 1780 words">
- <Block name="MyROBlock" mode="READ-ONLY" size="53" address="44" mem-size="124">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="2" mem-size="1" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="6" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="8" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="12" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="64" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="84" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="92" mem-size="2" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="94" mem-size="1" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="96" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="100" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="104" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="108" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="112" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="116" mem-size="8" synchro="MASTER"/>
- </Block>
- <Block name="MyRWBlock" mode="READ-WRITE" size="212" address="292" mem-size="472">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="8" mem-size="4" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="12" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="20" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="28" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="44" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="60" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="76" mem-size="256" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="332" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="364" mem-size="8" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="372" mem-size="4" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="376" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="384" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="400" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="408" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="424" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="440" mem-size="32" synchro="MASTER"/>
- </Block>
- <Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="1236" mem-size="1184">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="20" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="30" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="50" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="72" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="112" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="152" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="192" mem-size="640" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="832" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="912" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="932" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="942" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="964" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="1004" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1024" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1064" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1104" mem-size="80" synchro="SLAVE"/>
- </Block>
+ <SILECS-Class name="AllTypes" version="0.1.0" address="44" usedMemory="MW22..MW1801 / 1780 words">
+ <Acquisition-Block name="MyROBlock" size="53" address="44" mem-size="124">
+ <Acquisition-Register name="RO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="2">
+ <scalar format="int8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint8" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="2" mem-size="1">
+ <scalar format="uint8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int16" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="int16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint16" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="6" mem-size="2">
+ <scalar format="uint16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int32" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="8" mem-size="4">
+ <scalar format="int32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint32" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="12" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_float32" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="16" mem-size="4">
+ <scalar format="float32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_string" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="20" mem-size="64">
+ <string string-length="64" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_date" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="84" mem-size="8">
+ <scalar format="date"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_char" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="92" mem-size="2">
+ <scalar format="char"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_byte" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="94" mem-size="1">
+ <scalar format="byte"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_word" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="96" mem-size="2">
+ <scalar format="word"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dword" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="100" mem-size="4">
+ <scalar format="dword"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="104" mem-size="2">
+ <scalar format="int"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dint" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="108" mem-size="4">
+ <scalar format="dint"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_real" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="112" mem-size="4">
+ <scalar format="real"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dt" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="116" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
+ <Setting-Block name="MyRWBlock" size="212" address="292" mem-size="472">
+ <Volatile-Register name="RW_int8" generateFesaValueItem="true" size="1" address="0" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint8" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="8" mem-size="4">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int16" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="12" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint16" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="20" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int32" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="28" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint32" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="44" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_float32" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="60" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_string" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="76" mem-size="256">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_date" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="332" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_char" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="364" mem-size="8">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_byte" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="372" mem-size="4">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_word" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="376" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dword" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="384" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="400" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dint" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="408" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_real" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="424" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dt" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="440" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Volatile-Register>
+ </Setting-Block>
+ <Command-Block name="MyWOBlock" size="530" address="1236" mem-size="1184">
+ <Setting-Register name="WO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="20">
+ <array dim="10" format="int8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint8" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="20" mem-size="10">
+ <array dim="10" format="uint8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int16" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="30" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint16" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="50" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int32" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="72" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint32" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="112" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_float32" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="152" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_string" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="192" mem-size="640">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Setting-Register>
+ <Setting-Register name="WO_date" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="832" mem-size="80">
+ <array dim="10" format="date"/>
+ </Setting-Register>
+ <Setting-Register name="WO_char" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="912" mem-size="20">
+ <array dim="10" format="char"/>
+ </Setting-Register>
+ <Setting-Register name="WO_byte" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="932" mem-size="10">
+ <array dim="10" format="byte"/>
+ </Setting-Register>
+ <Setting-Register name="WO_word" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="942" mem-size="20">
+ <array dim="10" format="word"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dword" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="964" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="1004" mem-size="20">
+ <array dim="10" format="int"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dint" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1024" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Setting-Register>
+ <Setting-Register name="WO_real" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1064" mem-size="40">
+ <array dim="10" format="real"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dt" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1104" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Setting-Register>
+ </Command-Block>
<Instance label="testDevice1" address="0"/>
<Instance label="testDevice2" address="1"/>
</SILECS-Class>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Schneider_PremiumQuantum.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Schneider_PremiumQuantum.silecsparam
index 0e904f07e7c59035237e3f7c681c82fcfeacb287..6c0873bb380d0b9d046f082c0d72fe1a13aa285a 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Schneider_PremiumQuantum.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Schneider_PremiumQuantum.silecsparam
@@ -2,77 +2,187 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 16:04:19.735644"/>
- <Deployment checksum="3940683809"/>
+ <Generation date="2017-06-08 16:28:46.931934"/>
+ <Deployment checksum="308863231"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Schneider_PremiumQuantum" plc-brand="SCHNEIDER" plc-system="UNITY Pro" plc-model="Premium" protocol="BLOCK_MODE" address="0" domain="NotUsed" used-mem="TODO">
- <SILECS-Class name="SilecsHeader" version="1.0.0" address="0" used-mem="MW0..MW21 / 22 words">
- <Block name="hdrBlk" mode="READ-ONLY" size="14" address="0" mem-size="44">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="16" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="16" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="36" mem-size="8" synchro="MASTER"/>
- </Block>
+ <SILECS-Class name="SilecsHeader" version="1.0.0" address="0" usedMemory="MW0..MW21 / 22 words">
+ <Acquisition-Block name="hdrBlk" size="14" address="0" mem-size="44">
+ <Acquisition-Register name="_version" size="1" address="0" mem-size="16">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_checksum" size="4" address="16" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_user" size="1" address="20" mem-size="16">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_date" size="8" address="36" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
- <SILECS-Class name="AllTypes" version="0.1.0" address="44" used-mem="MW22..MW1793 / 1772 words">
- <Block name="MyROBlock" mode="READ-ONLY" size="53" address="44" mem-size="120">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="2" mem-size="1" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="6" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="8" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="12" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="16" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="20" mem-size="64" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="84" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="92" mem-size="2" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="94" mem-size="1" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="96" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="98" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="102" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="104" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="108" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="112" mem-size="8" synchro="MASTER"/>
- </Block>
- <Block name="MyRWBlock" mode="READ-WRITE" size="212" address="284" mem-size="472">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="8" mem-size="4" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="12" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="20" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="28" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="44" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="60" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="76" mem-size="256" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="332" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="364" mem-size="8" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="372" mem-size="4" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="376" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="384" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="400" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="408" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="424" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="440" mem-size="32" synchro="MASTER"/>
- </Block>
- <Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="1228" mem-size="1180">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="20" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="30" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="50" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="70" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="110" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="150" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="190" mem-size="640" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="830" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="910" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="930" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="940" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="960" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="1000" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1020" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1060" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1100" mem-size="80" synchro="SLAVE"/>
- </Block>
+ <SILECS-Class name="AllTypes" version="0.1.0" address="44" usedMemory="MW22..MW1793 / 1772 words">
+ <Acquisition-Block name="MyROBlock" size="53" address="44" mem-size="120">
+ <Acquisition-Register name="RO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="2">
+ <scalar format="int8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint8" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="2" mem-size="1">
+ <scalar format="uint8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int16" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="int16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint16" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="6" mem-size="2">
+ <scalar format="uint16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int32" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="8" mem-size="4">
+ <scalar format="int32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint32" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="12" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_float32" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="16" mem-size="4">
+ <scalar format="float32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_string" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="20" mem-size="64">
+ <string string-length="64" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_date" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="84" mem-size="8">
+ <scalar format="date"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_char" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="92" mem-size="2">
+ <scalar format="char"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_byte" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="94" mem-size="1">
+ <scalar format="byte"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_word" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="96" mem-size="2">
+ <scalar format="word"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dword" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="98" mem-size="4">
+ <scalar format="dword"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="102" mem-size="2">
+ <scalar format="int"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dint" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="104" mem-size="4">
+ <scalar format="dint"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_real" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="108" mem-size="4">
+ <scalar format="real"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dt" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="112" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
+ <Setting-Block name="MyRWBlock" size="212" address="284" mem-size="472">
+ <Volatile-Register name="RW_int8" generateFesaValueItem="true" size="1" address="0" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint8" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="8" mem-size="4">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int16" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="12" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint16" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="20" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int32" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="28" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint32" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="44" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_float32" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="60" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_string" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="76" mem-size="256">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_date" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="332" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_char" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="364" mem-size="8">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_byte" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="372" mem-size="4">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_word" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="376" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dword" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="384" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="400" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dint" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="408" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_real" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="424" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dt" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="440" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Volatile-Register>
+ </Setting-Block>
+ <Command-Block name="MyWOBlock" size="530" address="1228" mem-size="1180">
+ <Setting-Register name="WO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="20">
+ <array dim="10" format="int8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint8" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="20" mem-size="10">
+ <array dim="10" format="uint8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int16" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="30" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint16" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="50" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int32" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="70" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint32" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="110" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_float32" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="150" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_string" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="190" mem-size="640">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Setting-Register>
+ <Setting-Register name="WO_date" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="830" mem-size="80">
+ <array dim="10" format="date"/>
+ </Setting-Register>
+ <Setting-Register name="WO_char" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="910" mem-size="20">
+ <array dim="10" format="char"/>
+ </Setting-Register>
+ <Setting-Register name="WO_byte" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="930" mem-size="10">
+ <array dim="10" format="byte"/>
+ </Setting-Register>
+ <Setting-Register name="WO_word" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="940" mem-size="20">
+ <array dim="10" format="word"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dword" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="960" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="1000" mem-size="20">
+ <array dim="10" format="int"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dint" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1020" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Setting-Register>
+ <Setting-Register name="WO_real" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1060" mem-size="40">
+ <array dim="10" format="real"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dt" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1100" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Setting-Register>
+ </Command-Block>
<Instance label="testDevice1" address="0"/>
<Instance label="testDevice2" address="1"/>
</SILECS-Class>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Siemens_Step7Block.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Siemens_Step7Block.silecsparam
index 8182e9e37eb4180a7a04cc04f42152d391623375..857d51b7073f220520b8563a439be31a5c55d5e8 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Siemens_Step7Block.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Siemens_Step7Block.silecsparam
@@ -2,77 +2,187 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 16:03:31.706052"/>
- <Deployment checksum="3940683809"/>
+ <Generation date="2017-06-08 16:28:46.708946"/>
+ <Deployment checksum="308863231"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Siemens_Step7Block" plc-brand="SIEMENS" plc-system="STEP-7" plc-model="SIMATIC_S7-300" protocol="DEVICE_MODE" address="0" domain="NotUsed" used-mem="TODO">
- <SILECS-Class name="SilecsHeader" version="1.0.0" address="0" used-mem="DB0..DB0 / 48 bytes">
- <Block name="hdrBlk" mode="READ-ONLY" size="14" address="0" mem-size="48">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="18" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="18" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="22" mem-size="18" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="40" mem-size="8" synchro="MASTER"/>
- </Block>
+ <SILECS-Class name="SilecsHeader" version="1.0.0" address="0" usedMemory="DB0..DB0 / 48 bytes">
+ <Acquisition-Block name="hdrBlk" size="14" address="0" mem-size="48">
+ <Acquisition-Register name="_version" size="1" address="0" mem-size="18">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_checksum" size="4" address="18" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_user" size="1" address="22" mem-size="18">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_date" size="8" address="40" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
- <SILECS-Class name="AllTypes" version="0.1.0" address="1" used-mem="DB1..DB2 / 3540 bytes">
- <Block name="MyROBlock" mode="READ-ONLY" size="53" address="0" mem-size="118">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="1" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="1" mem-size="1" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="2" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="6" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="10" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="14" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="18" mem-size="66" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="84" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="92" mem-size="1" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="93" mem-size="1" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="94" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="96" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="100" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="102" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="106" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="110" mem-size="8" synchro="MASTER"/>
- </Block>
- <Block name="MyRWBlock" mode="READ-WRITE" size="212" address="118" mem-size="472">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="4" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="4" mem-size="4" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="8" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="16" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="24" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="40" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="56" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="72" mem-size="264" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="336" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="368" mem-size="4" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="372" mem-size="4" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="376" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="384" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="400" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="408" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="424" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="440" mem-size="32" synchro="MASTER"/>
- </Block>
- <Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="590" mem-size="1180">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="10" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="20" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="40" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="60" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="100" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="140" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="180" mem-size="660" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="840" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="920" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="930" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="940" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="960" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="1000" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1020" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1060" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1100" mem-size="80" synchro="SLAVE"/>
- </Block>
+ <SILECS-Class name="AllTypes" version="0.1.0" address="1" usedMemory="DB1..DB2 / 3540 bytes">
+ <Acquisition-Block name="MyROBlock" size="53" address="0" mem-size="118">
+ <Acquisition-Register name="RO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="1">
+ <scalar format="int8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint8" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="1" mem-size="1">
+ <scalar format="uint8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int16" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="2" mem-size="2">
+ <scalar format="int16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint16" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="uint16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int32" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="6" mem-size="4">
+ <scalar format="int32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint32" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="10" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_float32" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="14" mem-size="4">
+ <scalar format="float32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_string" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="18" mem-size="66">
+ <string string-length="64" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_date" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="84" mem-size="8">
+ <scalar format="date"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_char" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="92" mem-size="1">
+ <scalar format="char"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_byte" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="93" mem-size="1">
+ <scalar format="byte"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_word" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="94" mem-size="2">
+ <scalar format="word"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dword" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="96" mem-size="4">
+ <scalar format="dword"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="100" mem-size="2">
+ <scalar format="int"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dint" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="102" mem-size="4">
+ <scalar format="dint"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_real" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="106" mem-size="4">
+ <scalar format="real"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dt" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="110" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
+ <Setting-Block name="MyRWBlock" size="212" address="118" mem-size="472">
+ <Volatile-Register name="RW_int8" generateFesaValueItem="true" size="1" address="0" mem-size="4">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint8" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="4" mem-size="4">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int16" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="8" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint16" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="16" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int32" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="24" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint32" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="40" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_float32" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="56" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_string" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="72" mem-size="264">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_date" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="336" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_char" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="368" mem-size="4">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_byte" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="372" mem-size="4">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_word" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="376" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dword" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="384" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="400" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dint" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="408" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_real" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="424" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dt" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="440" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Volatile-Register>
+ </Setting-Block>
+ <Command-Block name="MyWOBlock" size="530" address="590" mem-size="1180">
+ <Setting-Register name="WO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="10">
+ <array dim="10" format="int8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint8" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="10" mem-size="10">
+ <array dim="10" format="uint8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int16" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="20" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint16" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="40" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int32" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="60" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint32" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="100" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_float32" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="140" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_string" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="180" mem-size="660">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Setting-Register>
+ <Setting-Register name="WO_date" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="840" mem-size="80">
+ <array dim="10" format="date"/>
+ </Setting-Register>
+ <Setting-Register name="WO_char" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="920" mem-size="10">
+ <array dim="10" format="char"/>
+ </Setting-Register>
+ <Setting-Register name="WO_byte" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="930" mem-size="10">
+ <array dim="10" format="byte"/>
+ </Setting-Register>
+ <Setting-Register name="WO_word" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="940" mem-size="20">
+ <array dim="10" format="word"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dword" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="960" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="1000" mem-size="20">
+ <array dim="10" format="int"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dint" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1020" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Setting-Register>
+ <Setting-Register name="WO_real" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1060" mem-size="40">
+ <array dim="10" format="real"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dt" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1100" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Setting-Register>
+ </Command-Block>
<Instance label="testDevice1" address="1"/>
<Instance label="testDevice2" address="2"/>
</SILECS-Class>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Siemens_Step7Device.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Siemens_Step7Device.silecsparam
index 46bf195eae0ebb7cb9f3c0c47b46ecaf9233d8e7..6ae45a184b3224eb6bb845ce28e4864d10633834 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Siemens_Step7Device.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Siemens_Step7Device.silecsparam
@@ -2,77 +2,187 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 16:03:18.892092"/>
- <Deployment checksum="3940683809"/>
+ <Generation date="2017-06-08 16:28:46.747628"/>
+ <Deployment checksum="308863231"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Siemens_Step7Device" plc-brand="SIEMENS" plc-system="STEP-7" plc-model="SIMATIC_S7-300" protocol="BLOCK_MODE" address="0" domain="NotUsed" used-mem="TODO">
- <SILECS-Class name="SilecsHeader" version="1.0.0" address="0" used-mem="DB0..DB0 / 48 bytes">
- <Block name="hdrBlk" mode="READ-ONLY" size="14" address="0" mem-size="48">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="18" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="18" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="22" mem-size="18" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="40" mem-size="8" synchro="MASTER"/>
- </Block>
+ <SILECS-Class name="SilecsHeader" version="1.0.0" address="0" usedMemory="DB0..DB0 / 48 bytes">
+ <Acquisition-Block name="hdrBlk" size="14" address="0" mem-size="48">
+ <Acquisition-Register name="_version" size="1" address="0" mem-size="18">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_checksum" size="4" address="18" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_user" size="1" address="22" mem-size="18">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_date" size="8" address="40" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
- <SILECS-Class name="AllTypes" version="0.1.0" address="1" used-mem="DB1..DB3 / 3540 bytes">
- <Block name="MyROBlock" mode="READ-ONLY" size="53" address="1" mem-size="118">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="1" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="1" mem-size="1" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="2" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="6" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="10" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="14" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="18" mem-size="66" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="84" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="92" mem-size="1" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="93" mem-size="1" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="94" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="96" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="100" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="102" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="106" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="110" mem-size="8" synchro="MASTER"/>
- </Block>
- <Block name="MyRWBlock" mode="READ-WRITE" size="212" address="2" mem-size="472">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="4" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="4" mem-size="4" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="8" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="16" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="24" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="40" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="56" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="72" mem-size="264" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="336" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="368" mem-size="4" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="372" mem-size="4" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="376" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="384" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="400" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="408" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="424" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="440" mem-size="32" synchro="MASTER"/>
- </Block>
- <Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="3" mem-size="1180">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="10" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="20" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="40" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="60" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="100" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="140" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="180" mem-size="660" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="840" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="920" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="930" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="940" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="960" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="1000" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1020" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1060" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1100" mem-size="80" synchro="SLAVE"/>
- </Block>
+ <SILECS-Class name="AllTypes" version="0.1.0" address="1" usedMemory="DB1..DB3 / 3540 bytes">
+ <Acquisition-Block name="MyROBlock" size="53" address="1" mem-size="118">
+ <Acquisition-Register name="RO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="1">
+ <scalar format="int8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint8" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="1" mem-size="1">
+ <scalar format="uint8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int16" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="2" mem-size="2">
+ <scalar format="int16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint16" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="uint16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int32" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="6" mem-size="4">
+ <scalar format="int32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint32" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="10" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_float32" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="14" mem-size="4">
+ <scalar format="float32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_string" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="18" mem-size="66">
+ <string string-length="64" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_date" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="84" mem-size="8">
+ <scalar format="date"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_char" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="92" mem-size="1">
+ <scalar format="char"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_byte" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="93" mem-size="1">
+ <scalar format="byte"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_word" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="94" mem-size="2">
+ <scalar format="word"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dword" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="96" mem-size="4">
+ <scalar format="dword"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="100" mem-size="2">
+ <scalar format="int"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dint" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="102" mem-size="4">
+ <scalar format="dint"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_real" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="106" mem-size="4">
+ <scalar format="real"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dt" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="110" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
+ <Setting-Block name="MyRWBlock" size="212" address="2" mem-size="472">
+ <Volatile-Register name="RW_int8" generateFesaValueItem="true" size="1" address="0" mem-size="4">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint8" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="4" mem-size="4">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int16" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="8" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint16" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="16" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int32" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="24" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint32" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="40" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_float32" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="56" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_string" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="72" mem-size="264">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_date" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="336" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_char" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="368" mem-size="4">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_byte" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="372" mem-size="4">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_word" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="376" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dword" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="384" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="400" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dint" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="408" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_real" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="424" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dt" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="440" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Volatile-Register>
+ </Setting-Block>
+ <Command-Block name="MyWOBlock" size="530" address="3" mem-size="1180">
+ <Setting-Register name="WO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="10">
+ <array dim="10" format="int8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint8" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="10" mem-size="10">
+ <array dim="10" format="uint8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int16" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="20" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint16" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="40" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int32" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="60" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint32" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="100" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_float32" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="140" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_string" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="180" mem-size="660">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Setting-Register>
+ <Setting-Register name="WO_date" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="840" mem-size="80">
+ <array dim="10" format="date"/>
+ </Setting-Register>
+ <Setting-Register name="WO_char" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="920" mem-size="10">
+ <array dim="10" format="char"/>
+ </Setting-Register>
+ <Setting-Register name="WO_byte" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="930" mem-size="10">
+ <array dim="10" format="byte"/>
+ </Setting-Register>
+ <Setting-Register name="WO_word" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="940" mem-size="20">
+ <array dim="10" format="word"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dword" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="960" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="1000" mem-size="20">
+ <array dim="10" format="int"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dint" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1020" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Setting-Register>
+ <Setting-Register name="WO_real" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1060" mem-size="40">
+ <array dim="10" format="real"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dt" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1100" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Setting-Register>
+ </Command-Block>
<Instance label="testDevice1" address="0"/>
<Instance label="testDevice2" address="1"/>
</SILECS-Class>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Siemens_TiaBlock.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Siemens_TiaBlock.silecsparam
index 7f4c98485504479f0f0f3a85d51a19b9261ae7c0..cc3461d67109613d6fd6b18277394b378661a432 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Siemens_TiaBlock.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Siemens_TiaBlock.silecsparam
@@ -2,77 +2,187 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 16:02:43.799998"/>
- <Deployment checksum="3940683809"/>
+ <Generation date="2017-06-08 16:28:46.675405"/>
+ <Deployment checksum="308863231"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Siemens_TiaBlock" plc-brand="SIEMENS" plc-system="TIA-PORTAL" plc-model="SIMATIC_S7-300" protocol="BLOCK_MODE" address="0" domain="NotUsed" used-mem="TODO">
- <SILECS-Class name="SilecsHeader" version="1.0.0" address="0" used-mem="DB0..DB0 / 48 bytes">
- <Block name="hdrBlk" mode="READ-ONLY" size="14" address="0" mem-size="48">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="18" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="18" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="22" mem-size="18" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="40" mem-size="8" synchro="MASTER"/>
- </Block>
+ <SILECS-Class name="SilecsHeader" version="1.0.0" address="0" usedMemory="DB0..DB0 / 48 bytes">
+ <Acquisition-Block name="hdrBlk" size="14" address="0" mem-size="48">
+ <Acquisition-Register name="_version" size="1" address="0" mem-size="18">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_checksum" size="4" address="18" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_user" size="1" address="22" mem-size="18">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_date" size="8" address="40" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
- <SILECS-Class name="AllTypes" version="0.1.0" address="1" used-mem="DB1..DB3 / 3540 bytes">
- <Block name="MyROBlock" mode="READ-ONLY" size="53" address="1" mem-size="118">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="1" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="1" mem-size="1" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="2" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="6" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="10" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="14" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="18" mem-size="66" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="84" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="92" mem-size="1" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="93" mem-size="1" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="94" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="96" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="100" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="102" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="106" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="110" mem-size="8" synchro="MASTER"/>
- </Block>
- <Block name="MyRWBlock" mode="READ-WRITE" size="212" address="2" mem-size="472">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="4" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="4" mem-size="4" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="8" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="16" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="24" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="40" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="56" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="72" mem-size="264" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="336" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="368" mem-size="4" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="372" mem-size="4" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="376" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="384" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="400" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="408" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="424" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="440" mem-size="32" synchro="MASTER"/>
- </Block>
- <Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="3" mem-size="1180">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="10" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="20" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="40" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="60" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="100" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="140" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="180" mem-size="660" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="840" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="920" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="930" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="940" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="960" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="1000" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1020" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1060" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1100" mem-size="80" synchro="SLAVE"/>
- </Block>
+ <SILECS-Class name="AllTypes" version="0.1.0" address="1" usedMemory="DB1..DB3 / 3540 bytes">
+ <Acquisition-Block name="MyROBlock" size="53" address="1" mem-size="118">
+ <Acquisition-Register name="RO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="1">
+ <scalar format="int8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint8" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="1" mem-size="1">
+ <scalar format="uint8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int16" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="2" mem-size="2">
+ <scalar format="int16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint16" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="uint16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int32" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="6" mem-size="4">
+ <scalar format="int32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint32" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="10" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_float32" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="14" mem-size="4">
+ <scalar format="float32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_string" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="18" mem-size="66">
+ <string string-length="64" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_date" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="84" mem-size="8">
+ <scalar format="date"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_char" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="92" mem-size="1">
+ <scalar format="char"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_byte" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="93" mem-size="1">
+ <scalar format="byte"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_word" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="94" mem-size="2">
+ <scalar format="word"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dword" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="96" mem-size="4">
+ <scalar format="dword"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="100" mem-size="2">
+ <scalar format="int"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dint" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="102" mem-size="4">
+ <scalar format="dint"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_real" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="106" mem-size="4">
+ <scalar format="real"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dt" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="110" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
+ <Setting-Block name="MyRWBlock" size="212" address="2" mem-size="472">
+ <Volatile-Register name="RW_int8" generateFesaValueItem="true" size="1" address="0" mem-size="4">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint8" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="4" mem-size="4">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int16" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="8" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint16" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="16" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int32" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="24" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint32" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="40" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_float32" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="56" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_string" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="72" mem-size="264">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_date" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="336" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_char" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="368" mem-size="4">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_byte" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="372" mem-size="4">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_word" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="376" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dword" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="384" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="400" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dint" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="408" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_real" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="424" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dt" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="440" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Volatile-Register>
+ </Setting-Block>
+ <Command-Block name="MyWOBlock" size="530" address="3" mem-size="1180">
+ <Setting-Register name="WO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="10">
+ <array dim="10" format="int8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint8" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="10" mem-size="10">
+ <array dim="10" format="uint8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int16" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="20" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint16" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="40" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int32" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="60" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint32" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="100" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_float32" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="140" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_string" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="180" mem-size="660">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Setting-Register>
+ <Setting-Register name="WO_date" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="840" mem-size="80">
+ <array dim="10" format="date"/>
+ </Setting-Register>
+ <Setting-Register name="WO_char" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="920" mem-size="10">
+ <array dim="10" format="char"/>
+ </Setting-Register>
+ <Setting-Register name="WO_byte" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="930" mem-size="10">
+ <array dim="10" format="byte"/>
+ </Setting-Register>
+ <Setting-Register name="WO_word" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="940" mem-size="20">
+ <array dim="10" format="word"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dword" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="960" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="1000" mem-size="20">
+ <array dim="10" format="int"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dint" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1020" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Setting-Register>
+ <Setting-Register name="WO_real" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1060" mem-size="40">
+ <array dim="10" format="real"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dt" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1100" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Setting-Register>
+ </Command-Block>
<Instance label="testDevice1" address="0"/>
<Instance label="testDevice2" address="1"/>
</SILECS-Class>
diff --git a/silecs-codegen/src/xml/test/generated_correct/client/Siemens_TiaDevice.silecsparam b/silecs-codegen/src/xml/test/generated_correct/client/Siemens_TiaDevice.silecsparam
index 766dea9a9109655e0cab5141ecd0f7fb9f9a45a1..7488b8716434fac183a6d719522514d301141e27 100644
--- a/silecs-codegen/src/xml/test/generated_correct/client/Siemens_TiaDevice.silecsparam
+++ b/silecs-codegen/src/xml/test/generated_correct/client/Siemens_TiaDevice.silecsparam
@@ -2,77 +2,187 @@
<SILECS-Param silecs-version="DEV">
<Mapping-Info>
<Owner user-login="schwinn"/>
- <Generation date="2016-07-14 15:59:09.165849"/>
- <Deployment checksum="3940683809"/>
+ <Generation date="2017-06-08 16:28:46.637256"/>
+ <Deployment checksum="308863231"/>
</Mapping-Info>
<SILECS-Mapping plc-name="Siemens_TiaDevice" plc-brand="SIEMENS" plc-system="TIA-PORTAL" plc-model="SIMATIC_S7-300" protocol="DEVICE_MODE" address="0" domain="NotUsed" used-mem="TODO">
- <SILECS-Class name="SilecsHeader" version="1.0.0" address="0" used-mem="DB0..DB0 / 48 bytes">
- <Block name="hdrBlk" mode="READ-ONLY" size="14" address="0" mem-size="48">
- <Register name="_version" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="18" synchro="MASTER"/>
- <Register name="_checksum" format="uint32" array-dim1="1" array-dim2="1" size="4" address="18" mem-size="4" synchro="MASTER"/>
- <Register name="_user" format="string" string-len="16" array-dim1="1" array-dim2="1" size="1" address="22" mem-size="18" synchro="MASTER"/>
- <Register name="_date" format="dt" array-dim1="1" array-dim2="1" size="8" address="40" mem-size="8" synchro="MASTER"/>
- </Block>
+ <SILECS-Class name="SilecsHeader" version="1.0.0" address="0" usedMemory="DB0..DB0 / 48 bytes">
+ <Acquisition-Block name="hdrBlk" size="14" address="0" mem-size="48">
+ <Acquisition-Register name="_version" size="1" address="0" mem-size="18">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_checksum" size="4" address="18" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_user" size="1" address="22" mem-size="18">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_date" size="8" address="40" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
<Instance label="SilecsHeader" address="0"/>
</SILECS-Class>
- <SILECS-Class name="AllTypes" version="0.1.0" address="1" used-mem="DB1..DB2 / 3540 bytes">
- <Block name="MyROBlock" mode="READ-ONLY" size="53" address="0" mem-size="118">
- <Register name="RO_int8" format="int8" array-dim1="1" array-dim2="1" size="1" address="0" mem-size="1" synchro="MASTER"/>
- <Register name="RO_uint8" format="uint8" array-dim1="1" array-dim2="1" size="1" address="1" mem-size="1" synchro="MASTER"/>
- <Register name="RO_int16" format="int16" array-dim1="1" array-dim2="1" size="2" address="2" mem-size="2" synchro="MASTER"/>
- <Register name="RO_uint16" format="uint16" array-dim1="1" array-dim2="1" size="2" address="4" mem-size="2" synchro="MASTER"/>
- <Register name="RO_int32" format="int32" array-dim1="1" array-dim2="1" size="4" address="6" mem-size="4" synchro="MASTER"/>
- <Register name="RO_uint32" format="uint32" array-dim1="1" array-dim2="1" size="4" address="10" mem-size="4" synchro="MASTER"/>
- <Register name="RO_float32" format="float32" array-dim1="1" array-dim2="1" size="4" address="14" mem-size="4" synchro="MASTER"/>
- <Register name="RO_string" format="string" string-len="64" array-dim1="1" array-dim2="1" size="1" address="18" mem-size="66" synchro="MASTER"/>
- <Register name="RO_date" format="date" array-dim1="1" array-dim2="1" size="8" address="84" mem-size="8" synchro="MASTER"/>
- <Register name="RO_char" format="char" array-dim1="1" array-dim2="1" size="1" address="92" mem-size="1" synchro="MASTER"/>
- <Register name="RO_byte" format="byte" array-dim1="1" array-dim2="1" size="1" address="93" mem-size="1" synchro="MASTER"/>
- <Register name="RO_word" format="word" array-dim1="1" array-dim2="1" size="2" address="94" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dword" format="dword" array-dim1="1" array-dim2="1" size="4" address="96" mem-size="4" synchro="MASTER"/>
- <Register name="RO_int" format="int" array-dim1="1" array-dim2="1" size="2" address="100" mem-size="2" synchro="MASTER"/>
- <Register name="RO_dint" format="dint" array-dim1="1" array-dim2="1" size="4" address="102" mem-size="4" synchro="MASTER"/>
- <Register name="RO_real" format="real" array-dim1="1" array-dim2="1" size="4" address="106" mem-size="4" synchro="MASTER"/>
- <Register name="RO_dt" format="dt" array-dim1="1" array-dim2="1" size="8" address="110" mem-size="8" synchro="MASTER"/>
- </Block>
- <Block name="MyRWBlock" mode="READ-WRITE" size="212" address="118" mem-size="472">
- <Register name="RW_int8" format="int8" array-dim1="2" array-dim2="2" size="1" address="0" mem-size="4" synchro="MASTER"/>
- <Register name="RW_uint8" format="uint8" array-dim1="2" array-dim2="2" size="1" address="4" mem-size="4" synchro="MASTER"/>
- <Register name="RW_int16" format="int16" array-dim1="2" array-dim2="2" size="2" address="8" mem-size="8" synchro="MASTER"/>
- <Register name="RW_uint16" format="uint16" array-dim1="2" array-dim2="2" size="2" address="16" mem-size="8" synchro="MASTER"/>
- <Register name="RW_int32" format="int32" array-dim1="2" array-dim2="2" size="4" address="24" mem-size="16" synchro="MASTER"/>
- <Register name="RW_uint32" format="uint32" array-dim1="2" array-dim2="2" size="4" address="40" mem-size="16" synchro="MASTER"/>
- <Register name="RW_float32" format="float32" array-dim1="2" array-dim2="2" size="4" address="56" mem-size="16" synchro="MASTER"/>
- <Register name="RW_string" format="string" string-len="64" array-dim1="2" array-dim2="2" size="1" address="72" mem-size="264" synchro="MASTER"/>
- <Register name="RW_date" format="date" array-dim1="2" array-dim2="2" size="8" address="336" mem-size="32" synchro="MASTER"/>
- <Register name="RW_char" format="char" array-dim1="2" array-dim2="2" size="1" address="368" mem-size="4" synchro="MASTER"/>
- <Register name="RW_byte" format="byte" array-dim1="2" array-dim2="2" size="1" address="372" mem-size="4" synchro="MASTER"/>
- <Register name="RW_word" format="word" array-dim1="2" array-dim2="2" size="2" address="376" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dword" format="dword" array-dim1="2" array-dim2="2" size="4" address="384" mem-size="16" synchro="MASTER"/>
- <Register name="RW_int" format="int" array-dim1="2" array-dim2="2" size="2" address="400" mem-size="8" synchro="MASTER"/>
- <Register name="RW_dint" format="dint" array-dim1="2" array-dim2="2" size="4" address="408" mem-size="16" synchro="MASTER"/>
- <Register name="RW_real" format="real" array-dim1="2" array-dim2="2" size="4" address="424" mem-size="16" synchro="MASTER"/>
- <Register name="RW_dt" format="dt" array-dim1="2" array-dim2="2" size="8" address="440" mem-size="32" synchro="MASTER"/>
- </Block>
- <Block name="MyWOBlock" mode="WRITE-ONLY" size="530" address="590" mem-size="1180">
- <Register name="WO_int8" format="int8" array-dim1="10" array-dim2="1" size="1" address="0" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_uint8" format="uint8" array-dim1="10" array-dim2="1" size="1" address="10" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_int16" format="int16" array-dim1="10" array-dim2="1" size="2" address="20" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_uint16" format="uint16" array-dim1="10" array-dim2="1" size="2" address="40" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_int32" format="int32" array-dim1="10" array-dim2="1" size="4" address="60" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_uint32" format="uint32" array-dim1="10" array-dim2="1" size="4" address="100" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_float32" format="float32" array-dim1="10" array-dim2="1" size="4" address="140" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_string" format="string" string-len="64" array-dim1="10" array-dim2="1" size="1" address="180" mem-size="660" synchro="SLAVE"/>
- <Register name="WO_date" format="date" array-dim1="10" array-dim2="1" size="8" address="840" mem-size="80" synchro="SLAVE"/>
- <Register name="WO_char" format="char" array-dim1="10" array-dim2="1" size="1" address="920" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_byte" format="byte" array-dim1="10" array-dim2="1" size="1" address="930" mem-size="10" synchro="SLAVE"/>
- <Register name="WO_word" format="word" array-dim1="10" array-dim2="1" size="2" address="940" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dword" format="dword" array-dim1="10" array-dim2="1" size="4" address="960" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_int" format="int" array-dim1="10" array-dim2="1" size="2" address="1000" mem-size="20" synchro="SLAVE"/>
- <Register name="WO_dint" format="dint" array-dim1="10" array-dim2="1" size="4" address="1020" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_real" format="real" array-dim1="10" array-dim2="1" size="4" address="1060" mem-size="40" synchro="SLAVE"/>
- <Register name="WO_dt" format="dt" array-dim1="10" array-dim2="1" size="8" address="1100" mem-size="80" synchro="SLAVE"/>
- </Block>
+ <SILECS-Class name="AllTypes" version="0.1.0" address="1" usedMemory="DB1..DB2 / 3540 bytes">
+ <Acquisition-Block name="MyROBlock" size="53" address="0" mem-size="118">
+ <Acquisition-Register name="RO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="1">
+ <scalar format="int8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint8" generateFesaValueItem="true" fesaFieldName="RO_uint8_fesa" size="1" address="1" mem-size="1">
+ <scalar format="uint8"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int16" generateFesaValueItem="true" fesaFieldName="RO_int16_fesa" size="2" address="2" mem-size="2">
+ <scalar format="int16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint16" generateFesaValueItem="true" fesaFieldName="RO_uint16_fesa" size="2" address="4" mem-size="2">
+ <scalar format="uint16"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int32" generateFesaValueItem="true" fesaFieldName="RO_int32_fesa" size="4" address="6" mem-size="4">
+ <scalar format="int32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_uint32" generateFesaValueItem="true" fesaFieldName="RO_uint32_fesa" size="4" address="10" mem-size="4">
+ <scalar format="uint32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_float32" generateFesaValueItem="true" fesaFieldName="RO_float32_fesa" size="4" address="14" mem-size="4">
+ <scalar format="float32"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_string" generateFesaValueItem="true" fesaFieldName="RO_string_fesa" size="1" address="18" mem-size="66">
+ <string string-length="64" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_date" generateFesaValueItem="true" fesaFieldName="RO_date_fesa" size="8" address="84" mem-size="8">
+ <scalar format="date"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_char" generateFesaValueItem="true" fesaFieldName="RO_char_fesa" size="1" address="92" mem-size="1">
+ <scalar format="char"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_byte" generateFesaValueItem="true" fesaFieldName="RO_byte_fesa" size="1" address="93" mem-size="1">
+ <scalar format="byte"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_word" generateFesaValueItem="true" fesaFieldName="RO_word_fesa" size="2" address="94" mem-size="2">
+ <scalar format="word"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dword" generateFesaValueItem="true" fesaFieldName="RO_dword_fesa" size="4" address="96" mem-size="4">
+ <scalar format="dword"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_int" generateFesaValueItem="true" fesaFieldName="RO_int_fesa" size="2" address="100" mem-size="2">
+ <scalar format="int"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dint" generateFesaValueItem="true" fesaFieldName="RO_dint_fesa" size="4" address="102" mem-size="4">
+ <scalar format="dint"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_real" generateFesaValueItem="true" fesaFieldName="RO_real_fesa" size="4" address="106" mem-size="4">
+ <scalar format="real"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="RO_dt" generateFesaValueItem="true" fesaFieldName="RO_dt_fesa" size="8" address="110" mem-size="8">
+ <scalar format="dt"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
+ <Setting-Block name="MyRWBlock" size="212" address="118" mem-size="472">
+ <Volatile-Register name="RW_int8" generateFesaValueItem="true" size="1" address="0" mem-size="4">
+ <array2D dim1="2" dim2="2" format="int8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint8" generateFesaValueItem="true" fesaFieldName="RW_uint8_fesa" size="1" address="4" mem-size="4">
+ <array2D dim1="2" dim2="2" format="uint8"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int16" generateFesaValueItem="true" fesaFieldName="RW_int16_fesa" size="2" address="8" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint16" generateFesaValueItem="true" fesaFieldName="RW_uint16_fesa" size="2" address="16" mem-size="8">
+ <array2D dim1="2" dim2="2" format="uint16"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int32" generateFesaValueItem="true" fesaFieldName="RW_int32_fesa" size="4" address="24" mem-size="16">
+ <array2D dim1="2" dim2="2" format="int32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_uint32" generateFesaValueItem="true" fesaFieldName="RW_uint32_fesa" size="4" address="40" mem-size="16">
+ <array2D dim1="2" dim2="2" format="uint32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_float32" generateFesaValueItem="true" fesaFieldName="RW_float32_fesa" size="4" address="56" mem-size="16">
+ <array2D dim1="2" dim2="2" format="float32"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_string" generateFesaValueItem="true" fesaFieldName="RW_string_fesa" size="1" address="72" mem-size="264">
+ <stringArray2D dim1="2" dim2="2" string-length="64" format="string"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_date" generateFesaValueItem="true" fesaFieldName="RW_date_fesa" size="8" address="336" mem-size="32">
+ <array2D dim1="2" dim2="2" format="date"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_char" generateFesaValueItem="true" fesaFieldName="RW_char_fesa" size="1" address="368" mem-size="4">
+ <array2D dim1="2" dim2="2" format="char"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_byte" generateFesaValueItem="true" fesaFieldName="RW_byte_fesa" size="1" address="372" mem-size="4">
+ <array2D dim1="2" dim2="2" format="byte"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_word" generateFesaValueItem="true" fesaFieldName="RW_word_fesa" size="2" address="376" mem-size="8">
+ <array2D dim1="2" dim2="2" format="word"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dword" generateFesaValueItem="true" fesaFieldName="RW_dword_fesa" size="4" address="384" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dword"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_int" generateFesaValueItem="true" fesaFieldName="RW_int_fesa" size="2" address="400" mem-size="8">
+ <array2D dim1="2" dim2="2" format="int"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dint" generateFesaValueItem="true" fesaFieldName="RW_dint_fesa" size="4" address="408" mem-size="16">
+ <array2D dim1="2" dim2="2" format="dint"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_real" generateFesaValueItem="true" fesaFieldName="RW_real_fesa" size="4" address="424" mem-size="16">
+ <array2D dim1="2" dim2="2" format="real"/>
+ </Volatile-Register>
+ <Volatile-Register name="RW_dt" generateFesaValueItem="true" fesaFieldName="RW_dt_fesa" size="8" address="440" mem-size="32">
+ <array2D dim1="2" dim2="2" format="dt"/>
+ </Volatile-Register>
+ </Setting-Block>
+ <Command-Block name="MyWOBlock" size="530" address="590" mem-size="1180">
+ <Setting-Register name="WO_int8" generateFesaValueItem="true" size="1" address="0" mem-size="10">
+ <array dim="10" format="int8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint8" generateFesaValueItem="true" fesaFieldName="WO_uint8_fesa" size="1" address="10" mem-size="10">
+ <array dim="10" format="uint8"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int16" generateFesaValueItem="true" fesaFieldName="WO_int16_fesa" size="2" address="20" mem-size="20">
+ <array dim="10" format="int16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint16" generateFesaValueItem="true" fesaFieldName="WO_uint16_fesa" size="2" address="40" mem-size="20">
+ <array dim="10" format="uint16"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int32" generateFesaValueItem="true" fesaFieldName="WO_int32_fesa" size="4" address="60" mem-size="40">
+ <array dim="10" format="int32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_uint32" generateFesaValueItem="true" fesaFieldName="WO_uint32_fesa" size="4" address="100" mem-size="40">
+ <array dim="10" format="uint32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_float32" generateFesaValueItem="true" fesaFieldName="WO_float32_fesa" size="4" address="140" mem-size="40">
+ <array dim="10" format="float32"/>
+ </Setting-Register>
+ <Setting-Register name="WO_string" generateFesaValueItem="true" fesaFieldName="WO_string_fesa" size="1" address="180" mem-size="660">
+ <stringArray dim="10" string-length="64" format="string"/>
+ </Setting-Register>
+ <Setting-Register name="WO_date" generateFesaValueItem="true" fesaFieldName="WO_date_fesa" size="8" address="840" mem-size="80">
+ <array dim="10" format="date"/>
+ </Setting-Register>
+ <Setting-Register name="WO_char" generateFesaValueItem="true" fesaFieldName="WO_char_fesa" size="1" address="920" mem-size="10">
+ <array dim="10" format="char"/>
+ </Setting-Register>
+ <Setting-Register name="WO_byte" generateFesaValueItem="true" fesaFieldName="WO_byte_fesa" size="1" address="930" mem-size="10">
+ <array dim="10" format="byte"/>
+ </Setting-Register>
+ <Setting-Register name="WO_word" generateFesaValueItem="true" fesaFieldName="WO_word_fesa" size="2" address="940" mem-size="20">
+ <array dim="10" format="word"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dword" generateFesaValueItem="true" fesaFieldName="WO_dword_fesa" size="4" address="960" mem-size="40">
+ <array dim="10" format="dword"/>
+ </Setting-Register>
+ <Setting-Register name="WO_int" generateFesaValueItem="true" fesaFieldName="WO_int_fesa" size="2" address="1000" mem-size="20">
+ <array dim="10" format="int"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dint" generateFesaValueItem="true" fesaFieldName="WO_dint_fesa" size="4" address="1020" mem-size="40">
+ <array dim="10" format="dint"/>
+ </Setting-Register>
+ <Setting-Register name="WO_real" generateFesaValueItem="true" fesaFieldName="WO_real_fesa" size="4" address="1060" mem-size="40">
+ <array dim="10" format="real"/>
+ </Setting-Register>
+ <Setting-Register name="WO_dt" generateFesaValueItem="true" fesaFieldName="WO_dt_fesa" size="8" address="1100" mem-size="80">
+ <array dim="10" format="dt"/>
+ </Setting-Register>
+ </Command-Block>
<Instance label="testDevice1" address="1"/>
<Instance label="testDevice2" address="2"/>
</SILECS-Class>
diff --git a/silecs-codegen/src/xml/test/generated_correct/controller/Beckhoff_BC9020.exp b/silecs-codegen/src/xml/test/generated_correct/controller/Beckhoff_BC9020.exp
index db9ec3db27e3da588dda7281f46815659add0885..68210c9c6172ef0e3928f3b621189cfde9ddef5e 100644
--- a/silecs-codegen/src/xml/test/generated_correct/controller/Beckhoff_BC9020.exp
+++ b/silecs-codegen/src/xml/test/generated_correct/controller/Beckhoff_BC9020.exp
@@ -11,13 +11,13 @@ VAR_GLOBAL
_version_a781_SilecsHeader AT %MW0: STRING(16):= DEV;
(*SilecsHeader/SilecsHeader/hdrBlk *)
- _checksum_a781_SilecsHeader AT %MW9: DWORD:= 2843029646;
+ _checksum_a781_SilecsHeader AT %MW9: DWORD:= 1037751963;
(*SilecsHeader/SilecsHeader/hdrBlk *)
_user_a781_SilecsHeader AT %MW11: STRING(16):= 'schwinn';
(*SilecsHeader/SilecsHeader/hdrBlk *)
- _date_a781_SilecsHeader AT %MW20: DT:= DT#2016-7-14-16:7:52;
+ _date_a781_SilecsHeader AT %MW20: DT:= DT#2017-6-8-16:38:3;
(*AllTypes/testDevice1/MyROBlock *)
RO_int8_a583_testDevice1 AT %MW24: SINT;
diff --git a/silecs-codegen/src/xml/test/generated_correct/controller/Beckhoff_CX9020.exp b/silecs-codegen/src/xml/test/generated_correct/controller/Beckhoff_CX9020.exp
index c05bd13cac550027757c98b4f380c2e74742e07c..d6fca4ca68637ac60952990e7de60bbdeb1bfe47 100644
--- a/silecs-codegen/src/xml/test/generated_correct/controller/Beckhoff_CX9020.exp
+++ b/silecs-codegen/src/xml/test/generated_correct/controller/Beckhoff_CX9020.exp
@@ -11,13 +11,13 @@ VAR_GLOBAL
_version_a781_SilecsHeader AT %MW0: STRING(16):= DEV;
(*SilecsHeader/SilecsHeader/hdrBlk *)
- _checksum_a781_SilecsHeader AT %MW20: DWORD:= 427563505;
+ _checksum_a781_SilecsHeader AT %MW20: DWORD:= 2754857673;
(*SilecsHeader/SilecsHeader/hdrBlk *)
_user_a781_SilecsHeader AT %MW24: STRING(16):= 'schwinn';
(*SilecsHeader/SilecsHeader/hdrBlk *)
- _date_a781_SilecsHeader AT %MW44: DT:= DT#2016-7-14-16:8:13;
+ _date_a781_SilecsHeader AT %MW44: DT:= DT#2017-6-8-16:38:3;
(*AllTypes/testDevice1/MyROBlock *)
RO_int8_a583_testDevice1 AT %MW52: SINT;
diff --git a/silecs-codegen/src/xml/test/generated_correct/controller/Rabbit_BlockMode.h b/silecs-codegen/src/xml/test/generated_correct/controller/Rabbit_BlockMode.h
index 51ea9947fa4c6188656a5d80ce18f068f59b5f79..a5857abf63b31fa1699601a15005f03e69f4beeb 100644
--- a/silecs-codegen/src/xml/test/generated_correct/controller/Rabbit_BlockMode.h
+++ b/silecs-codegen/src/xml/test/generated_correct/controller/Rabbit_BlockMode.h
@@ -183,13 +183,13 @@ int SILECS_init()
strcpy((unsigned char *)silecsData.data.SilecsHeader_hdrBlk.device[0]._version, "SILECS_DEV");
/* Silecs checksum initialization */
- silecsData.data.SilecsHeader_hdrBlk.device[0]._checksum = 3940683809;
+ silecsData.data.SilecsHeader_hdrBlk.device[0]._checksum = 308863231;
/* Silecs user initialization */
strcpy((unsigned char *)silecsData.data.SilecsHeader_hdrBlk.device[0]._user, "schwinn");
/* Silecs date initialization */
- SILECS_set_dt(3,48,8,16,14,7,2016,&silecsData.data.SilecsHeader_hdrBlk.device[0]._date);
+ SILECS_set_dt(3,3,38,16,8,6,2017,&silecsData.data.SilecsHeader_hdrBlk.device[0]._date);
}
/*
diff --git a/silecs-codegen/src/xml/test/generated_correct/controller/Rabbit_DeviceMode.h b/silecs-codegen/src/xml/test/generated_correct/controller/Rabbit_DeviceMode.h
index d382f9dedbd147e7ceb37aaee84bafcdd6d2a32d..95491d747e28f33f3618ed1e6afda28e4a3fe2f8 100644
--- a/silecs-codegen/src/xml/test/generated_correct/controller/Rabbit_DeviceMode.h
+++ b/silecs-codegen/src/xml/test/generated_correct/controller/Rabbit_DeviceMode.h
@@ -176,13 +176,13 @@ int SILECS_init()
strcpy((unsigned char *)silecsData.data.SilecsHeader_device[0].hdrBlk._version, "SILECS_DEV");
/* Silecs checksum initialization */
- silecsData.data.SilecsHeader_device[0].hdrBlk._checksum = 3940683809;
+ silecsData.data.SilecsHeader_device[0].hdrBlk._checksum = 308863231;
/* Silecs user initialization */
strcpy((unsigned char *)silecsData.data.SilecsHeader_device[0].hdrBlk._user, "schwinn");
/* Silecs date initialization */
- SILECS_set_dt(3,0,9,16,14,7,2016,&silecsData.data.SilecsHeader_device[0].hdrBlk._date);
+ SILECS_set_dt(3,3,38,16,8,6,2017,&silecsData.data.SilecsHeader_device[0].hdrBlk._date);
}
/*
diff --git a/silecs-codegen/src/xml/test/generated_correct/controller/Schneider_M340.xsy b/silecs-codegen/src/xml/test/generated_correct/controller/Schneider_M340.xsy
index 580607556a28904252eb1297249febefba9f35b4..354b71b039da276fb50252fe7a4abfdbdeb1c86f 100644
--- a/silecs-codegen/src/xml/test/generated_correct/controller/Schneider_M340.xsy
+++ b/silecs-codegen/src/xml/test/generated_correct/controller/Schneider_M340.xsy
@@ -5,7 +5,7 @@
<comment>SilecsHeader/SilecsHeader/hdrBlk</comment>
</variables>
<variables name="_checksum_a781_SilecsHeader" typeName="DWORD" topologicalAddress="%MW8">
- <variableInit value="3940683809"/>
+ <variableInit value="308863231"/>
<comment>SilecsHeader/SilecsHeader/hdrBlk</comment>
</variables>
<variables name="_user_a781_SilecsHeader" typeName="STRING[16]" topologicalAddress="%MW10">
@@ -13,7 +13,7 @@
<comment>SilecsHeader/SilecsHeader/hdrBlk</comment>
</variables>
<variables name="_date_a781_SilecsHeader" typeName="DT" topologicalAddress="%MW18">
- <variableInit value="DT#2016-7-14-16:8:24"/>
+ <variableInit value="DT#2017-6-8-16:38:3"/>
<comment>SilecsHeader/SilecsHeader/hdrBlk</comment>
</variables>
<variables name="RO_int8_a583_testDevice1" typeName="WORD" topologicalAddress="%MW22">
diff --git a/silecs-codegen/src/xml/test/generated_correct/controller/Schneider_PremiumQuantum.xsy b/silecs-codegen/src/xml/test/generated_correct/controller/Schneider_PremiumQuantum.xsy
index 90041edc6d060edc6fb80aa7dcae9cc36fe24ce4..724ac1040422d4352f637eb1721396fd64f9953d 100644
--- a/silecs-codegen/src/xml/test/generated_correct/controller/Schneider_PremiumQuantum.xsy
+++ b/silecs-codegen/src/xml/test/generated_correct/controller/Schneider_PremiumQuantum.xsy
@@ -5,7 +5,7 @@
<comment>SilecsHeader/SilecsHeader/hdrBlk</comment>
</variables>
<variables name="_checksum_a781_SilecsHeader" typeName="DWORD" topologicalAddress="%MW8">
- <variableInit value="3940683809"/>
+ <variableInit value="308863231"/>
<comment>SilecsHeader/SilecsHeader/hdrBlk</comment>
</variables>
<variables name="_user_a781_SilecsHeader" typeName="STRING[16]" topologicalAddress="%MW10">
@@ -13,7 +13,7 @@
<comment>SilecsHeader/SilecsHeader/hdrBlk</comment>
</variables>
<variables name="_date_a781_SilecsHeader" typeName="DT" topologicalAddress="%MW18">
- <variableInit value="DT#2016-7-14-16:8:40"/>
+ <variableInit value="DT#2017-6-8-16:38:3"/>
<comment>SilecsHeader/SilecsHeader/hdrBlk</comment>
</variables>
<variables name="RO_int8_a583_testDevice1" typeName="WORD" topologicalAddress="%MW22">
diff --git a/silecs-codegen/src/xml/test/generated_correct/controller/Siemens_Step7Block.scl b/silecs-codegen/src/xml/test/generated_correct/controller/Siemens_Step7Block.scl
index c5cd604ba78e2a8c7f6a3015495d13ab24ffce06..cdf21c5539ee5544c6f7d45f6889a9204def106f 100644
--- a/silecs-codegen/src/xml/test/generated_correct/controller/Siemens_Step7Block.scl
+++ b/silecs-codegen/src/xml/test/generated_correct/controller/Siemens_Step7Block.scl
@@ -8,9 +8,9 @@ FAMILY: SILECS
NAME: UDTB
STRUCT
_version: STRING[16] := 'SILECS_DEV';
- _checksum: DWORD := DW#16#eae21021;
+ _checksum: DWORD := DW#16#1268e0ff;
_user: STRING[16] := 'schwinn';
- _date: DT := DT#2016-7-14-16:7:40;
+ _date: DT := DT#2017-6-8-16:38:3;
END_STRUCT;
END_TYPE
diff --git a/silecs-codegen/src/xml/test/generated_correct/controller/Siemens_Step7Device.scl b/silecs-codegen/src/xml/test/generated_correct/controller/Siemens_Step7Device.scl
index 32b0476df75d8226bf16e2e4e9abc078fe75d716..142d3f927c49e11f6b209ddf811f22de340af82b 100644
--- a/silecs-codegen/src/xml/test/generated_correct/controller/Siemens_Step7Device.scl
+++ b/silecs-codegen/src/xml/test/generated_correct/controller/Siemens_Step7Device.scl
@@ -8,9 +8,9 @@ FAMILY: SILECS
NAME: UDTB
STRUCT
_version: STRING[16] := 'SILECS_DEV';
- _checksum: DWORD := DW#16#eae21021;
+ _checksum: DWORD := DW#16#1268e0ff;
_user: STRING[16] := 'schwinn';
- _date: DT := DT#2016-7-14-16:7:24;
+ _date: DT := DT#2017-6-8-16:38:3;
END_STRUCT;
END_TYPE
diff --git a/silecs-codegen/src/xml/test/generated_correct/controller/Siemens_TiaBlock.scl b/silecs-codegen/src/xml/test/generated_correct/controller/Siemens_TiaBlock.scl
index a12f7bd70ce4d6e013e361af12f490d175aade87..f91e96353f6332370d78024ced64683280ae584c 100644
--- a/silecs-codegen/src/xml/test/generated_correct/controller/Siemens_TiaBlock.scl
+++ b/silecs-codegen/src/xml/test/generated_correct/controller/Siemens_TiaBlock.scl
@@ -8,9 +8,9 @@ FAMILY: SILECS
NAME: UDTB
STRUCT
_version: STRING[16] := 'SILECS_DEV';
- _checksum: DWORD := DW#16#eae21021;
+ _checksum: DWORD := DW#16#1268e0ff;
_user: STRING[16] := 'schwinn';
- _date: DT := DT#2016-7-14-16:7:12;
+ _date: DT := DT#2017-6-8-16:38:3;
END_STRUCT;
END_TYPE
diff --git a/silecs-codegen/src/xml/test/generated_correct/controller/Siemens_TiaDevice.scl b/silecs-codegen/src/xml/test/generated_correct/controller/Siemens_TiaDevice.scl
index 3f0ee9dc2884c6ddd4bb049ee7011a08f7a09c75..b83ccff3aab84110589b86ee4f2f7354a3d02623 100644
--- a/silecs-codegen/src/xml/test/generated_correct/controller/Siemens_TiaDevice.scl
+++ b/silecs-codegen/src/xml/test/generated_correct/controller/Siemens_TiaDevice.scl
@@ -8,9 +8,9 @@ FAMILY: SILECS
NAME: UDTB
STRUCT
_version: STRING[16] := 'SILECS_DEV';
- _checksum: DWORD := DW#16#eae21021;
+ _checksum: DWORD := DW#16#1268e0ff;
_user: STRING[16] := 'schwinn';
- _date: DT := DT#2016-7-14-16:6:23;
+ _date: DT := DT#2017-6-8-16:38:3;
END_STRUCT;
END_TYPE
diff --git a/silecs-codegen/src/xml/xmltemplate.py b/silecs-codegen/src/xml/xmltemplate.py
index 19bdc3fc4404084281753a785d3fa9047d369c2d..b09e09f18a9ed06c70bd884c2cf363a244604c44 100644
--- a/silecs-codegen/src/xml/xmltemplate.py
+++ b/silecs-codegen/src/xml/xmltemplate.py
@@ -27,12 +27,20 @@ silecsHeader = """<?xml version="1.0" encoding="UTF-8"?>
<Editor user-login="%s"/>
</Information>
<SILECS-Class domain="TEST" name="SilecsHeader" version="1.0.0">
- <Block mode="READ-ONLY" name="hdrBlk">
- <Register array-dim1="1" array-dim2="1" format="string" name="_version" string-len="16" synchro="MASTER"/>
- <Register array-dim1="1" array-dim2="1" format="uint32" name="_checksum" synchro="MASTER"/>
- <Register array-dim1="1" array-dim2="1" format="string" name="_user" string-len="16" synchro="MASTER"/>
- <Register array-dim1="1" array-dim2="1" format="dt" name="_date" synchro="MASTER"/>
- </Block>
+ <Acquisition-Block name="hdrBlk">
+ <Acquisition-Register name="_version">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_checksum">
+ <scalar format="uint32" />
+ </Acquisition-Register>
+ <Acquisition-Register name="_user">
+ <string string-length="16" format="string"/>
+ </Acquisition-Register>
+ <Acquisition-Register name="_date">
+ <scalar format="dt" />
+ </Acquisition-Register>
+ </Acquisition-Block>
</SILECS-Class>
</SILECS-Design>
"""
@@ -53,9 +61,11 @@ designTemplate = """<?xml version="1.0" encoding="UTF-8"?>
<Editor user-login="%s"/>
</Information>
<SILECS-Class name="%s" version="0.1.0" domain="OPERATIONAL" >
- <Block name="MyBlock" mode="READ-ONLY" generateFesaProperty="true">
- <Register name="myRegister" format="int32" synchro="MASTER" generateFesaValueItem="true" />
- </Block>
+ <Acquisition-Block name="MyBlock" generateFesaProperty="true">
+ <Acquisition-Register name="myRegister" generateFesaValueItem="true">
+ <scalar format="int32"/>
+ </Acquisition-Register>
+ </Acquisition-Block>
</SILECS-Class>
</SILECS-Design>
"""
diff --git a/silecs-communication-cpp/.cproject b/silecs-communication-cpp/.cproject
index b71572d468506db98ca65fa2f567d08fccbdd09b..28a705b83f00b801bbebcbc0ceca65870a7a0b9b 100644
--- a/silecs-communication-cpp/.cproject
+++ b/silecs-communication-cpp/.cproject
@@ -5,7 +5,7 @@
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="cdt.managedbuild.config.gnu.exe.debug.512849333" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
- <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
@@ -21,17 +21,17 @@
<builder buildPath="${workspace_loc:/silecs-communication-cpp}" id="cdt.managedbuild.target.gnu.builder.exe.debug.1509177360" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="cdt.managedbuild.target.gnu.builder.exe.debug"/>
<tool id="cdt.managedbuild.tool.gnu.archiver.base.1070762906" name="GCC Archiver" superClass="cdt.managedbuild.tool.gnu.archiver.base"/>
<tool id="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug.290909559" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug">
- <option id="gnu.cpp.compiler.exe.debug.option.optimization.level.1848198526" name="Optimization Level" superClass="gnu.cpp.compiler.exe.debug.option.optimization.level" value="gnu.cpp.compiler.optimization.level.none" valueType="enumerated"/>
- <option id="gnu.cpp.compiler.exe.debug.option.debugging.level.240667535" name="Debug Level" superClass="gnu.cpp.compiler.exe.debug.option.debugging.level" value="gnu.cpp.compiler.debugging.level.max" valueType="enumerated"/>
- <option id="gnu.cpp.compiler.option.include.paths.773424835" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
+ <option id="gnu.cpp.compiler.exe.debug.option.optimization.level.1848198526" name="Optimization Level" superClass="gnu.cpp.compiler.exe.debug.option.optimization.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.optimization.level.none" valueType="enumerated"/>
+ <option id="gnu.cpp.compiler.exe.debug.option.debugging.level.240667535" name="Debug Level" superClass="gnu.cpp.compiler.exe.debug.option.debugging.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.debugging.level.max" valueType="enumerated"/>
+ <option id="gnu.cpp.compiler.option.include.paths.773424835" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
<listOptionValue builtIn="false" value="/acc/sys/L866/usr/include/libxml2"/>
<listOptionValue builtIn="false" value="/acc/sys/L866/usr/local/natinst/ninetv/include"/>
</option>
<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.1806199416" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
</tool>
<tool id="cdt.managedbuild.tool.gnu.c.compiler.exe.debug.926882765" name="GCC C Compiler" superClass="cdt.managedbuild.tool.gnu.c.compiler.exe.debug">
- <option defaultValue="gnu.c.optimization.level.none" id="gnu.c.compiler.exe.debug.option.optimization.level.116711054" name="Optimization Level" superClass="gnu.c.compiler.exe.debug.option.optimization.level" valueType="enumerated"/>
- <option id="gnu.c.compiler.exe.debug.option.debugging.level.1551801327" name="Debug Level" superClass="gnu.c.compiler.exe.debug.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
+ <option defaultValue="gnu.c.optimization.level.none" id="gnu.c.compiler.exe.debug.option.optimization.level.116711054" name="Optimization Level" superClass="gnu.c.compiler.exe.debug.option.optimization.level" useByScannerDiscovery="false" valueType="enumerated"/>
+ <option id="gnu.c.compiler.exe.debug.option.debugging.level.1551801327" name="Debug Level" superClass="gnu.c.compiler.exe.debug.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.2005171832" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
</tool>
<tool id="cdt.managedbuild.tool.gnu.c.linker.exe.debug.1604657084" name="GCC C Linker" superClass="cdt.managedbuild.tool.gnu.c.linker.exe.debug"/>
@@ -58,7 +58,7 @@
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="cdt.managedbuild.config.gnu.exe.release.10628772" moduleId="org.eclipse.cdt.core.settings" name="Release">
<externalSettings/>
<extensions>
- <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
@@ -136,23 +136,15 @@
<buildTargets>
<target name="clean" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
- <buildArguments/>
<buildTarget>clean</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand>
<runAllBuilders>true</runAllBuilders>
</target>
<target name="x86_64" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
- <buildCommand>make</buildCommand>
- <buildTarget>CPU=x86_64 -j4</buildTarget>
- <stopOnError>true</stopOnError>
- <useDefaultCommand>true</useDefaultCommand>
- <runAllBuilders>true</runAllBuilders>
- </target>
- <target name="release" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
- <buildTarget>release RELEASE_GROUP=bel RELEASE_LOCATION=~ SVN_REPOSITORY=https://www-acc.gsi.de/svn/silecs/silecs-communication-cpp</buildTarget>
+ <buildTarget>CPU=x86_64 -j4</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand>
<runAllBuilders>true</runAllBuilders>
diff --git a/silecs-communication-cpp/.settings/language.settings.xml b/silecs-communication-cpp/.settings/language.settings.xml
index 3c4fe0fc48b61ea9de4753e075d75d6c336e0510..852a7f6184a015c89a00194f8b27e4b37935c1ad 100644
--- a/silecs-communication-cpp/.settings/language.settings.xml
+++ b/silecs-communication-cpp/.settings/language.settings.xml
@@ -5,7 +5,7 @@
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
- <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-226963044723472530" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-226059455508497530" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
@@ -16,7 +16,7 @@
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
- <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-226963044723472530" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-226059455508497530" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
diff --git a/silecs-communication-cpp/jenkins.sh b/silecs-communication-cpp/jenkins.sh
deleted file mode 100755
index 2b5218be175ab60d0135dee574c8e4281b82503d..0000000000000000000000000000000000000000
--- a/silecs-communication-cpp/jenkins.sh
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/bin/sh
-#test2
-export COMMON_MAKE_PATH="$WORKSPACE/../../generics/generic-makefiles"
-export SNAP7_BASE="$WORKSPACE/../snap7/snap7-full"
-export BOOST_HOME="$WORKSPACE/../../generics/boost_1.54.0/boost/1.54.0"
-make all CPU=x86_64 -j4
diff --git a/silecs-communication-cpp/releaseSilecs.sh b/silecs-communication-cpp/releaseSilecs.sh
index 76a5cff66bdc5b1a03d8ff3fc646c6cd61a89bfd..9b1b69e08e8e176494fb3c56a9e7b531b007f684 100755
--- a/silecs-communication-cpp/releaseSilecs.sh
+++ b/silecs-communication-cpp/releaseSilecs.sh
@@ -3,17 +3,17 @@
# $ source releaseSilecs.sh
#
# release a new version v1.0.0
-# $ release 1.0.0 /common/usr/cscofe/silecs /home/bel/schwinn/lnx/git/silecs
+# $ release 1.0.0 /common/usr/cscofe/silecs /home/bel/schwinn/lnx/git
#
# patch 2 packages of an existing version 1.2.3
-# $ patch silecs-codegen 1.2.4 1.2.3 /common/usr/cscofe/silecs /home/bel/schwinn/lnx/git/silecs
-# $ patch silecs-model 1.2.4 1.2.3 /common/usr/cscofe/silecs /home/bel/schwinn/lnx/git/silecs
+# $ patch silecs-codegen 1.2.4 1.2.3 /common/usr/cscofe/silecs /home/bel/schwinn/lnx/git
+# $ patch silecs-model 1.2.4 1.2.3 /common/usr/cscofe/silecs /home/bel/schwinn/lnx/git
#
# release a new version of the silecs-eclipse plugin
-# $ plugin_release /common/usr/cscofe/silecs /home/bel/schwinn/lnx/git/silecs-plugin
+# $ plugin_release /common/usr/cscofe/silecs /home/bel/schwinn/lnx/git-silecs-plugin
-# List of silecs packages which is released or patched
-PACKAGES="silecs-codegen silecs-model silecs-communication-cpp silecs-diagnostic-cpp snap7"
+# List of silecs packages which can be released or patched
+PACKAGES="silecs-codegen silecs-model silecs-communication-cpp silecs-diagnostic-cpp silecs-cli-client snap7"
# Check that folder exists, print proper error if not
checkFolderExists()
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/communication/SNAP7Connection.cpp b/silecs-communication-cpp/src/silecs-communication/interface/communication/SNAP7Connection.cpp
index ea562aacb40311a201aa25a30f4013635cea89d0..6f91e021fd6c84ed8c4dfd7b45e2475c4fc59eb9 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/communication/SNAP7Connection.cpp
+++ b/silecs-communication-cpp/src/silecs-communication/interface/communication/SNAP7Connection.cpp
@@ -160,6 +160,17 @@ namespace Silecs
return 0;
}
+ bool SNAP7Connection::isRunning(PLC* thePLC)
+ {
+ UnitStatusType statusStruct;
+ this->readUnitStatus(thePLC, statusStruct);
+ switch (statusStruct.status)
+ {
+ case S7CpuStatusRun : return true;
+ case S7CpuStatusStop: return false;
+ default : throw SilecsException(__FILE__, __LINE__, UNKNOWN_ERROR,std::string("PLC Status is: UNKNOWN"));
+ }
+ }
//-------------------------------------------------------------------------------------------------------------------
int SNAP7Connection::readData(PLC* thePLC, unsigned long DBn, unsigned long offset, unsigned long size, unsigned char* pBuffer)
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/communication/SNAP7Connection.h b/silecs-communication-cpp/src/silecs-communication/interface/communication/SNAP7Connection.h
index 740dc9bd4cde83420920c53c20383dd6d5093dff..1a86cc943d4a36b6bc29807a24309c38cc409d78 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/communication/SNAP7Connection.h
+++ b/silecs-communication-cpp/src/silecs-communication/interface/communication/SNAP7Connection.h
@@ -40,6 +40,8 @@ namespace Silecs
int readCPUInfo(PLC* thePLC, CPUInfoType& dataStruct);
int readCPInfo(PLC* thePLC, CPInfoType& dataStruct);
+ bool isRunning(PLC* thePLC);
+
int readData(PLC* thePLC, unsigned long DBn, unsigned long offset, unsigned long size, unsigned char* pBuffer);
int writeData(PLC* thePLC, unsigned long DBn, unsigned long offset, unsigned long size, unsigned char* pBuffer);
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/communication/SilecsConnection.cpp b/silecs-communication-cpp/src/silecs-communication/interface/communication/SilecsConnection.cpp
index d89db59b1108b9658020d1699905dbca78af283a..1cf18425468f6c6b07af9e89784d0896bff537dd 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/communication/SilecsConnection.cpp
+++ b/silecs-communication-cpp/src/silecs-communication/interface/communication/SilecsConnection.cpp
@@ -263,7 +263,12 @@ namespace Silecs
return -1;
}
- //PERFORM COLD RESTART
+ bool Connection::isRunning(PLC* thePLC)
+ {
+ throw SilecsException(__FILE__, __LINE__, DIAG_PLC_REPORT_NOT_SUPPORTED, thePLC->getName());
+ return -1;
+ }
+
int Connection::coldRestart(PLC* thePLC)
{
throw SilecsException(__FILE__, __LINE__, DIAG_PLC_REPORT_NOT_SUPPORTED, thePLC->getName());
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/communication/SilecsConnection.h b/silecs-communication-cpp/src/silecs-communication/interface/communication/SilecsConnection.h
index ed9d0177af471602dd917d46873d8f04142ea5ba..0cc27ee12f37d9da1e33e31172d4ef4f14200e7c 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/communication/SilecsConnection.h
+++ b/silecs-communication-cpp/src/silecs-communication/interface/communication/SilecsConnection.h
@@ -89,6 +89,10 @@ namespace Silecs
virtual int readUnitStatus(PLC* thePLC, UnitStatusType& dataStruct);
virtual int readCPUInfo(PLC* thePLC, CPUInfoType& dataStruct);
virtual int readCPInfo(PLC* thePLC, CPInfoType& dataStruct);
+
+ // true if the "recvUnitStatus" is RUN, false otherwise. Throws exception on failure
+ virtual bool isRunning(PLC* thePLC);
+
//SET PLC COLD RESTART
virtual int coldRestart(PLC* thePLC);
virtual int plcStop(PLC* thePLC);
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/core/SilecsService.cpp b/silecs-communication-cpp/src/silecs-communication/interface/core/SilecsService.cpp
index 82774b4a5284715c86661b52bc2ca8adb3a29f53..d765f08aef9e66393aa1038eff4e9e9419e7c504 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/core/SilecsService.cpp
+++ b/silecs-communication-cpp/src/silecs-communication/interface/core/SilecsService.cpp
@@ -207,15 +207,6 @@ namespace Silecs
return semverPatch_;
}
- SynchroType Service::whichSynchroType(std::string type)
- {
- StringUtilities::toLower(type);
- if (type == "master") return Master;
- else if (type == "slave") return Slave;
- else if (type == "none") return No;
- else throw SilecsException(__FILE__, __LINE__, DATA_UNKNOWN_SYNCHRO_TYPE, type);
- }
-
bool Service::withInputAccess(AccessType& accessType)
{ return (accessType != Output);
}
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/core/SilecsService.h b/silecs-communication-cpp/src/silecs-communication/interface/core/SilecsService.h
index d6ade6bb5b1f5217a2880314d89839cbd6aedf14..ea98f9b741b6e7e302430c51a3f5721cf0db00e5 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/core/SilecsService.h
+++ b/silecs-communication-cpp/src/silecs-communication/interface/core/SilecsService.h
@@ -25,11 +25,6 @@
namespace Silecs
{
- // Register and Block synchronization type
- typedef enum
- { Master, Slave, No
- } SynchroType;
-
/// @cond
// Register and Block access types
typedef enum
@@ -160,7 +155,6 @@ namespace Silecs
void printArgs();
static const std::string getParamsFilesPath();
- static SynchroType whichSynchroType(std::string type);
static bool withInputAccess(AccessType& accessType);
static bool withOutputAccess(AccessType& accessType);
static bool fileExists(std::string filename);
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/equipment/CNVBlock.cpp b/silecs-communication-cpp/src/silecs-communication/interface/equipment/CNVBlock.cpp
index 53080f534936322b6f7180d564455ad8b5f36b46..6818c53a12f52429c21af2af96fe00ba00a2101a 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/equipment/CNVBlock.cpp
+++ b/silecs-communication-cpp/src/silecs-communication/interface/equipment/CNVBlock.cpp
@@ -65,7 +65,7 @@ namespace Silecs
CNVInputBlock::CNVInputBlock(PLC* thePLC, ElementXML blockNode, AccessType accessType) :
CNVBlock(thePLC, blockNode, accessType)
{
- if (DEBUG & Log::topics_) LOG(ALLOC) << "Block (create): " << name_ << ", CNV: " << getPLC()->getName() << ", access: Input" << ", hasMaster: " << (hasMasterRegister() ? "yes" : "no") << ", hasSlave: " << (hasSlaveRegister() ? "yes" : "no") << ", address: " << address_ << ", mem-size: " << memSize_ ;//<< ", buffer-size: " << bufferSize_;
+ if (DEBUG & Log::topics_) LOG(ALLOC) << "Block (create): " << name_ << ", CNV: " << getPLC()->getName() << ", access: Input" << ", address: " << address_ << ", mem-size: " << memSize_ ;//<< ", buffer-size: " << bufferSize_;
handle_ = NULL;
subscriptionFlag_ = false;
@@ -269,7 +269,7 @@ namespace Silecs
CNVOutputBlock::CNVOutputBlock(PLC* thePLC, ElementXML blockNode, AccessType accessType) :
CNVBlock(thePLC, blockNode, accessType)
{
- if (DEBUG & Log::topics_) LOG(ALLOC) << "Block (create): " << name_ << ", CNV: " << getPLC()->getName() << ", access: Output" << ", hasMaster: " << (hasMasterRegister() ? "yes" : "no") << ", hasSlave: " << (hasSlaveRegister() ? "yes" : "no") << ", address: " << address_ << ", mem-size: " << memSize_;// << ", buffer-size: " << bufferSize_;
+ if (DEBUG & Log::topics_) LOG(ALLOC) << "Block (create): " << name_ << ", CNV: " << getPLC()->getName() << ", access: Output" << ", address: " << address_ << ", mem-size: " << memSize_;// << ", buffer-size: " << bufferSize_;
/* ALLOCATE THE BUFFER */
deviceVectorType deviceCol = thePLC->getDeviceMap();
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/equipment/PLCBlock.cpp b/silecs-communication-cpp/src/silecs-communication/interface/equipment/PLCBlock.cpp
index 69a3b8af823d889596a310f9808da4519f67693e..b144357b739eb4149002513dc0d550fc6289c67a 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/equipment/PLCBlock.cpp
+++ b/silecs-communication-cpp/src/silecs-communication/interface/equipment/PLCBlock.cpp
@@ -52,7 +52,7 @@ namespace Silecs
InputBlock::InputBlock(PLC* thePLC,ElementXML blockNode, AccessType accessType) :
PLCBlock(thePLC, blockNode, accessType)
{
- if (DEBUG & Log::topics_) LOG(ALLOC) << "Block (create): " << name_ << ", plc: " << getPLC()->getName() << ", access: Input" << ", hasMaster: " << (hasMasterRegister() ? "yes" : "no") << ", hasSlave: " << (hasSlaveRegister() ? "yes" : "no") << ", address: " << address_ << ", mem-size: " << memSize_ << ", buffer-size: " << bufferSize_;
+ if (DEBUG & Log::topics_) LOG(ALLOC) << "Block (create): " << name_ << ", plc: " << getPLC()->getName() << ", access: Input" << ", address: " << address_ << ", mem-size: " << memSize_ << ", buffer-size: " << bufferSize_;
// Creates receive task which relies on the block exchange
if (getPLC()->getProtocolID() == BlockMode)
@@ -73,7 +73,7 @@ namespace Silecs
OutputBlock::OutputBlock(PLC* thePLC,ElementXML blockNode, AccessType accessType) :
PLCBlock(thePLC, blockNode, accessType)
{
- if (DEBUG & Log::topics_) LOG(ALLOC) << "Block (create): " << name_ << ", plc: " << getPLC()->getName() << ", access: Output" << ", hasMaster: " << (hasMasterRegister() ? "yes" : "no") << ", hasSlave: " << (hasSlaveRegister() ? "yes" : "no") << ", address: " << address_ << ", mem-size: " << memSize_ << ", buffer-size: " << bufferSize_;
+ if (DEBUG & Log::topics_) LOG(ALLOC) << "Block (create): " << name_ << ", plc: " << getPLC()->getName() << ", access: Output" << ", address: " << address_ << ", mem-size: " << memSize_ << ", buffer-size: " << bufferSize_;
// Creates send task which relies on the block exchange
if (getPLC()->getProtocolID() == BlockMode)
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsBlock.cpp b/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsBlock.cpp
index bb4ee710446c48b2db3dd6c1c178dcefc5f6d3dc..44667bf9a60a60f7036444541f46dd5fc7918614 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsBlock.cpp
+++ b/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsBlock.cpp
@@ -29,7 +29,7 @@ namespace Silecs
{
Block::Block(PLC* thePLC, ElementXML blockNode, AccessType accessType) :
- thePLC_ (thePLC), hasMaster_(false), hasSlave_(false)
+ thePLC_ (thePLC)
{
std::string designName = blockNode.getAttribute("name");
@@ -44,21 +44,6 @@ namespace Silecs
* and the accessType is given by the caller.
*/
accessType_ = accessType;
-
- // Adjust the synchro-type of the block relying on its own registers
- // . hasMaster if the block contains 1 MASTER register at least
- // . hasSlave if the block contains 1 SLAVE register at least
- // can be a mix or none if only Volatile registers
- std::vector< boost::shared_ptr<ElementXML> > registerNodes = blockNode.childList_;
- std::vector< boost::shared_ptr<ElementXML> >::const_iterator registerIter;
- for(registerIter = registerNodes.begin(); registerIter != registerNodes.end(); registerIter++)
- {
- std::string synchro = (*registerIter)->getAttribute("synchro");
- if (!hasMaster_ && Service::whichSynchroType(synchro) == Master)
- hasMaster_ = true;
- if (!hasSlave_ && Service::whichSynchroType(synchro) == Slave)
- hasSlave_ = true;
- }
}
Block::~Block()
@@ -72,10 +57,9 @@ namespace Silecs
AccessType Block::whichAccessType(std::string type)
{
- StringUtilities::toLower(type);
- if (type == "write-only") return Output;
- else if (type == "read-only") return Input;
- else if (type == "read-write") return InOut;
+ if (type == "Acquisition-Block") return Input;
+ else if (type == "Command-Block") return Output;
+ else if (type == "Setting-Block") return InOut;
else throw SilecsException(__FILE__, __LINE__, DATA_UNKNOWN_ACCESS_TYPE, type);
}
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsBlock.h b/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsBlock.h
index 01dbdace83662e1df0d54febf71c68eb814d09ce..a0cdfb623c6af425383a359d7187acbc271f01ca 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsBlock.h
+++ b/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsBlock.h
@@ -49,8 +49,8 @@ namespace Silecs
static AccessType whichAccessType(std::string type);
static std::string whichAccessType(AccessType type);
- inline bool hasInputAccess() { return (accessType_ != Output); }
- inline bool hasOutputAccess() { return (accessType_ != Input); }
+ inline bool isReadable() { return (accessType_ != Output); }
+ inline bool isWritable() { return (accessType_ != Input); }
inline PLC* getPLC() { return thePLC_; }
inline std::string& getName() { return name_; }
@@ -59,8 +59,6 @@ namespace Silecs
inline unsigned long& getMemSize() { return memSize_; }
inline Task<WrapperAction>* getTask() { return pTask_; }
inline void* getBuffer() { return pBuffer_; }
- inline bool hasMasterRegister() { return hasMaster_; }
- inline bool hasSlaveRegister() { return hasSlave_; }
/// @cond
void setCustomAttributes(const unsigned long customAddress, const unsigned long customOffset, const unsigned long customSize);
@@ -109,12 +107,6 @@ namespace Silecs
// Send/Receive data buffer
void *pBuffer_;
-
- /// True if the block contains 1 MASTER and/or 1 Slave register at least
- /// MASTER en SLAVE registers can be mixed in the same block.
- /// Only Volatile (NONE) ==> both are false
- bool hasMaster_;
- bool hasSlave_;
};
} // namespace
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsDevice.cpp b/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsDevice.cpp
index 9994de5c33ffc7519d2bf7384986e15f78cb5a5e..088852570e742e23e3a3140ebdede214b8e093dd 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsDevice.cpp
+++ b/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsDevice.cpp
@@ -46,7 +46,7 @@ namespace Silecs
{
std::string blockName = blockIter->getAttribute("name");
LOG(ALLOC) << "Adding Block to Device: " << blockName;
- AccessType accessType = Block::whichAccessType(blockIter->getAttribute("mode"));
+ AccessType accessType = Block::whichAccessType(blockIter->name_);
std::vector< boost::shared_ptr<ElementXML> > registerNodes = blockIter->childList_;
instantiateRegisters(blockName, accessType, registerNodes);
}
@@ -213,65 +213,36 @@ namespace Silecs
void Device::importRegisters(Block* pBlock, void* pBuffer, timeval ts, Context* pContext)
{
std::vector<Register*>& registerCol = getRegisterCollection(pBlock->getName());
+ std::vector<Register*>::iterator pReg;
+ for (pReg=registerCol.begin(); pReg<registerCol.end(); pReg++)
+ {
+ // do not update volatile registers for sync (client has to force a transaction himself if required).
+ if( !(*pReg)->isVolatile() || !pContext->isForSynchronization() )
+ {
+ if((*pReg)->getFormat() == String)
+ (*pReg)->importString(pBuffer, ts);
+ else
+ (*pReg)->importValue(pBuffer, ts);
+ }
+ }
- if (pContext->isForSynchronization())
- { // Transaction has been done within the context of retentive registers synchronization,
- // do not update volatile registers (client has to force a transaction himself if required).
- for (unsigned int i=0; i<registerCol.size(); i++)
- {
- Register* pReg = registerCol[i];
- if (pReg->isRetentive())
- {
- if(pReg->getFormat() == String)
- pReg->importString(pBuffer, ts);
- else // all registers but those having string format
- pReg->importValue(pBuffer, ts);
- }
- }
- }
- else
- { // It's a normal transaction from the client process,
- // all registers of the block have to be updated.
- for (unsigned int i=0; i<registerCol.size(); i++)
- {
- if(registerCol[i]->getFormat() == String)
- registerCol[i]->importString(pBuffer, ts);
- else // all registers but those having string format
- registerCol[i]->importValue(pBuffer, ts);
- }
- }
}
void Device::exportRegisters(Block* pBlock, void* pBuffer, Context* pContext)
{
- std::vector<Register*>& registerCol = getRegisterCollection(pBlock->getName());
-
- if (pContext->isForSynchronization())
- { // Transaction has been done within the context of retentive registers synchronization,
- // do not update volatile register (client has to force a transaction himself if required).
- for (unsigned int i=0; i<registerCol.size(); i++)
- {
- Register* pReg = registerCol[i];
- if (pReg->isRetentive())
- {
- if(pReg->getFormat() == String)
- pReg->exportString(pBuffer);
- else // all registers but those having string format
- pReg->exportValue(pBuffer);
- }
- }
- }
- else
- { // It's a normal transaction from the client process,
- // all registers of the block have to be updated.
- for (unsigned int i=0; i<registerCol.size(); i++)
- {
- if(registerCol[i]->getFormat() == String)
- registerCol[i]->exportString(pBuffer);
- else
- registerCol[i]->exportValue(pBuffer);
- }
- }
+ std::vector<Register*>& registerCol = getRegisterCollection(pBlock->getName());
+ std::vector<Register*>::iterator pReg;
+ for (pReg=registerCol.begin(); pReg<registerCol.end(); pReg++)
+ {
+ // do not update volatile registers for sync (client has to force a transaction himself if required).
+ if( !(*pReg)->isVolatile() || !pContext->isForSynchronization() )
+ {
+ if((*pReg)->getFormat() == String)
+ (*pReg)->exportString(pBuffer);
+ else
+ (*pReg)->exportValue(pBuffer);
+ }
+ }
}
void Device::copyInToOut(const std::string blockName)
@@ -279,7 +250,7 @@ namespace Silecs
std::vector<Register*>& registerCol = getRegisterCollection(blockName);
for (unsigned int i=0; i<registerCol.size(); i++)
{ Register* pReg = registerCol[i];
- if (pReg->hasInputAccess() && pReg->hasOutputAccess())
+ if (pReg->isReadable() && pReg->isWritable())
pReg->copyValue();
}
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsPLC.cpp b/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsPLC.cpp
index 48580fbdbf80e96cdcd8f2ea822ea3d425f2d76c..b73be2e3072a84b8d822974cd459802946a99e5b 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsPLC.cpp
+++ b/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsPLC.cpp
@@ -233,7 +233,7 @@ namespace Silecs
blockVectorType::iterator blockIter;
for (blockIter = blockCol_.begin();blockIter!= blockCol_.end(); blockIter ++)
{
- if ((*blockIter)->hasInputAccess())
+ if ((*blockIter)->isReadable())
{
deviceVectorType::iterator pDeviceIter;
for(pDeviceIter = deviceCol_.begin(); pDeviceIter != deviceCol_.end(); ++pDeviceIter)
@@ -259,6 +259,11 @@ namespace Silecs
return getConnection()->readUnitStatus(this, dataStruct);
}
+ bool PLC::isRunning()
+ {
+ return getConnection()->isRunning(this);
+ }
+
int PLC::recvCPUInfo(CPUInfoType& dataStruct)
{
@@ -332,20 +337,19 @@ namespace Silecs
XMLParser xmlParser(parameterFile_,true);
// Extract general information ===========================================
- ElementXML rootNode = xmlParser.getFirstElementFromXPath("/SILECS-Param");
+ ElementXML rootNode = xmlParser.getSingleElementFromXPath("/SILECS-Param");
localRelease_ = rootNode.getAttribute("silecs-version");
-
- ElementXML ownerNode = xmlParser.getFirstElementFromXPath("/SILECS-Param/Mapping-Info/Owner");
+ ElementXML ownerNode = xmlParser.getSingleElementFromXPath("/SILECS-Param/Mapping-Info/Owner");
localOwner_ = ownerNode.getAttribute("user-login");
- ElementXML generationNode = xmlParser.getFirstElementFromXPath("/SILECS-Param/Mapping-Info/Generation");
+ ElementXML generationNode = xmlParser.getSingleElementFromXPath("/SILECS-Param/Mapping-Info/Generation");
localDate_ = generationNode.getAttribute("date");
- ElementXML deploymentNode = xmlParser.getFirstElementFromXPath("/SILECS-Param/Mapping-Info/Deployment");
+ ElementXML deploymentNode = xmlParser.getSingleElementFromXPath("/SILECS-Param/Mapping-Info/Deployment");
StringUtilities::fromString(localChecksum_,deploymentNode.getAttribute("checksum") );
// Extract PLC general configuration ======================================
- ElementXML mappingNode = xmlParser.getFirstElementFromXPath("/SILECS-Param/SILECS-Mapping");
+ ElementXML mappingNode = xmlParser.getSingleElementFromXPath("/SILECS-Param/SILECS-Mapping");
//name_ = pEl->getStringAttribute("name"); already done before
domain_ = mappingNode.getAttribute("domain");
brand_ = mappingNode.getAttribute("plc-brand");
@@ -373,8 +377,7 @@ namespace Silecs
for(classIter = classNodes.begin(); classIter != classNodes.end(); classIter++)
{
std::string className = (*classIter)->getAttribute("name");
-
- boost::ptr_vector<ElementXML> blockNodes = xmlParser.getElementsFromXPath_throwIfEmpty("/SILECS-Param/SILECS-Mapping/SILECS-Class[@name='"+ className + "']/Block");
+ boost::ptr_vector<ElementXML> blockNodes = xmlParser.getElementsFromXPath_throwIfEmpty("/SILECS-Param/SILECS-Mapping/SILECS-Class[@name='"+ className + "']/*[ name()='Acquisition-Block' or name()='Setting-Block' or name()='Command-Block']");
boost::ptr_vector<ElementXML>::const_iterator blockIter;
boost::ptr_vector<ElementXML> instanceNodes = xmlParser.getElementsFromXPath_throwIfEmpty("/SILECS-Param/SILECS-Mapping/SILECS-Class[@name='"+ className + "']/Instance");
@@ -392,8 +395,8 @@ namespace Silecs
for(blockIter = blockNodes.begin(); blockIter != blockNodes.end(); blockIter++)
{
std::string blockName = (*blockIter).getAttribute("name");
- AccessType accessType = Block::whichAccessType((*blockIter).getAttribute("mode"));
- LOG((DIAG)) << "The block '" << blockName << " will be created with access-type: '" << accessType << "'.";
+ AccessType accessType = Block::whichAccessType((*blockIter).name_);
+ LOG((DIAG)) << "The block '" << blockName << " of type '"<< (*blockIter).name_ << "' will be created.";
Block* pBlock = 0;
// Instantiate Input blocks ------------------------------------------------------
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsPLC.h b/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsPLC.h
index 43f513e06a638b703046a8b4baad57620aa8e6b5..b3327be3673cc99ab5d04b653d780e9c2f688264 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsPLC.h
+++ b/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsPLC.h
@@ -270,7 +270,9 @@ namespace Silecs
int recvCPUInfo(CPUInfoType& dataStruct);
int recvCPInfo(CPInfoType& dataStruct);
- //Cold RESTART
+ // true if the "recvUnitStatus" is RUN, false otherwise. Throws exception on failure
+ bool isRunning();
+
int sendColdRestart();
int sendPlcStop();
/*!
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsRegister.cpp b/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsRegister.cpp
index 901fb367450958b58b6e146ca5b3fd2771f6ff93..5b4bf9076d39cf0ed442df6290dc3cba7e484fbb 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsRegister.cpp
+++ b/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsRegister.cpp
@@ -29,30 +29,41 @@
namespace Silecs
{
- Register::Register(Device* theDevice,const boost::shared_ptr<ElementXML>& registerNode) : theDevice_ (theDevice)
- {
+ Register::Register(Device* theDevice,const boost::shared_ptr<ElementXML>& registerNode) : theDevice_ (theDevice)
+ {
name_ = registerNode->getAttribute("name");
- format_ = whichFormatType(registerNode->getAttribute("format"));
- StringUtilities::fromString(dimension1_,registerNode->getAttribute("array-dim1") );
- StringUtilities::fromString(dimension2_,registerNode->getAttribute("array-dim2") );
- StringUtilities::fromString(size_,registerNode->getAttribute("size") );
- StringUtilities::fromString(memSize_,registerNode->getAttribute("mem-size") );
- StringUtilities::fromString(address_,registerNode->getAttribute("address") );
- synchro_ = Service::whichSynchroType(registerNode->getAttribute("synchro"));
- isInitialized_ = false; //register not initialized yet (used for output registers)
-
- // if format is string, retrieve also string-len attribute
- if (format_ == String)
- {
- StringUtilities::fromString(length_,registerNode->getAttribute("string-len") );
- if (DEBUG & Log::topics_) LOG(ALLOC) << "Register (create): " << name_ << ", format: " << getFormatAsString() << ", string-len: " << length_ << ", dim: " << dimension1_ << ", dim2: " << dimension2_ << ", synchro: " << getSynchroTypeAsString() << ", offset: " << address_;
- }
- else
- {
- length_ = 1;
- if (DEBUG & Log::topics_) LOG(ALLOC) << "Register (create): " << name_ << ", format: " << getFormatAsString() << ", dim: " << dimension1_ << ", dim2: " << dimension2_ << ", synchro: " << getSynchroTypeAsString() << ", offset: " << address_;
- }
- }
+ length_ = 1;
+ dimension1_ = 1;
+ dimension2_ = 1;
+ std::vector< boost::shared_ptr<ElementXML> > childNodes = registerNode->childList_;
+ std::vector< boost::shared_ptr<ElementXML> >::const_iterator childIter;
+ for(childIter = childNodes.begin(); childIter != childNodes.end(); childIter++)
+ {
+ // We have to loop, since there is as well the description-element
+ format_ = whichFormatType((*childIter)->getAttribute("format"));
+ if( (*childIter)->hasAttribute("dim") )
+ StringUtilities::fromString(dimension1_,(*childIter)->getAttribute("dim") );// dim is used for 1d-arrays
+ if( (*childIter)->hasAttribute("dim1") )
+ StringUtilities::fromString(dimension1_,(*childIter)->getAttribute("dim1") );
+ if( (*childIter)->hasAttribute("dim2") )
+ StringUtilities::fromString(dimension2_,(*childIter)->getAttribute("dim2") );
+ if( (*childIter)->hasAttribute("string-length") )
+ StringUtilities::fromString(length_,(*childIter)->getAttribute("string-length") );
+ }
+ StringUtilities::fromString(size_,registerNode->getAttribute("size") );
+ StringUtilities::fromString(memSize_,registerNode->getAttribute("mem-size") );
+ StringUtilities::fromString(address_,registerNode->getAttribute("address") );
+ isInitialized_ = false; //register not initialized yet (used for output registers)
+
+ if (length_ > 1)
+ {
+ LOG(DEBUG) << "Register (create): " << name_ << ", format: " << getFormatAsString() << ", string-length: " << length_ << ", dim: " << dimension1_ << ", dim2: " << dimension2_ << ", offset: " << address_;
+ }
+ else
+ {
+ LOG(DEBUG) << "Register (create): " << name_ << ", format: " << getFormatAsString() << ", dim: " << dimension1_ << ", dim2: " << dimension2_ << ", offset: " << address_;
+ }
+ }
Register::~Register()
{
@@ -99,7 +110,7 @@ namespace Silecs
template <typename T>
inline T Register::getVal(FormatType F)
{
- if (!hasInputAccess())
+ if (!isReadable())
throw SilecsException(__FILE__, __LINE__, DATA_READ_ACCESS_TYPE_MISMATCH, getName());
if ((format_ != F) || !isScalar())
throw SilecsException(__FILE__, __LINE__, PARAM_FORMAT_TYPE_MISMATCH, getName());
@@ -109,7 +120,7 @@ namespace Silecs
template <typename T>
inline void Register::getValArray(FormatType F, T* pValue, uint32_t dim)
{
- if (!hasInputAccess())
+ if (!isReadable())
throw SilecsException(__FILE__, __LINE__, DATA_READ_ACCESS_TYPE_MISMATCH, getName());
if ((format_ != F) || !isSingleArray())
throw SilecsException(__FILE__, __LINE__, PARAM_FORMAT_TYPE_MISMATCH, getName());
@@ -121,7 +132,7 @@ namespace Silecs
template <typename T>
inline void Register::getValArray2D(FormatType F, T* pValue, uint32_t dim1, uint32_t dim2)
{
- if(!hasInputAccess())
+ if(!isReadable())
throw SilecsException(__FILE__, __LINE__, DATA_READ_ACCESS_TYPE_MISMATCH, getName());
if((format_ != F) || !isDoubleArray())
throw SilecsException(__FILE__, __LINE__, PARAM_FORMAT_TYPE_MISMATCH, getName());
@@ -133,7 +144,7 @@ namespace Silecs
template <typename Tsrc, typename Tdst>
inline void Register::convGetValArray(FormatType F, Tdst* pValue, uint32_t dim)
{
- if (!hasInputAccess())
+ if (!isReadable())
throw SilecsException(__FILE__, __LINE__, DATA_READ_ACCESS_TYPE_MISMATCH, getName());
if ((format_ != F) || !isSingleArray())
throw SilecsException(__FILE__, __LINE__, PARAM_FORMAT_TYPE_MISMATCH, getName());
@@ -147,7 +158,7 @@ namespace Silecs
template <typename Tsrc, typename Tdst>
inline void Register::convGetValArray2D(FormatType F, Tdst* pValue, uint32_t dim1, uint32_t dim2)
{
- if (!hasInputAccess())
+ if (!isReadable())
throw SilecsException(__FILE__, __LINE__, DATA_READ_ACCESS_TYPE_MISMATCH, getName());
if((format_ != F) || !isDoubleArray())
throw SilecsException(__FILE__, __LINE__, PARAM_FORMAT_TYPE_MISMATCH, getName());
@@ -161,7 +172,7 @@ namespace Silecs
template <typename T>
inline T* Register::getRefArray(FormatType F, uint32_t& dim)
{
- if (!hasInputAccess())
+ if (!isReadable())
throw SilecsException(__FILE__, __LINE__, DATA_READ_ACCESS_TYPE_MISMATCH, getName());
if ((format_ != F) || !isSingleArray())
throw SilecsException(__FILE__, __LINE__, PARAM_FORMAT_TYPE_MISMATCH, getName());
@@ -172,7 +183,7 @@ namespace Silecs
template <typename T>
inline T* Register::getRefArray2D(FormatType F, uint32_t& dim1, uint32_t& dim2)
{
- if (!hasInputAccess())
+ if (!isReadable())
throw SilecsException(__FILE__, __LINE__, DATA_READ_ACCESS_TYPE_MISMATCH, getName());
if((format_ != F) || !isDoubleArray())
throw SilecsException(__FILE__, __LINE__, PARAM_FORMAT_TYPE_MISMATCH, getName());
@@ -185,7 +196,7 @@ namespace Silecs
// No template for string format
std::string Register::getValString()
{
- if (!hasInputAccess())
+ if (!isReadable())
throw SilecsException(__FILE__, __LINE__, DATA_READ_ACCESS_TYPE_MISMATCH, getName());
if ((format_ != String) || (dimension1_ != 1)|| (dimension2_ != 1))
throw SilecsException(__FILE__, __LINE__, PARAM_FORMAT_TYPE_MISMATCH, getName());
@@ -195,7 +206,7 @@ namespace Silecs
void Register::getValStringArray(std::string* pVal, uint32_t dim)
{
- if (!hasInputAccess())
+ if (!isReadable())
throw SilecsException(__FILE__, __LINE__, DATA_READ_ACCESS_TYPE_MISMATCH, getName());
if (format_ != String)
throw SilecsException(__FILE__, __LINE__, PARAM_FORMAT_TYPE_MISMATCH, getName());
@@ -209,7 +220,7 @@ namespace Silecs
void Register::getValStringArray2D(std::string* pVal, uint32_t dim1, uint32_t dim2)
{
- if (!hasInputAccess())
+ if (!isReadable())
throw SilecsException(__FILE__, __LINE__, DATA_READ_ACCESS_TYPE_MISMATCH, getName());
if (format_ != String)
throw SilecsException(__FILE__, __LINE__, PARAM_FORMAT_TYPE_MISMATCH, getName());
@@ -225,7 +236,7 @@ namespace Silecs
const std::string** Register::getRefStringArray(uint32_t& dim)
{
- if (!hasInputAccess())
+ if (!isReadable())
throw SilecsException(__FILE__, __LINE__, DATA_READ_ACCESS_TYPE_MISMATCH, getName());
if (dimension1_ <= 1)
throw SilecsException(__FILE__, __LINE__, PARAM_ARRAY_DIMENSION_MISMATCH, getName());
@@ -235,7 +246,7 @@ namespace Silecs
const std::string** Register::getRefStringArray2D(uint32_t& dim1, uint32_t& dim2)
{
- if (!hasInputAccess())
+ if (!isReadable())
throw SilecsException(__FILE__, __LINE__, DATA_READ_ACCESS_TYPE_MISMATCH, getName());
if (dimension2_ <= 1)
throw SilecsException(__FILE__, __LINE__, PARAM_ARRAY_DIMENSION_MISMATCH, getName());
@@ -415,20 +426,12 @@ namespace Silecs
pSendValue_ = calloc(dimension1_*dimension2_, size_);
}
}
-
- /* The synchronization mode and the Access type of the register must be compatible:
- * - Read-only register cannot have SLAVE synchronization (not supported: has to be Read-Write register)
- * - Write-only register cannot have MASTER synchronization (does not make sense)
- */
- if ( ((accessType_ == Input) && (synchro_ == Slave) ) ||
- ((accessType_ == Output) && (synchro_ == Master) ))
- throw SilecsException(__FILE__, __LINE__, DATA_SYNCHRO_ACCESS_TYPE_MISMATCH, name_);
}
template <typename T>
inline void Register::setVal(FormatType F, T val)
{
- if (!hasOutputAccess())
+ if (!isWritable())
throw SilecsException(__FILE__, __LINE__, DATA_WRITE_ACCESS_TYPE_MISMATCH, getName());
if ((format_ != F) || (dimension1_ != 1))
throw SilecsException(__FILE__, __LINE__, PARAM_FORMAT_TYPE_MISMATCH, getName());
@@ -439,7 +442,7 @@ namespace Silecs
template <typename T>
inline void Register::setValArray(FormatType F, const T* pVal, uint32_t dim)
{
- if (!hasOutputAccess())
+ if (!isWritable())
throw SilecsException(__FILE__, __LINE__, DATA_WRITE_ACCESS_TYPE_MISMATCH, getName());
if (format_ != F)
throw SilecsException(__FILE__, __LINE__, PARAM_FORMAT_TYPE_MISMATCH, getName());
@@ -452,7 +455,7 @@ namespace Silecs
template <typename T>
inline void Register::setValArray2D(FormatType F, const T* pVal, uint32_t dim1, uint32_t dim2)
{
- if (!hasOutputAccess())
+ if (!isWritable())
throw SilecsException(__FILE__, __LINE__, DATA_WRITE_ACCESS_TYPE_MISMATCH, getName());
if (format_ != F)
throw SilecsException(__FILE__, __LINE__, PARAM_FORMAT_TYPE_MISMATCH, getName());
@@ -465,7 +468,7 @@ namespace Silecs
template <typename Tsrc, typename Tdst>
inline void Register::convSetValArray(FormatType F, const Tsrc* pVal, uint32_t dim)
{
- if (!hasOutputAccess())
+ if (!isWritable())
throw SilecsException(__FILE__, __LINE__, DATA_WRITE_ACCESS_TYPE_MISMATCH, getName());
if (format_ != F)
throw SilecsException(__FILE__, __LINE__, PARAM_FORMAT_TYPE_MISMATCH, getName());
@@ -480,7 +483,7 @@ namespace Silecs
template <typename Tsrc, typename Tdst>
inline void Register::convSetValArray2D(FormatType F, const Tsrc* pVal, uint32_t dim1, uint32_t dim2)
{
- if (!hasOutputAccess())
+ if (!isWritable())
throw SilecsException(__FILE__, __LINE__, DATA_WRITE_ACCESS_TYPE_MISMATCH, getName());
if (format_ != F)
throw SilecsException(__FILE__, __LINE__, PARAM_FORMAT_TYPE_MISMATCH, getName());
@@ -496,7 +499,7 @@ namespace Silecs
// No template for string format
void Register::setValString(std::string val)
{
- if (!hasOutputAccess())
+ if (!isWritable())
throw SilecsException(__FILE__, __LINE__, DATA_WRITE_ACCESS_TYPE_MISMATCH, getName());
if ((format_ != String) || (dimension1_ != 1)|| (dimension2_ != 1))
throw SilecsException(__FILE__, __LINE__, PARAM_FORMAT_TYPE_MISMATCH, getName());
@@ -508,7 +511,7 @@ namespace Silecs
void Register::setValStringArray(const std::string* pVal, uint32_t dim)
{
- if (!hasOutputAccess())
+ if (!isWritable())
throw SilecsException(__FILE__, __LINE__, DATA_WRITE_ACCESS_TYPE_MISMATCH, getName());
if (format_ != String)
throw SilecsException(__FILE__, __LINE__, PARAM_FORMAT_TYPE_MISMATCH, getName());
@@ -524,7 +527,7 @@ namespace Silecs
void Register::setValStringArray2D(const std::string* pVal, uint32_t dim1, uint32_t dim2)
{
- if (!hasOutputAccess())
+ if (!isWritable())
throw SilecsException(__FILE__, __LINE__, DATA_WRITE_ACCESS_TYPE_MISMATCH, getName());
if (format_ != String)
throw SilecsException(__FILE__, __LINE__, PARAM_FORMAT_TYPE_MISMATCH, getName());
@@ -641,14 +644,11 @@ namespace Silecs
FormatType Register::getFormat() { return format_; }
std::string Register::getBlockName() { return blockName_; }
std::string Register::getFormatAsString() { return FormatTypeString[format_]; }
- SynchroType Register::getSynchroType() { return synchro_; }
- std::string Register::getSynchroTypeAsString() { return SynchroTypeString[synchro_]; }
- bool Register::hasInputAccess() { return (accessType_ != Output); }
- bool Register::hasOutputAccess() { return (accessType_ != Input); }
+ bool Register::isReadable() { return (accessType_ != Output); }
+ bool Register::isWritable() { return (accessType_ != Input); }
- bool Register::isRetentive() { return (synchro_ != No); }
- bool Register::isVolatile() { return (synchro_ == No); }
+ bool Register::isVolatile(){ return isVolatile_; }
bool Register::isScalar() { return ((dimension1_ == 1) && (dimension2_ == 1)); }
bool Register::isSingleArray() { return ((dimension1_ > 1) && (dimension2_ == 1)); }
bool Register::isDoubleArray() { return (dimension2_ > 1); }
@@ -774,7 +774,7 @@ namespace Silecs
std::string Register::getInputValAsString(unsigned long i) { return getInputValAsString(i, 0); };
std::string Register::getInputValAsString(unsigned long i, unsigned long j)
{
- if (hasInputAccess())
+ if (isReadable())
{ return getValAsString(pRecvValue_,i,j);
}
else
@@ -786,7 +786,7 @@ namespace Silecs
std::string Register::getOutputValAsString(unsigned long i) { return getOutputValAsString(i, 0); };
std::string Register::getOutputValAsString(unsigned long i, unsigned long j)
{
- if (hasOutputAccess())
+ if (isWritable())
{ return getValAsString(pSendValue_,i,j);
}
else
@@ -846,14 +846,14 @@ namespace Silecs
timeval Register::getTimeStamp()
{
- if (hasInputAccess()) return tod_;
+ if (isReadable()) return tod_;
throw SilecsException(__FILE__, __LINE__, PARAM_NO_TIME_STAMP, getName());
}
std::string Register::getTimeStampAsString()
{
- if (hasInputAccess())
+ if (isReadable())
{
std::ostringstream os;
double ts = (double)tod_.tv_sec + (double)tod_.tv_usec/1000000.0; //second
@@ -868,17 +868,17 @@ namespace Silecs
void Register::printVal()
{
std::ostringstream os;
- os << getName() << " " << getFormatAsString() << "[" << dimension1_ << "][" << dimension2_ << "] " << getSynchroTypeAsString();
+ os << getName() << " " << getFormatAsString() << "[" << dimension1_ << "][" << dimension2_ << "] ";
if(getFormat() == String) os << ", string-length: " << getLength();
- if (hasInputAccess()) {
+ if (isReadable()) {
os << ", input: ";
for (unsigned int i=0; i<dimension1_; i++)
for (unsigned int j=0; j<dimension2_; j++)
os << getValAsString(pRecvValue_, i, j) << " ";
}
- if (hasOutputAccess()) {
+ if (isWritable()) {
os << ", output: ";
for (unsigned int i=0; i<dimension1_; i++)
for (unsigned int j=0; j<dimension2_; j++)
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsRegister.h b/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsRegister.h
index 5a5023c2086fc704c0f8c4d8f71c54aee57735d9..66cd817b32434b39690374a7af61ba598e012267 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsRegister.h
+++ b/silecs-communication-cpp/src/silecs-communication/interface/equipment/SilecsRegister.h
@@ -53,16 +53,6 @@ namespace Silecs
"String" /*!<: String of ASCII characters*/
};
- // Register synchronization type
- static const std::string SynchroTypeString[] =
- {
- "Master", //register is retentive, PLC is the source
- "Slave", //register is retentive, client is the source
- "NoSynchro" //register is volatile
- };
- /// @endcond
-
-
/*!
* \brief Enumeration for the Register data type. Used by Register::getFormat() method.
* Each type has a PLC type equivalent (see below)
@@ -141,18 +131,6 @@ namespace Silecs
*/
uint32_t getLength();
- /*!
- * \brief Returns the synchronization type of the current register (Master, Slave or No)
- * \return value from the SynchroType enumeration
- */
- SynchroType getSynchroType();
-
- /*!
- * \brief Returns the synchronization type of the current register
- * \return String value of the Synchronization type ("Master", "Slave" or "NoSynchro")
- */
- std::string getSynchroTypeAsString();
-
/*!
* \brief Returns the name of the block which contains the register as defined in the Class design
* \return Block name of the register
@@ -167,26 +145,9 @@ namespace Silecs
*/
timeval getTimeStamp();
- /*!
- * \brief A register can have read-only, write-only or read-write access mode as defined in the Class design.
- * \return true if register has read-only or read-write access mode
- */
- bool hasInputAccess();
+ bool isReadable();
- /*!
- * \brief A register can have read-only, write-only or read-write access mode as defined in the Class design.
- * \return true if the register has write-only or read-write access mode
- */
- bool hasOutputAccess();
-
- /*!
- * \brief A retentive register can be a persistent or a constant data.
- * Its value must be initialized at the system start-up.
- * - From the client side if the synchro register is 'Slave'
- * - From the PLC side if the synchro register is 'Master'
- * \return true if the register has Master or Slave synchro as defined in the Class design
- */
- bool isRetentive();
+ bool isWritable();
/*!
* \brief A register that has not persistent or constant value is Volatile.
@@ -1681,9 +1642,6 @@ namespace Silecs
/// data address within the PLC memory (from the block base-address)
unsigned long address_;
- /// Synchronization mode: Master, Slave, No
- SynchroType synchro_;
-
/// Flag used to check if the register has been setted once at least.
/// Uploading Slave registers at connection time is allowed only if all
/// the retentive Slave registers are initialized!
@@ -1697,6 +1655,8 @@ namespace Silecs
/// Name of the "parent" Block name (for general information)
std::string blockName_;
+ bool isVolatile_;
+
// Time-of-day: number of seconds and microseconds since the POSIX.1 Epoch (00:00:00 UTC, January 1, 1970)
// Use to time-stamp the register coming from PLC (no time-stamping on send).
// FEC clock and Timing are synchronized using SNTP (common GPS source)
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/utility/SilecsException.cpp b/silecs-communication-cpp/src/silecs-communication/interface/utility/SilecsException.cpp
index ae114f73de6a4132a11092d48ae65043dab08814..8274e22457264fdb15506bcd7c8f1122122b4317 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/utility/SilecsException.cpp
+++ b/silecs-communication-cpp/src/silecs-communication/interface/utility/SilecsException.cpp
@@ -147,10 +147,6 @@ namespace Silecs
errCategory_ = DATA_FAULT;
errMessage_ = "Block Design has a wrong access-type: ";
break;
- case DATA_UNKNOWN_SYNCHRO_TYPE:
- errCategory_ = DATA_FAULT;
- errMessage_ = "Register Design has a wrong synchronization type: ";
- break;
case DATA_UNKNOWN_PLC_MANUFACTURER:
errCategory_ = DATA_FAULT;
errMessage_ = "Controller Deployment has a wrong manufacturer: ";
@@ -175,10 +171,6 @@ namespace Silecs
errCategory_ = DATA_FAULT;
errMessage_ = "Trying to write a read-only register: ";
break;
- case DATA_SYNCHRO_ACCESS_TYPE_MISMATCH:
- errCategory_ = DATA_FAULT;
- errMessage_ = "Synchronization and Access types of this register are not compatible: ";
- break;
case DATA_ARRAY_LENGTH_MISMATCH:
errCategory_ = DATA_FAULT;
errMessage_ = "ArrCOMM_BLOCK_RESIZING_NOT_ALLOWEDay length is not compatible: ";
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/utility/SilecsException.h b/silecs-communication-cpp/src/silecs-communication/interface/utility/SilecsException.h
index 5d1f5f8031dfab8bca75ef453bdd21c0dfa2a3c2..1cc455c255fe876a221bfc5ba00eb20fb97d6d1d 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/utility/SilecsException.h
+++ b/silecs-communication-cpp/src/silecs-communication/interface/utility/SilecsException.h
@@ -60,14 +60,12 @@ namespace Silecs
XML_DATA_TYPE_MISMATCH,
DATA_UNKNOWN_FORMAT_TYPE,
DATA_UNKNOWN_ACCESS_TYPE,
- DATA_UNKNOWN_SYNCHRO_TYPE,
DATA_UNKNOWN_PLC_MANUFACTURER,
DATA_UNKNOWN_PLC_MODEL,
DATA_UNKNOWN_PLC_SYSTEM,
DATA_UNKNOWN_PROTOCOL_MODE,
DATA_READ_ACCESS_TYPE_MISMATCH,
DATA_WRITE_ACCESS_TYPE_MISMATCH,
- DATA_SYNCHRO_ACCESS_TYPE_MISMATCH,
DATA_ARRAY_LENGTH_MISMATCH,
PARAM_INCORRECT_ARGUMENTS,
PARAM_FILE_NOT_FOUND,
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/utility/XMLParser.cpp b/silecs-communication-cpp/src/silecs-communication/interface/utility/XMLParser.cpp
index 488c853229c3fa7dca24e3f971361a7865cb9bad..a3192240f1f3fdb57d29a6dbb5ffe51c391caead 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/utility/XMLParser.cpp
+++ b/silecs-communication-cpp/src/silecs-communication/interface/utility/XMLParser.cpp
@@ -187,6 +187,18 @@ ElementXML XMLParser::getFirstElementFromXPath(const std::string& xpathExpressio
return result.get()[0];
}
+ElementXML XMLParser::getSingleElementFromXPath(const std::string& xpathExpression) const
+{
+ boost::optional<boost::ptr_vector<ElementXML> > result = getElementsFromXPath_throwIfEmpty(xpathExpression);
+ if (result.get().size() > 1)
+ {
+ std::ostringstream message;
+ message << "The xpathExpression: '" << xpathExpression << "' returns more than one XML-Elements";
+ throw SilecsException(__FILE__, __LINE__, message.str().c_str());
+ }
+ return result.get()[0];
+}
+
xmlChar* XMLParser::ConvertInput(const char *in, const char *encoding)
{
xmlChar *out;
diff --git a/silecs-communication-cpp/src/silecs-communication/interface/utility/XMLParser.h b/silecs-communication-cpp/src/silecs-communication/interface/utility/XMLParser.h
index b403b40026601735079c3aab44dde5904b6c7100..addc43c47470eaae14ac0d682f42e01b0075f2fd 100644
--- a/silecs-communication-cpp/src/silecs-communication/interface/utility/XMLParser.h
+++ b/silecs-communication-cpp/src/silecs-communication/interface/utility/XMLParser.h
@@ -66,7 +66,7 @@ class ElementXML
{
public:
/*!
- * \brief name of the element
+ * \brief name of the xml-node
*/
std::string name_;
@@ -109,7 +109,7 @@ class ElementXML
}
}
std::ostringstream message;
- message << "The XML Attribute " << (*attributeIter)->name_ << " was not found";
+ message << "The XML Attribute '" << attributeName << "' was not found";
throw SilecsException(__FILE__, __LINE__, message.str().c_str());
}
};
@@ -142,6 +142,8 @@ class XMLParser
*/
virtual boost::optional<boost::ptr_vector<ElementXML> > getElementsFromXPath(const std::string& xpathExpression) const;
+ virtual ElementXML getSingleElementFromXPath(const std::string& xpathExpression) const;
+
virtual ElementXML getFirstElementFromXPath(const std::string& xpathExpression) const;
virtual boost::ptr_vector<ElementXML> getElementsFromXPath_throwIfEmpty(const std::string& xpathExpression) const;
diff --git a/silecs-diagnostic-cpp/.cproject b/silecs-diagnostic-cpp/.cproject
index bf123f3919aebd79b80d4e4d566e92edfaf72804..9eed05321f96bc52ff4af3bc809c771ec3bb160d 100644
--- a/silecs-diagnostic-cpp/.cproject
+++ b/silecs-diagnostic-cpp/.cproject
@@ -5,7 +5,7 @@
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="cdt.managedbuild.config.gnu.exe.debug.1063983837" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
- <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
@@ -21,23 +21,23 @@
<builder buildPath="${workspace_loc:/silecs-diagnostic-cpp}" id="cdt.managedbuild.target.gnu.builder.exe.debug.153658845" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="cdt.managedbuild.target.gnu.builder.exe.debug"/>
<tool id="cdt.managedbuild.tool.gnu.archiver.base.160739010" name="GCC Archiver" superClass="cdt.managedbuild.tool.gnu.archiver.base"/>
<tool id="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug.1203858904" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.exe.debug">
- <option id="gnu.cpp.compiler.exe.debug.option.optimization.level.894792522" name="Optimization Level" superClass="gnu.cpp.compiler.exe.debug.option.optimization.level" value="gnu.cpp.compiler.optimization.level.none" valueType="enumerated"/>
- <option id="gnu.cpp.compiler.exe.debug.option.debugging.level.2108944082" name="Debug Level" superClass="gnu.cpp.compiler.exe.debug.option.debugging.level" value="gnu.cpp.compiler.debugging.level.max" valueType="enumerated"/>
- <option id="gnu.cpp.compiler.option.include.paths.464457323" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" valueType="includePath">
+ <option id="gnu.cpp.compiler.exe.debug.option.optimization.level.894792522" name="Optimization Level" superClass="gnu.cpp.compiler.exe.debug.option.optimization.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.optimization.level.none" valueType="enumerated"/>
+ <option id="gnu.cpp.compiler.exe.debug.option.debugging.level.2108944082" name="Debug Level" superClass="gnu.cpp.compiler.exe.debug.option.debugging.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.debugging.level.max" valueType="enumerated"/>
+ <option id="gnu.cpp.compiler.option.include.paths.464457323" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
<listOptionValue builtIn="false" value=""${workspace_loc:/silecs-communication-cpp/build/include}""/>
<listOptionValue builtIn="false" value="/usr/lib64/qt4/mkspecs/linux-g++-64"/>
<listOptionValue builtIn="false" value="/usr/include/QtCore"/>
<listOptionValue builtIn="false" value="/usr/include/QtGui"/>
<listOptionValue builtIn="false" value="/acc/local/L866/cmw/cmw-rbac/6.1.0/include"/>
</option>
- <option id="gnu.cpp.compiler.option.preprocessor.def.1628203586" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" valueType="definedSymbols">
+ <option id="gnu.cpp.compiler.option.preprocessor.def.1628203586" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" useByScannerDiscovery="false" valueType="definedSymbols">
<listOptionValue builtIn="false" value="WITH_RBAC=1"/>
</option>
<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.2102143749" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
</tool>
<tool id="cdt.managedbuild.tool.gnu.c.compiler.exe.debug.77525709" name="GCC C Compiler" superClass="cdt.managedbuild.tool.gnu.c.compiler.exe.debug">
- <option defaultValue="gnu.c.optimization.level.none" id="gnu.c.compiler.exe.debug.option.optimization.level.2144307006" name="Optimization Level" superClass="gnu.c.compiler.exe.debug.option.optimization.level" valueType="enumerated"/>
- <option id="gnu.c.compiler.exe.debug.option.debugging.level.1892440763" name="Debug Level" superClass="gnu.c.compiler.exe.debug.option.debugging.level" value="gnu.c.debugging.level.max" valueType="enumerated"/>
+ <option defaultValue="gnu.c.optimization.level.none" id="gnu.c.compiler.exe.debug.option.optimization.level.2144307006" name="Optimization Level" superClass="gnu.c.compiler.exe.debug.option.optimization.level" useByScannerDiscovery="false" valueType="enumerated"/>
+ <option id="gnu.c.compiler.exe.debug.option.debugging.level.1892440763" name="Debug Level" superClass="gnu.c.compiler.exe.debug.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.2107742755" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
</tool>
<tool id="cdt.managedbuild.tool.gnu.c.linker.exe.debug.790245700" name="GCC C Linker" superClass="cdt.managedbuild.tool.gnu.c.linker.exe.debug"/>
@@ -64,7 +64,7 @@
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="cdt.managedbuild.config.gnu.exe.release.1657185205" moduleId="org.eclipse.cdt.core.settings" name="Release">
<externalSettings/>
<extensions>
- <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+ <extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
@@ -139,18 +139,18 @@
</storageModule>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets">
<buildTargets>
- <target name="clean LOCAL" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+ <target name="clean" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
- <buildTarget>clean LOCAL=TRUE</buildTarget>
+ <buildTarget>clean</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand>
<runAllBuilders>true</runAllBuilders>
</target>
- <target name="x86_64 LOCAL" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+ <target name="x86_64" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
<buildCommand>make</buildCommand>
<buildArguments/>
- <buildTarget>CPU=x86_64 -j1 LOCAL=TRUE</buildTarget>
+ <buildTarget>CPU=x86_64 -j1</buildTarget>
<stopOnError>true</stopOnError>
<useDefaultCommand>true</useDefaultCommand>
<runAllBuilders>true</runAllBuilders>
diff --git a/silecs-diagnostic-cpp/.settings/language.settings.xml b/silecs-diagnostic-cpp/.settings/language.settings.xml
index 1d5ad43cdb798e5d5376058ed49bf392988ac736..815530adab29195e3111d115e0895d6cfa207d13 100644
--- a/silecs-diagnostic-cpp/.settings/language.settings.xml
+++ b/silecs-diagnostic-cpp/.settings/language.settings.xml
@@ -5,7 +5,7 @@
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
- <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-226963044723472530" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-226059455508497530" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
@@ -16,7 +16,7 @@
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
- <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-226963044723472530" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
+ <provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-226059455508497530" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
<language-scope id="org.eclipse.cdt.core.g++"/>
</provider>
diff --git a/silecs-diagnostic-cpp/src/silecs-diagnostic/diagnostictoolmainview.cpp b/silecs-diagnostic-cpp/src/silecs-diagnostic/diagnostictoolmainview.cpp
index 142acd2701653acb4f862b44df556a5ce513fe74..991e0e9f5e32a29f31bc660e7b09c1c57826bc35 100755
--- a/silecs-diagnostic-cpp/src/silecs-diagnostic/diagnostictoolmainview.cpp
+++ b/silecs-diagnostic-cpp/src/silecs-diagnostic/diagnostictoolmainview.cpp
@@ -18,6 +18,7 @@
#include <silecs-diagnostic/utils.h>
#include <silecs-communication/interface/utility/XMLParser.h>
+#include <silecs-communication/interface/utility/SilecsException.h>
#include <exception>
extern silecsModule *mysilecs;
@@ -197,6 +198,11 @@ void diagnosticToolMainView::loadFiles()
}while(blockListSplitted3);
}
}
+ catch (const Silecs::SilecsException& ex)
+ {
+ std::cout << "Test"<< std::endl;
+ Utils::logError(ui->console, ex.what());
+ }
catch(std::string *str)
{
Utils::logError(ui->console,*str);
@@ -251,7 +257,10 @@ void diagnosticToolMainView::on_connectButton_clicked()
Utils::displayPLCInformation(plc,ui->InformationMessage);
//highlight PLC background in green
- ui->treeWidget->currentItem()->setBackgroundColor(0,Qt::green);
+ currentItem->setBackgroundColor(0,Qt::green);
+
+ //show the run-state of the PLC
+ mysilecs->updatePLCRunState(currentItem);
// Increment number of connected PLC
mysilecs->counterConnectedPLC++;
@@ -284,6 +293,9 @@ void diagnosticToolMainView::on_disconnectButton_clicked()
// Cast the linked object PLC type
Silecs::PLC* plc = (Silecs::PLC*)(currentItem->getLinkedObject());
+ //update the runstate
+ mysilecs->updatePLCRunState(currentItem);
+
// Disconnect
plc->disconnect();
@@ -523,7 +535,7 @@ void diagnosticToolMainView::on_treeWidget_doubleClicked(const QModelIndex &inde
markItemNotEdiable(itm);
return;
case 3:// double click performed on 3th column (local value)
- if(!reg->hasOutputAccess() )// is READ only for silecs or is wrong column
+ if(!reg->isWritable() )// is READ only for silecs or is wrong column
{
markItemNotEdiable(itm);
return;
@@ -747,14 +759,18 @@ void diagnosticToolMainView::fillClassNameComboBox()
{
Utils::logInfo(ui->console,"Loading deploy file: " + deployFile);
XMLParser parserDeploy(deployFile,true);
- boost::ptr_vector<ElementXML> classNodes = parserDeploy.getElementsFromXPath_throwIfEmpty("/SILECS-Deploy/Controller/SilecsDesign");
- if(classNodes.size() == 0)
+ boost::ptr_vector<ElementXML> classNodes;
+ try
{
- Utils::logError(ui->console,"No classes found for this Deploy");
+ classNodes = parserDeploy.getElementsFromXPath_throwIfEmpty("/SILECS-Deploy/Controller/SilecsDesign");
+ }
+ catch(const Silecs::SilecsException& ex2)
+ {
+ Utils::logError(ui->console,"No classes found for this Deploy: " + deployFile + ". Exception: " + ex2.what());
return;
}
- QStringList list;
+ QStringList list;
boost::ptr_vector<ElementXML>::const_iterator classIter;
for(classIter = classNodes.begin(); classIter != classNodes.end(); classIter++)
{
@@ -762,6 +778,8 @@ void diagnosticToolMainView::fillClassNameComboBox()
if(!list.contains(className))
list += className;
}
+ QString headerName(HEADER_NAME.c_str());
+ list += headerName;
ui->classNameComboBox->clear();
ui->classNameComboBox->addItems(list);
}
diff --git a/silecs-diagnostic-cpp/src/silecs-diagnostic/silecsmodule.cpp b/silecs-diagnostic-cpp/src/silecs-diagnostic/silecsmodule.cpp
index a716747c3f9534079994c7f72a5982a4c350e4c6..b264bdea2c55a398421237893ce6739ea6587208 100755
--- a/silecs-diagnostic-cpp/src/silecs-diagnostic/silecsmodule.cpp
+++ b/silecs-diagnostic-cpp/src/silecs-diagnostic/silecsmodule.cpp
@@ -79,113 +79,141 @@ void silecsModule::enableDebugLog()
debugLoggingEnabled_ = true;
}
-Item *silecsModule::generateTree(string className, string deployFile)
+void silecsModule::updatePLCRunState(Item *plcItem)
{
- Item *root = NULL;
- try{
+ int index = 1;
+ try
+ {
+ Silecs::PLC* plc = (Silecs::PLC*)(plcItem->getLinkedObject());
+ if( !plc->isConnected() )
+ {
+ plcItem->setText(index,"");
+ plcItem->setBackgroundColor(index,Qt::white);
+ }
+ if( plc->isRunning() )
+ {
+ plcItem->setText(index,"running");
+ plcItem->setBackgroundColor(index,Qt::green);
+ }
+ else
+ {
+ plcItem->setText(index,"stopped");
+ plcItem->setBackgroundColor(index,Qt::yellow);
+ }
+ }
+ catch(const Silecs::SilecsException& ex2)
+ {
+ plcItem->setText(index,"state unknown");
+ plcItem->setBackgroundColor(index,Qt::red);
+ std::string message = "Failed to obtain plc run-state: ";
+ message += ex2.what();
+ Utils::logError(messageConsole_,message);
+ }
+
+}
- Utils::logInfo(messageConsole_,"Loading deploy file: " + deployFile);
- XMLParser parserDeploy(deployFile,true);
+Item *silecsModule::generateTree(string className, string deployFile)
+{
+ Utils::logInfo(messageConsole_,"Loading deploy file: " + deployFile);
+ XMLParser parserDeploy(deployFile,true);
+ Item *root = new Item(silecsCluster);
+ if( className == HEADER_NAME )
+ {
+ silecsCluster = silecsService->getCluster(HEADER_NAME,HEADER_VERSION);
+ root->setText(0,QString::fromStdString(HEADER_NAME+" v"+HEADER_VERSION));
+ }
+ else
+ {
ElementXML silecsDesign = parserDeploy.getFirstElementFromXPath("/SILECS-Deploy/Controller/SilecsDesign[@silecs-design-name='" + className + "']");
string classVersion = silecsDesign.getAttribute("silecs-design-version");
- ElementXML deployUnitNode = parserDeploy.getFirstElementFromXPath("/SILECS-Deploy/Deploy-Unit");
- string deployName = deployUnitNode.getAttribute("name");
-
- silecsCluster = silecsService->getCluster(className,classVersion);
- root = new Item(silecsCluster);
+ silecsCluster = silecsService->getCluster(className,classVersion);
root->setText(0,QString::fromStdString(className+" v"+classVersion));
- root->setWhatsThis(0,QString::fromStdString(CLUSTER_TYPE));
- root->setLinkedObject(silecsCluster);
+ }
+ root->setWhatsThis(0,QString::fromStdString(CLUSTER_TYPE));
+ root->setLinkedObject(silecsCluster);
- boost::ptr_vector<ElementXML> controllerNodes = parserDeploy.getElementsFromXPath_throwIfEmpty("/SILECS-Deploy/Controller");
- if(controllerNodes.size() == 0)
+ boost::ptr_vector<ElementXML> controllerNodes = parserDeploy.getElementsFromXPath_throwIfEmpty("/SILECS-Deploy/Controller");
+ boost::ptr_vector<ElementXML>::const_iterator controllerIter;
+ for(controllerIter = controllerNodes.begin(); controllerIter != controllerNodes.end(); controllerIter++)
+ {
+ std::string plcName = controllerIter->getAttribute("host-name");
+ if(plcName.compare("")==true)
{
- Utils::logError(messageConsole_,"No controller defined");
- return root;
+ Utils::logError(messageConsole_,"PLC name empty - will be skipped");
+ break;
}
- boost::ptr_vector<ElementXML>::const_iterator controllerIter;
- for(controllerIter = controllerNodes.begin(); controllerIter != controllerNodes.end(); controllerIter++)
+ Silecs::PLC *plc;
+ string parameterFile = "";
+ try
{
- std::string plcName = controllerIter->getAttribute("host-name");
- if(plcName.compare("")==true)
- {
- Utils::logError(messageConsole_,"PLC name empty - will be skipped");
- break;
- }
- Silecs::PLC *plc;
- try
- {
- std::size_t deployFolderPos = deployFile.find(deployName);
- string deployProject = deployFile.substr(0,deployFolderPos) + deployName;
- string parameterFile = deployProject + "/generated/client/" + plcName + ".silecsparam";
-
- Utils::logInfo(messageConsole_,"Loading parameter file: " + parameterFile);
- plc = silecsCluster->getPLC(plcName,parameterFile);
- }
- catch(const Silecs::SilecsException& ex2)
- {
- Utils::logError(messageConsole_,"Error while loading "+ plcName+". "+ ex2.what());
- continue;
- }
-
- // add plc on the tree
- Item *plcItem = Utils::addTreeItem(root,QString::fromStdString(plcName),
- "",QString::fromStdString(PLC_TYPE),plc,":/Images/PLC.png");
+ ElementXML deployUnitNode = parserDeploy.getFirstElementFromXPath("/SILECS-Deploy/Deploy-Unit");
+ string deployName = deployUnitNode.getAttribute("name");
+ std::size_t deployFolderPos = deployFile.find(deployName);
+ string deployProject = deployFile.substr(0,deployFolderPos) + deployName;
+ parameterFile = deployProject + "/generated/client/" + plcName + ".silecsparam";
+
+ Utils::logInfo(messageConsole_,"Loading parameter file: " + parameterFile);
+ plc = silecsCluster->getPLC(plcName,parameterFile);
+ }
+ catch(const Silecs::SilecsException& ex2)
+ {
+ Utils::logError(messageConsole_,"Error while loading "+ plcName+". "+ ex2.what());
+ continue;
+ }
- // get devices for the current PLC
- deviceVectorType deviceMap = plc->getDeviceMap();
+ // add plc on the tree
+ Item *plcItem = Utils::addTreeItem(root,QString::fromStdString(plcName),"",QString::fromStdString(PLC_TYPE),plc,":/Images/PLC.png");
- deviceVectorType::iterator pDeviceIter;
- for(pDeviceIter = deviceMap.begin(); pDeviceIter != deviceMap.end(); ++pDeviceIter)
- {
- std::string deviceName = pDeviceIter->first;
+ boost::ptr_vector<ElementXML> instances;
+ XMLParser parseParam(parameterFile,true);
+ try
+ {
+ instances = parseParam.getElementsFromXPath_throwIfEmpty("/SILECS-Param/SILECS-Mapping/SILECS-Class[@name='" + className + "']/Instance");
+ }
+ catch(const Silecs::SilecsException& ex2)
+ {
+ Utils::logError(messageConsole_,"Failed to fetch instances for class '" + className + "' from parameter-file '" + parameterFile + "':" + ex2.what());
+ break;
+ }
- Silecs::Device *device = pDeviceIter->second;
- Utils::logInfo(messageConsole_,"found device: '" + deviceName + "' in parameter-file");
+ boost::ptr_vector<ElementXML>::iterator pInstanceIter;
+ for(pInstanceIter = instances.begin(); pInstanceIter != instances.end(); ++pInstanceIter)
+ {
+ std::string deviceName = pInstanceIter->getAttribute("label");
+ Utils::logInfo(messageConsole_,"found device: '" + deviceName + "' in parameter-file");
+ Silecs::Device *device = plc->getDevice(deviceName);
- // add device on the tree
- Item *deviceItem = Utils::addTreeItem(plcItem,QString::fromStdString(deviceName),"",QString::fromStdString(DEVICE_TYPE),device,":/Images/DEV.png");
+ // add device on the tree
+ Item *deviceItem = Utils::addTreeItem(plcItem,QString::fromStdString(deviceName),"",QString::fromStdString(DEVICE_TYPE),device,":/Images/DEV.png");
- // get register List for the current device
- std::string registerList = device->getRegisterList();
- istringstream registerListSplitted(registerList);
+ // get register List for the current device
+ std::string registerList = device->getRegisterList();
+ istringstream registerListSplitted(registerList);
- do
- {
- std::string registerName;
- registerListSplitted >> registerName;
+ do
+ {
+ std::string registerName;
+ registerListSplitted >> registerName;
- //avoid last empty register
- if(registerName.compare("")==0) break;
+ //avoid last empty register
+ if(registerName.compare("")==0) break;
- Utils::logInfo(messageConsole_,"found Register: '" + registerName + "' in parameter file");
- Silecs::Register *reg = device->getRegister(registerName);
+ Utils::logInfo(messageConsole_,"found Register: '" + registerName + "' in parameter file");
+ Silecs::Register *reg = device->getRegister(registerName);
- Item *registerItem = Utils::addTreeItem(deviceItem,QString::fromStdString(registerName),"",QString::fromStdString(REGISTER_TYPE),reg,":/Images/REG.png" );
+ Item *registerItem = Utils::addTreeItem(deviceItem,QString::fromStdString(registerName),"",QString::fromStdString(REGISTER_TYPE),reg,":/Images/REG.png" );
- // Set the block name
- registerItem->setText(1 , QString::fromStdString(reg->getBlockName()));
+ // Set the block name
+ registerItem->setText(1 , QString::fromStdString(reg->getBlockName()));
- // Color background of input and output buffer
- registerItem->setBackgroundColor(2,QColor(255,255,204));//light yellow
- registerItem->setBackgroundColor(3,QColor(204,255,255));//light blue
+ // Color background of input and output buffer
+ registerItem->setBackgroundColor(2,QColor(255,255,204));//light yellow
+ registerItem->setBackgroundColor(3,QColor(204,255,255));//light blue
- }while(registerListSplitted);
- }
- } // END OF PLC LOOP
- }
- catch (const Silecs::SilecsException& ex)
- {
- std::string message = "getTreeroot - '";
- Utils::logError(messageConsole_, message + ex.what());
- return NULL;
- }
- catch(...)
- {
- Utils::logError(messageConsole_,"getTreeroot - Unknown Error '");
- return NULL;
- }
+ }while(registerListSplitted);
+ }
+ } // END OF PLC LOOP
// Reset the number of connected PLC
this->counterConnectedPLC =0;
@@ -902,6 +930,7 @@ void silecsModule::updateClusterItem(Item *Cluster,bool updateInputBufferOnly)
void silecsModule::updatePLCItem(Item *PLCItem,bool updateInputBufferOnly)
{
+ updatePLCRunState(PLCItem);
Silecs::PLC* plc = (Silecs::PLC*)(PLCItem->getLinkedObject());
Utils::logInfo(messageConsole_,std::string("updating controller: '") + plc->getName() + "'");
int numberOfdevice = PLCItem->childCount();
@@ -928,7 +957,7 @@ void silecsModule::updateDeviceItem(Item *deviceItem,bool updateInputBufferOnly)
// PLC values
try
{
- if(reg->hasInputAccess()) // is READ or READ+WRITE for silecs
+ if(reg->isReadable())
{
if(reg->isScalar())
{
@@ -958,7 +987,7 @@ void silecsModule::updateDeviceItem(Item *deviceItem,bool updateInputBufferOnly)
{
// local values
try{
- if(reg->hasOutputAccess()) // = is WRITE or READ+WRITE for silecs
+ if(reg->isWritable()) // = is WRITE or READ+WRITE for silecs
{
if(reg->isScalar())
{
diff --git a/silecs-diagnostic-cpp/src/silecs-diagnostic/silecsmodule.h b/silecs-diagnostic-cpp/src/silecs-diagnostic/silecsmodule.h
index 9e5a47760364327115a3f4df34cad50c56439d16..fea4e78e1a042636c8fb7d20b4b1f6705a2cfc58 100755
--- a/silecs-diagnostic-cpp/src/silecs-diagnostic/silecsmodule.h
+++ b/silecs-diagnostic-cpp/src/silecs-diagnostic/silecsmodule.h
@@ -68,6 +68,8 @@ public:
*/
~silecsModule();
+ void updatePLCRunState(Item *plcItem);
+
/**
*Generate the empty entire tree
*/
diff --git a/silecs-diagnostic-cpp/src/silecs-diagnostic/utils.cpp b/silecs-diagnostic-cpp/src/silecs-diagnostic/utils.cpp
index 85d3dc1691ffd0717abb9c2d72d88e1ac5b842bb..1ea5bfd2cc371e8b39c13c8bd18ffc1b54a4dc2f 100755
--- a/silecs-diagnostic-cpp/src/silecs-diagnostic/utils.cpp
+++ b/silecs-diagnostic-cpp/src/silecs-diagnostic/utils.cpp
@@ -184,22 +184,14 @@ void Utils::displayRegisterInformation(Silecs::Register *reg,QTextEdit *console)
text.append("<li>Last update: "+reg->getTimeStampAsString()+"</li>");
// Access method
- if(reg->hasInputAccess() && reg->hasOutputAccess())
+ if(reg->isReadable() && reg->isWritable())
text.append("<li>Access method: Read / Write </li>");
else
{
- if(reg->hasInputAccess()) text.append("<li>Access method: Read only </li>");
+ if(reg->isReadable()) text.append("<li>Access method: Read only </li>");
else text.append("<li>Access method: Write only </li>");
}
- text.append("<li>Synchronization method: "+reg->getSynchroTypeAsString()+"</li>");
-
- // Retentive volatile
- if(reg->isRetentive())
- text.append("<li>Storage method: Retentive</li>");
- else
- text.append("<li>Storage method: Volatile</li>");
-
text.append("</ul>");
console->setText(QString::fromStdString(text));
@@ -214,7 +206,7 @@ void Utils::displayRegisterValue(Silecs::Register *reg,
)
{
- if(!reg->hasInputAccess()){
+ if(!reg->isReadable()){
binValueLabel->setText("--Write only register--");
hexValueLabel->setText("--Write only register--");
decValueLabel->setText("--Write only register--");
diff --git a/silecs-model/src/xml/DesignSchema.xsd b/silecs-model/src/xml/DesignSchema.xsd
index aa754bc0e23c798a6e1f9e1de5b091d5c294c6d0..07073ebf7f172eb4c40a3bc7e0cbac4e44bf3066 100644
--- a/silecs-model/src/xml/DesignSchema.xsd
+++ b/silecs-model/src/xml/DesignSchema.xsd
@@ -90,52 +90,11 @@ along with this program. If not, see http://www.gnu.org/licenses/.-->
</xs:appinfo>
</xs:annotation>
<xs:complexType>
- <xs:sequence>
- <xs:element name="Description" type="xs:string" minOccurs="0"/>
- <xs:element name="Block" maxOccurs="unbounded">
- <xs:complexType>
- <xs:sequence>
- <xs:element name="Description" type="xs:string" minOccurs="0"/>
- <xs:element name="Register" type="RegisterType" maxOccurs="unbounded">
- <xs:annotation>
- <xs:appinfo>
- <doc>
- The Register is the elementary component of the SILECS data model.
- <br>Each variable has a unique name in the scope of the class (including all blocks).
- </doc>
- </xs:appinfo>
- </xs:annotation>
- </xs:element>
- </xs:sequence>
- <xs:attribute name="name" type="BlockNameType" use="required">
- <xs:annotation>
- <xs:appinfo>
- Defines the name of the block that must be unique in all the class.
- Must not exceed 12 characters.
- </xs:appinfo>
- </xs:annotation>
- </xs:attribute>
- <xs:attribute name="mode" use="required">
- <xs:annotation>
- <xs:documentation>Defines the access-mode of the block and finally of its related variables.</xs:documentation>
- </xs:annotation>
- <xs:simpleType>
- <xs:restriction base="xs:string">
- <xs:enumeration value="READ-ONLY"/>
- <xs:enumeration value="WRITE-ONLY"/>
- <xs:enumeration value="READ-WRITE"/>
- </xs:restriction>
- </xs:simpleType>
- </xs:attribute>
- <xs:attribute name="generateFesaProperty" type="xs:boolean" use="required">
- <xs:annotation>
- <xs:appinfo>
- Defines if the code-generation will generate a FESA-Property and the related Actions/Events/etc for this block
- </xs:appinfo>
- </xs:annotation>
- </xs:attribute>
- </xs:complexType>
- </xs:element>
+ <xs:sequence>
+ <xs:element name="Setting-Block" type="Setting-BlockType" minOccurs="0" maxOccurs="unbounded"/>
+ <xs:element name="Acquisition-Block" type="Acquisition-BlockType" minOccurs="0" maxOccurs="unbounded"/>
+ <xs:element name="Command-Block" type="Command-BlockType" minOccurs="0" maxOccurs="unbounded"/>
+ <xs:element name="Description" type="xs:string" minOccurs="0"/>
</xs:sequence>
<xs:attribute name="name" type="SilecsClassNameType" use="required"/>
<xs:attribute name="version" type="VersionType" use="required"/>
@@ -151,14 +110,22 @@ along with this program. If not, see http://www.gnu.org/licenses/.-->
</xs:simpleType>
</xs:attribute>
</xs:complexType>
- <xs:unique name="Register-name-per-class">
- <xs:selector xpath="Block/Register"/>
+ <xs:unique name="Register-name-has-to-be-unique">
+ <xs:selector xpath="*/*"/>
<xs:field xpath="@name"/>
</xs:unique>
- <xs:unique name="Block-name-per-class">
- <xs:selector xpath="Block"/>
+ <xs:unique name="Block-name-has-to-be-unique">
+ <xs:selector xpath="*"/>
<xs:field xpath="@name"/>
</xs:unique>
+ <xs:unique name="Property-name-has-to-be-unique">
+ <xs:selector xpath="*"/>
+ <xs:field xpath="@fesaPropertyName"/>
+ </xs:unique>
+ <xs:unique name="Field-name-has-to-be-unique">
+ <xs:selector xpath="*/*"/>
+ <xs:field xpath="@fesaFieldName"/>
+ </xs:unique>
</xs:element>
</xs:sequence>
<xs:attribute name="silecs-version" type="VersionType" use="required"/>
@@ -167,189 +134,235 @@ along with this program. If not, see http://www.gnu.org/licenses/.-->
</xs:complexType>
</xs:element>
-<xs:complexType name="RegisterType">
+
+<xs:complexType name="FesaCodegenType-ServerOnly">
<xs:sequence>
- <xs:element name="Description" type="xs:string" minOccurs="0"/>
</xs:sequence>
- <xs:attribute name="name" type="RegisterNameType" use="required">
- <xs:annotation>
- <xs:appinfo>
- <doc>Name must be unique and must respect the following standard: [_A-Za-z]+[_A-Za-z0-9]*</doc>
- </xs:appinfo>
- </xs:annotation>
- </xs:attribute>
- <xs:attribute name="format" type="FormatType" use="required">
- <xs:annotation>
- <xs:appinfo>
- <doc>
- <table border = "1">
- <tr>
- <th align="center"> Hardware types </th>
- <th align="center"> Client process types </th>
- </tr>
- <tr>
- <td align="center"> uint8 / byte </td>
- <td align="center"> uint8_t </td>
- </tr>
- <tr>
- <td align="center"> int8 / char </td>
- <td align="center"> int8_t </td>
- </tr>
- <tr>
- <td align="center"> uint16 / word </td>
- <td align="center"> uint16_t </td>
- </tr>
- <tr>
- <td align="center"> int16 / int </td>
- <td align="center"> int16_t </td>
- </tr>
- <tr>
- <td align="center"> uint32 / dword </td>
- <td align="center"> uint32_t </td>
- </tr>
- <tr>
- <td align="center"> int32 / dint </td>
- <td align="center"> int32_t </td>
- </tr>
- <tr>
- <td align="center"> uint64 </td>
- <td align="center"> uint64_t </td>
- </tr>
- <tr>
- <td align="center"> int64 </td>
- <td align="center"> int64_t </td>
- </tr>
- <tr>
- <td align="center"> float32 / real </td>
- <td align="center"> float </td>
- </tr>
- <tr>
- <td align="center"> float64 </td>
- <td align="center"> double </td>
- </tr>
- <tr>
- <td align="center"> date / dt </td>
- <td align="center"> double </td>
- </tr>
- <tr>
- <td align="center"> string / char[] </td>
- <td align="center"> string </td>
- </tr>
- </table>
- </doc>
- </xs:appinfo>
- </xs:annotation>
- </xs:attribute>
- <xs:attribute name="synchro" use="required">
+</xs:complexType>
+
+<xs:complexType name="FesaBlockCodegenConfigType">
+ <xs:sequence>
+ <xs:element name="Server" minOccurs="0">
+ <xs:complexType>
+ <xs:attribute name="fesaPropertyName" type="BlockNameType" use="required">
+ <xs:annotation>
+ <xs:appinfo>Defines the name of the generated Fesa-Property.</xs:appinfo>
+ </xs:annotation>
+ </xs:attribute>
+ </xs:complexType>
+ </xs:element>
+ </xs:sequence>
+</xs:complexType>
+
+<xs:complexType name="BlockType">
+ <xs:sequence>
+ <xs:element name="Description" type="xs:string" minOccurs="0"/>
+ </xs:sequence>
+ <xs:attribute name="name" type="BlockNameType" use="required">
+ <xs:annotation>
+ <xs:appinfo>
+ Defines the name of the block that must be unique in all the class.
+ Must not exceed 12 characters.
+ </xs:appinfo>
+ </xs:annotation>
+ </xs:attribute>
+ <xs:attribute name="generateFesaProperty" type="xs:boolean" use="required">
+ <xs:annotation>
+ <xs:appinfo>
+ Defines if the code-generation will generate a FESA-Property and the related Actions/Events/etc for this block
+ </xs:appinfo>
+ </xs:annotation>
+ </xs:attribute>
+ <xs:attribute name="fesaPropertyName" type="BlockNameType" use="optional">
+ <xs:annotation>
+ <xs:appinfo>Defines the name of the generated Fesa-Property. If not set, the Blockname will be used.</xs:appinfo>
+ </xs:annotation>
+ </xs:attribute>
+ <xs:attribute name="fesaGetServerActionName" type="BlockNameType" use="optional">
<xs:annotation>
- <xs:appinfo>
- <doc>
- initial value or processing value of persistent data must be up-to-date each time a connection is established.
- <br/>SILECS library supports automatic synchronization.
- <ul>
- <li>MASTER: PLC overwrites FEC register values. </li>
- <li>SLAVE: FEC overwrites PLC register values. </li>
- <li>NONE: no automatic synchronization performed. (volatile data) </li>
- </ul>
- </doc>
- </xs:appinfo>
+ <xs:appinfo>Defines the name of the generated Fesa-Server-Action. If not set, the Blockname will just be prefixed with get/set.</xs:appinfo>
</xs:annotation>
- <xs:simpleType>
- <xs:restriction base="xs:string">
- <xs:enumeration value="MASTER"/>
- <xs:enumeration value="SLAVE"/>
- <xs:enumeration value="NONE"/>
- </xs:restriction>
- </xs:simpleType>
</xs:attribute>
- <xs:attribute name="array-dim1" type="DimensionType" use="optional" default="1">
+ <xs:attribute name="fesaSetServerActionName" type="BlockNameType" use="optional">
<xs:annotation>
- <xs:appinfo>
- <doc>
- specify register dimension.
- <br/> if array-dim1 = 1 the register is a scalar. If array-dim1 > 1 the register is an array.
- </doc>
- </xs:appinfo>
+ <xs:appinfo>Defines the name of the generated Fesa-Server-Action. If not set, the Blockname will just be prefixed with get/set.</xs:appinfo>
</xs:annotation>
</xs:attribute>
- <xs:attribute name="array-dim2" type="DimensionType" use="optional" default="1">
+</xs:complexType>
+
+<xs:complexType name="Setting-BlockType">
+ <xs:complexContent>
+ <xs:extension base="BlockType">
+ <xs:sequence>
+ <xs:element name="Setting-Register" type="RegisterType" minOccurs="0" maxOccurs="unbounded">
+ <xs:annotation>
+ <xs:appinfo>
+ <doc>PLC Register which can be setted and read back by Silecs. The PLC should not modify it's value.</doc>
+ </xs:appinfo>
+ </xs:annotation>
+ </xs:element>
+ <xs:element name="Volatile-Register" type="RegisterType" minOccurs="0" maxOccurs="unbounded">
+ <xs:annotation>
+ <xs:appinfo>
+ <doc>PLC Register which can be set by both, Silecs and the PLC</doc>
+ </xs:appinfo>
+ </xs:annotation>
+ </xs:element>
+ </xs:sequence>
+ </xs:extension>
+ </xs:complexContent>
+</xs:complexType>
+
+<xs:complexType name="Acquisition-BlockType">
+ <xs:complexContent>
+ <xs:extension base="BlockType">
+ <xs:sequence>
+ <xs:element name="Acquisition-Register" type="RegisterType" minOccurs="0" maxOccurs="unbounded">
+ <xs:annotation>
+ <xs:appinfo>
+ <doc>PLC Register which is only read out by Silecs</doc>
+ </xs:appinfo>
+ </xs:annotation>
+ </xs:element>
+ </xs:sequence>
+ </xs:extension>
+ </xs:complexContent>
+</xs:complexType>
+
+<xs:complexType name="Command-BlockType">
+ <xs:complexContent>
+ <xs:extension base="BlockType">
+ <xs:sequence>
+ <xs:element name="Setting-Register" type="RegisterType" minOccurs="0" maxOccurs="unbounded">
+ <xs:annotation>
+ <xs:appinfo>
+ <doc>PLC Register which can be setted by Silecs. The PLC should not modify it's value.</doc>
+ </xs:appinfo>
+ </xs:annotation>
+ </xs:element>
+ </xs:sequence>
+ </xs:extension>
+ </xs:complexContent>
+</xs:complexType>
+
+
+<xs:complexType name="ScalarValueType">
+ <xs:attribute name="format" type="FormatType" use="required" />
+</xs:complexType>
+
+<xs:complexType name="ArrayValueType">
+ <xs:attribute name="format" type="FormatType" use="required" />
+ <xs:attribute name="dim" type="DimensionType" use="required"/>
+</xs:complexType>
+
+<xs:complexType name="Array2DValueType">
+ <xs:attribute name="format" type="FormatType" use="required" />
+ <xs:attribute name="dim1" type="DimensionType" use="required"/>
+ <xs:attribute name="dim2" type="DimensionType" use="required"/>
+</xs:complexType>
+
+<xs:complexType name="StringValueType">
+ <xs:attribute name="format" fixed="string" use="required" />
+ <xs:attribute name="string-length" type="LengthType" use="required"/>
+</xs:complexType>
+
+<xs:complexType name="StringArrayValueType">
+ <xs:attribute name="format" fixed="string" use="required" />
+ <xs:attribute name="string-length" type="LengthType" use="required"/>
+ <xs:attribute name="dim" type="DimensionType" use="required"/>
+</xs:complexType>
+
+<xs:complexType name="StringArray2DValueType">
+ <xs:attribute name="format" fixed="string" use="required" />
+ <xs:attribute name="string-length" type="LengthType" use="required"/>
+ <xs:attribute name="dim1" type="DimensionType" use="required"/>
+ <xs:attribute name="dim2" type="DimensionType" use="required"/>
+</xs:complexType>
+
+<xs:complexType name="RegisterType">
+ <xs:sequence>
+ <xs:element name="Description" type="xs:string" minOccurs="0"/>
+ <xs:choice>
+ <xs:element name="scalar" type="ScalarValueType" />
+ <xs:element name="array" type="ArrayValueType" />
+ <xs:element name="array2D" type="Array2DValueType" />
+ <xs:element name="string" type="StringValueType" />
+ <xs:element name="stringArray" type="StringArrayValueType" />
+ <xs:element name="stringArray2D" type="StringArray2DValueType" />
+ </xs:choice>
+ </xs:sequence>
+ <xs:attribute name="name" type="RegisterNameType" use="required">
<xs:annotation>
<xs:appinfo>
- <doc>
- specify second register dimension.
- <br/> if array-dim2 = 1 the register is monodimensional. If array-dim2 > 1 the register is bidimensional.
- </doc>
+ <doc>Name must be unique and must respect the following standard: [_A-Za-z]+[_A-Za-z0-9]*</doc>
</xs:appinfo>
</xs:annotation>
</xs:attribute>
- <xs:attribute name="string-len" type="LengthType" use="optional">
+ <xs:attribute name="generateFesaValueItem" type="xs:boolean" use="required">
<xs:annotation>
<xs:appinfo>
- <doc>specify length of string. If not specified, default value is 64.</doc>
+ Defines if the code-generation will generate a FESA-Value-Item for this Register
</xs:appinfo>
</xs:annotation>
</xs:attribute>
- <xs:attribute name="generateFesaValueItem" type="xs:boolean" use="required">
+ <xs:attribute name="fesaFieldName" type="RegisterNameType" use="optional">
<xs:annotation>
- <xs:appinfo>
- Defines if the code-generation will generate a FESA-Value-Item for this Register
- </xs:appinfo>
+ <xs:appinfo>Defines the name of the generated Fesa-Field. If not set, the Registername will be used.</xs:appinfo>
</xs:annotation>
</xs:attribute>
</xs:complexType>
-
- <xs:simpleType name="BlockNameType">
- <xs:restriction base="xs:string">
- <xs:minLength value="1"/>
- <xs:maxLength value="30"/>
- <!-- Siemens Support bezüglich der maximalen Zeichenlänge für PLC- Tags : S7-300/1200/1500er bei 128 Zeichen -->
- <!-- FESA PropertyNames have max. 30 characters. Since For each Block a prop is generated, we have to use this limit -->
- <xs:pattern value="[_A-Za-z]+[_A-Za-z0-9]*"/>
- </xs:restriction>
- </xs:simpleType>
- <xs:simpleType name="RegisterNameType">
- <xs:restriction base="xs:string">
- <xs:minLength value="1"/>
- <xs:maxLength value="60"/>
- <!-- FESA Fields have max. 60 characters. Since For each Register a field is generated, we have to use this limit -->
- <xs:pattern value="[_A-Za-z]+[_A-Za-z0-9]*"/>
- </xs:restriction>
- </xs:simpleType>
- <xs:simpleType name="FormatType">
- <xs:restriction base="xs:string">
- <xs:enumeration value="uint8"/>
- <xs:enumeration value="int8"/>
- <xs:enumeration value="uint16"/>
- <xs:enumeration value="int16"/>
- <xs:enumeration value="uint32"/>
- <xs:enumeration value="int32"/>
- <xs:enumeration value="uint64"/>
- <xs:enumeration value="int64"/>
- <xs:enumeration value="float32"/>
- <xs:enumeration value="float64"/>
- <xs:enumeration value="string"/>
- <xs:enumeration value="date"/>
- <xs:enumeration value="char"/>
- <xs:enumeration value="byte"/>
- <xs:enumeration value="word"/>
- <xs:enumeration value="dword"/>
- <xs:enumeration value="int"/>
- <xs:enumeration value="dint"/>
- <xs:enumeration value="real"/>
- <xs:enumeration value="dt"/>
- </xs:restriction>
- </xs:simpleType>
+<xs:simpleType name="BlockNameType">
+ <xs:restriction base="xs:string">
+ <xs:minLength value="1"/>
+ <xs:maxLength value="30"/>
+ <!-- Siemens Support bezüglich der maximalen Zeichenlänge für PLC- Tags : S7-300/1200/1500er bei 128 Zeichen -->
+ <!-- FESA PropertyNames have max. 30 characters. Since For each Block a prop is generated, we have to use this limit -->
+ <xs:pattern value="[_A-Za-z]+[_A-Za-z0-9]*"/>
+ </xs:restriction>
+</xs:simpleType>
+<xs:simpleType name="RegisterNameType">
+ <xs:restriction base="xs:string">
+ <xs:minLength value="1"/>
+ <xs:maxLength value="60"/>
+ <!-- FESA Fields have max. 60 characters. Since For each Register a field is generated, we have to use this limit -->
+ <xs:pattern value="[_A-Za-z]+[_A-Za-z0-9]*"/>
+ </xs:restriction>
+</xs:simpleType>
+<xs:simpleType name="FormatType">
+ <xs:restriction base="xs:string">
+ <xs:enumeration value="uint8"/>
+ <xs:enumeration value="int8"/>
+ <xs:enumeration value="uint16"/>
+ <xs:enumeration value="int16"/>
+ <xs:enumeration value="uint32"/>
+ <xs:enumeration value="int32"/>
+ <xs:enumeration value="uint64"/>
+ <xs:enumeration value="int64"/>
+ <xs:enumeration value="float32"/>
+ <xs:enumeration value="float64"/>
+ <xs:enumeration value="date"/>
+ <xs:enumeration value="char"/>
+ <xs:enumeration value="byte"/>
+ <xs:enumeration value="word"/>
+ <xs:enumeration value="dword"/>
+ <xs:enumeration value="int"/>
+ <xs:enumeration value="dint"/>
+ <xs:enumeration value="real"/>
+ <xs:enumeration value="dt"/>
+ </xs:restriction>
+</xs:simpleType>
+
+<xs:simpleType name="DimensionType">
+ <xs:restriction base="xs:unsignedInt">
+ <xs:minInclusive value="1"/>
+ </xs:restriction>
+</xs:simpleType>
+<xs:simpleType name="LengthType">
+ <xs:restriction base="xs:unsignedInt">
+ <xs:minInclusive value="2"/>
+ <xs:maxInclusive value="254"/>
+ </xs:restriction>
+</xs:simpleType>
- <xs:simpleType name="DimensionType">
- <xs:restriction base="xs:unsignedInt">
- <xs:minInclusive value="1"/>
- </xs:restriction>
- </xs:simpleType>
- <xs:simpleType name="LengthType">
- <xs:restriction base="xs:unsignedInt">
- <xs:minInclusive value="2"/>
- <xs:maxInclusive value="254"/>
- </xs:restriction>
- </xs:simpleType>
</xs:schema>
diff --git a/snap7/build.sh b/snap7/build.sh
index fe8ea20e0c24e1023b68271004fb78f6a503c7e9..4fb7c066d1f03df3d78b2a45f3279c07876cb7ce 100755
--- a/snap7/build.sh
+++ b/snap7/build.sh
@@ -4,9 +4,13 @@ set -e
SNAP7_VERSION=1.4.0
SNAP7_FOLDER=snap7-full-${SNAP7_VERSION}
-rm -rf snap7-full*
-wget http://downloads.sourceforge.net/project/snap7/${SNAP7_VERSION}/${SNAP7_FOLDER}.tar.gz
-tar -vxzf ${SNAP7_FOLDER}.tar.gz
-mv ${SNAP7_FOLDER} snap7-full
+archiveFile=${SNAP7_FOLDER}.tar.gz
+if [ ! -f "$archiveFile" ]
+then
+ rm -rf snap7-full*
+ wget http://downloads.sourceforge.net/project/snap7/${SNAP7_VERSION}/${archiveFile}
+ tar -vxzf ${archiveFile}
+ mv ${SNAP7_FOLDER} snap7-full
+fi
cd snap7-full/build/unix
make -f x86_64_linux.mk