silecs-codegen/src/xml/genduwrapper.py

@@ -43,13 +43,13 @@ def genClassHeader(workspacePath, deploy, design, funcGetSilecsDesignFilePath, f
         classDeclarations += genduwrappertemplate.getBlockClass(block,registerInitializerList,registerGetterSetter,registersDimentionsDeclaration,registersDeclaration)
     
     blockGetters = ""
-    sendRecvBlocks = genduwrappertemplate.getDeviceSendRecvBlocks(designClass.getBlockNodes())
+    sendRecvBlocks = genduwrappertemplate.getDeviceSendRecvBlocks(designClass.getBlockNodes(), designClass.customTypesXmlNode)
     for block in designClass.getDesignBlocks():
         blockGetters += genduwrappertemplate.getDeviceBlockGetterSetter(block)
 
     classDeclarations += genduwrappertemplate.getDeviceClass(blockGetters,sendRecvBlocks)
 
-    sendRecvBlocks = genduwrappertemplate.getControllerSendRecvBlocks(designClass.getBlockNodes())
+    sendRecvBlocks = genduwrappertemplate.getControllerSendRecvBlocks(designClass.getBlockNodes(), designClass.customTypesXmlNode)
     classDeclarations = genduwrappertemplate.getDesignClass(design.name, design.version)
     designWrapper = genduwrappertemplate.designFileTemplate.substitute({'designNameCapitalized' :  iecommon.capitalizeString(design.name),'designNameUpper' :  design.name.upper(),'classDeclarations' : classDeclarations})
 

silecs-codegen/src/xml/genduwrappertemplate.py

@@ -337,10 +337,10 @@ controllerSendTemplate = string.Template("""\
     
 """)
 
-def getControllerSendRecvBlocks(blockList):
+def getControllerSendRecvBlocks(blockList, customTypesXmlNode):
     text = ""
     for blockNode in blockList:
-        block = DesignBlock(blockNode)
+        block = DesignBlock(blockNode, customTypesXmlNode)
         map = {'blockName' : block.name,
                'blockNameCapitalized' : block.getNameCapitalized()}
         if block.isReadable():
@@ -405,39 +405,39 @@ ${blockInitialization}\
 matrixRegisterAssignementGetter = string.Template("""\
         // Copy register ${regName}
         ${cType} *__${regName} = new ${cType}[block.${regName}Dim1 * block.${regName}Dim2];
-        getSilecsDevice()->getRegister("${regName}")->getVal${silecsTypeCapitalized}Array2D(__${regName}, block.${regName}Dim1, block.${regName}Dim2);
+        getSilecsDevice()->getRegister("${regName}")->getValArray2D<${cType}>(__${regName}, block.${regName}Dim1, block.${regName}Dim2);
         block.set${regNameCapitalized}(__${regName});
         delete[] __${regName};
 """)
 arrayRegisterAssignementGetter = string.Template("""\
         // Copy register ${regName}
         ${cType} *__${regName} = new ${cType}[block.${regName}Dim1];
-        getSilecsDevice()->getRegister("${regName}")->getVal${silecsTypeCapitalized}Array(__${regName}, block.${regName}Dim1);
+        getSilecsDevice()->getRegister("${regName}")->getValArray<${cType}>(__${regName}, block.${regName}Dim1);
         block.set${regNameCapitalized}(__${regName});
         delete[] __${regName};
 """)
 scalarRegisterAssignementGetter = string.Template("""\
         // Copy register ${regName}
-        block.set${regNameCapitalized}(getSilecsDevice()->getRegister("${regName}")->getVal${silecsTypeCapitalized}());
+        block.set${regNameCapitalized}(getSilecsDevice()->getRegister("${regName}")->getVal<${cType}>());
 """)
 
 matrixRegisterAssignementSetter = string.Template("""\
         // Copy register ${regName}
         ${cType} *__${regName} = new ${cType}[block.${regName}Dim1 * block.${regName}Dim2];
         block.get${regNameCapitalized}(__${regName});
-        getSilecsDevice()->getRegister("${regName}")->setVal${silecsTypeCapitalized}Array2D(__${regName}, block.${regName}Dim1, block.${regName}Dim2);
+        getSilecsDevice()->getRegister("${regName}")->setValArray2D<${cType}>(__${regName}, block.${regName}Dim1, block.${regName}Dim2);
         delete[] __${regName};
 """)
 arrayRegisterAssignementSetter = string.Template("""\
         // Copy register ${regName}
         ${cType} *__${regName} = new ${cType}[block.${regName}Dim1];
         block.get${regNameCapitalized}(__${regName});
-        getSilecsDevice()->getRegister("${regName}")->setVal${silecsTypeCapitalized}Array(__${regName}, block.${regName}Dim1);
+        getSilecsDevice()->getRegister("${regName}")->setValArray<${cType}>(__${regName}, block.${regName}Dim1);
         delete[] __${regName};
 """)
 scalarRegisterAssignementSetter = string.Template("""\
         // Copy register ${regName}
-        getSilecsDevice()->getRegister("${regName}")->setVal${silecsTypeCapitalized}(block.get${regNameCapitalized}());
+        getSilecsDevice()->getRegister("${regName}")->setVal<${cType}>(block.get${regNameCapitalized}());
 """)
 
 def getDeviceBlockGetterSetter(block):
@@ -447,7 +447,6 @@ def getDeviceBlockGetterSetter(block):
         for register in block.getDesignRegisters():
             map = {'regName' : register.name,
                    'regNameCapitalized' : register.getNameCapitalized(),
-                   'silecsTypeCapitalized' : register.getSilecsTypeCapitalized(),
                    'cType' : register.getCType()}
             if register.isArray2D():
                 blockInitialization += matrixRegisterAssignementGetter.substitute(map)
@@ -465,7 +464,6 @@ def getDeviceBlockGetterSetter(block):
         for register in block.getDesignRegisters():
             map = {'regName' : register.name,
                    'regNameCapitalized' : register.getNameCapitalized(),
-                   'silecsTypeCapitalized' : register.getSilecsTypeCapitalized(),
                    'cType' : register.getCType()}
             if register.isArray2D():
                 blockInitialization += matrixRegisterAssignementSetter.substitute(map)
@@ -502,10 +500,10 @@ deviceSendTemplate = string.Template("""\
     
 """)
 
-def getDeviceSendRecvBlocks(blockList):
+def getDeviceSendRecvBlocks(blockList, customTypesXmlNode):
     text = ""
     for blockNode in blockList:
-        block = DesignBlock(blockNode)
+        block = DesignBlock(blockNode, customTypesXmlNode)
         map = {'blockName' : block.name,
                'blockNameCapitalized' : block.getNameCapitalized()}
         if block.isReadable():

silecs-codegen/src/xml/iecommon.py

@@ -20,7 +20,6 @@ import os
 import sys
 import getpass
 import codecs
-import commands
 
 import iecommon
 import libxml2
@@ -38,7 +37,7 @@ def logError(msg, exit,logTopics={}):
     if 'errorlog' in logTopics:
         if logTopics['errorlog'] == True:
             _logMsg = "%s%s" %(logHeader("ERROR"), msg)
-            print _logMsg
+            print(_logMsg)
             if exit:
                 raise Exception(_logMsg)
 
@@ -46,13 +45,13 @@ def logInfo(msg,logTopics={}):
     if 'infolog' in logTopics:
         if logTopics['infolog'] == True:
             _logMsg = "%s%s" %(logHeader("INFO"), msg)
-            print _logMsg
+            print(_logMsg)
     
 def logDebug(msg,logTopics={}):   
     if 'debuglog' in logTopics:
         if logTopics['debuglog'] == True:
             _logMsg = "%s%s" %(logHeader("DEBUG"), msg)
-            print _logMsg
+            print(_logMsg)
             
 # Append message to a text file
 def logToFile(path,msg):
@@ -143,7 +142,7 @@ def getOrCreateNamedFirstChild(parent,elementName, attributeNameValue):
     return newNode
 
 def fillAttributes(element, attrs):
-    for name,value in attrs.iteritems():
+    for name,value in attrs.items():
         if not type(value) is str:
             raise Exception("Error: Wrong Type Parsed for attribute: " + name)
         element.setProp(name, value)
@@ -173,4 +172,9 @@ def getPatchSilecsVersion(silecsVersionString):
     secondDot = silecsVersionString.find('.',firstDot)
     return silecsVersionString[secondDot:]
 
-
+def supportsDateTimeLong(controller):
+    if controller.brand != "SIEMENS":
+        return False
+    if controller.model in ['SIMATIC_S7-300', 'SIMATIC_S7-400']:
+        return False
+    return True

silecs-codegen/src/xml/iefiles.py

@@ -26,9 +26,9 @@ designFormat    = '.silecsdesign'
 deployFormat    = '.silecsdeploy'
 paramFormat     = '.silecsparam'
 
-def loadSilecsDesignDOM(workspacePath, silecsDesign, silecsVersion, funcGetSilecsDesignFilePath):
+def loadSilecsDesignDOM(workspacePath, silecsDesign, silecsVersion, funcGetSilecsDesignFilePath, datetime_format=xmltemplate.DATE_AND_TIME):
     if silecsDesign.name == "SilecsHeader":
-        silecsHeader = xmltemplate.getSilecsHeader(silecsVersion)
+        silecsHeader = xmltemplate.getSilecsHeader(silecsVersion, datetime_format)
         return libxml2.parseDoc(silecsHeader)
     else:
         designPath = funcGetSilecsDesignFilePath(workspacePath, silecsDesign.name)

silecs-codegen/src/xml/migration/0_10_xto1_0_x.py

@@ -16,6 +16,7 @@
 
 import os
 import sys
+import ParseMigrationArgs
 
 from migrationBase import MigrationBase
 from migration0_10_0to1_0_0.migrators import *
@@ -26,8 +27,8 @@ import FileUtils
 import shutil
 
 class Migration(MigrationBase):
-    def __init__(self, arguments):
-        super(Migration, self).__init__()
+    def __init__(self, silecsDocument, xmlSchema, versionOld, versionNew, createBackup):
+        super(Migration, self).__init__(silecsDocument, xmlSchema, versionOld, versionNew, createBackup)
 
     def migrateClass(self, context, projectDir ):
         modified = designGenerateFesaPropValueItemMigrator(context)
@@ -42,9 +43,7 @@ class Migration(MigrationBase):
         return modified
 
     def migrateFESAInstanceFile(self):
-        results = self.parser.parse_args()
-        silecsDocument = results.silecsDocument
-        projectDir = FileUtils.getProjectDir(silecsDocument)
+        projectDir = FileUtils.getProjectDir(self.silecsDocument)
         testFolder = projectDir + "/src/test"
         if not os.path.isdir(testFolder):
             return
@@ -60,7 +59,18 @@ class Migration(MigrationBase):
                         if fesaInstanceFileMigrator(context):
                             self._saveAndBackupFile(context,instanceFile)
 
-if __name__ == "__main__":
-    migration = Migration(sys.argv)
+def main_parse():
+    arguments = ParseMigrationArgs.parse_arguments()
+    run_migrate(arguments.silecsDocument,
+                arguments.xmlSchema,
+                arguments.versionOld, 
+                arguments.versionNew,
+                arguments.createBackup)
+
+def run_migrate(silecsDocument, xmlSchema, versionOld, versionNew, createBackup):
+    migration = Migration(silecsDocument, xmlSchema, versionOld, versionNew, createBackup)
     migration.migrate()
     migration.backupOldFESAMakeSpecific()
+
+if __name__ == "__main__":
+    main_parse()

silecs-codegen/src/xml/migration/0_9_xto0_10_x.py

@@ -16,6 +16,7 @@
 
 import os
 import sys
+import ParseMigrationArgs
 
 from migrationBase import MigrationBase
 from migration_0_9_0to0_10_0.migrateDeployDeviceNumber import DeployDeviceNumberMigrator
@@ -25,8 +26,8 @@ import libxml2
 import sys
 
 class Migration(MigrationBase):
-    def __init__(self, arguments):
-        super(Migration, self).__init__()
+    def __init__(self, silecsDocument, xmlSchema, versionOld, versionNew, createBackup):
+        super(Migration, self).__init__(silecsDocument, xmlSchema, versionOld, versionNew, createBackup)
         self._deployDomainMigrator = DeployDomainMigrator()
         self._migrateDeployDeviceNumber = DeployDeviceNumberMigrator()
 
@@ -39,6 +40,17 @@ class Migration(MigrationBase):
         modified = self._migrateDeployDeviceNumber.migrate(context)
         return modified
 
-if __name__ == "__main__":
-    migration = Migration(sys.argv)
+def main_parse():
+    arguments = ParseMigrationArgs.parse_arguments()
+    run_migrate(arguments.silecsDocument,
+                arguments.xmlSchema,
+                arguments.versionOld, 
+                arguments.versionNew,
+                arguments.createBackup)
+
+def run_migrate(silecsDocument, xmlSchema, versionOld, versionNew, createBackup):
+    migration = Migration(silecsDocument, xmlSchema, versionOld, versionNew, createBackup)
     migration.migrate()
+
+if __name__ == "__main__":
+    main_parse()

silecs-codegen/src/xml/migration/1_0_xto2_0_x.py

@@ -16,6 +16,7 @@
 
 import os
 import sys
+import ParseMigrationArgs
 
 from migrationBase import MigrationBase
 from migration1_0_Xto2_0_0.migrators import *
@@ -26,16 +27,26 @@ import FileUtils
 import shutil
 
 class Migration(MigrationBase):
-    def __init__(self, arguments):
-        super(Migration, self).__init__()
+    def __init__(self, silecsDocument, xmlSchema, versionOld, versionNew, createBackup):
+        super(Migration, self).__init__(silecsDocument, xmlSchema, versionOld, versionNew, createBackup)
 
-    def migrateClass(self, context, projectDir ):
+    def migrateClass(self, context, projectDir):
         modified = designValueTypeMigrator(context)
         modified |= designBlockRegisterMigrator(context)
         return modified
 
+def main_parse():
+    arguments = ParseMigrationArgs.parse_arguments()
+    run_migrate(arguments.silecsDocument,
+                arguments.xmlSchema,
+                arguments.versionOld, 
+                arguments.versionNew,
+                arguments.createBackup)
 
-if __name__ == "__main__":
-    migration = Migration(sys.argv)
+def run_migrate(silecsDocument, xmlSchema, versionOld, versionNew, createBackup):
+    migration = Migration(silecsDocument, xmlSchema, versionOld, versionNew, createBackup)
     migration.migrate()
     migration.backupOldFESAMakeSpecific()
+
+if __name__ == "__main__":
+    main_parse()

silecs-codegen/src/xml/migration/FileUtils.py

@@ -50,13 +50,6 @@ def getFesaSourceFiles(fesaClassName, projectDir):
     for root, subdirs, files in os.walk(fesaCodeFolder):
         for file in files:
             if file.endswith(".cpp") or file.endswith(".h"):
-                print os.path.join(root,file)
+                print(os.path.join(root,file))
                 sourceFiles.append(os.path.join(root,file))
     return sourceFiles
-
-def replaceInFile(filePath,searchString,replaceWithString):
-    with open(filePath, 'r') as file :
-      filedata = file.read()
-    filedata = filedata.replace(searchString, replaceWithString)
-    with open(filePath, 'w') as file:
-      file.write(filedata)
\ No newline at end of file