Commit 10e0cb67 authored by v.svintozelskyi's avatar v.svintozelskyi
Browse files

First commit

parents
{
"cells": [],
"metadata": {},
"nbformat": 4,
"nbformat_minor": 5
}
%% Cell type:code id:pleased-marina tags:
``` python
import sys
sys.path.insert(0, '../')
import pasttrec_ctrl as pt
import pasttrec_conf as pc
```
%% Cell type:code id:direct-humor tags:
``` python
# pt.found_baselines_for_boards(["0x1814", "0x1815", "0x1800"],plot=False)
```
%% Cell type:code id:coated-moral tags:
``` python
# mdc_tree = pc.getConnectedMDCtree()
# conf = pc.generateDefaultConfiguration(mdc_tree)
# conf = {"0x8001": conf["0x8001"], "0x8009": conf["0x8009"] }
# # print(*conf.values(), sep="\n")
# pc.found_all_baselines(conf)
# print(*conf.values(),sep="\n")
```
%% Cell type:code id:suited-plant tags:
``` python
pt.readMemory("0x1814")
```
This diff is collapsed.
This diff is collapsed.
%% Cell type:code id:proof-inside tags:
``` python
import sys
sys.path.insert(0, '../')
import pasttrec_ctrl as pt
import pasttrec_conf as pc
```
%% Cell type:code id:olive-clinton tags:
``` python
# pt.found_baselines_for_boards(["0x1814", "0x1815", "0x1800"],plot=False)
```
%% Cell type:code id:certified-tower tags:
``` python
# mdc_tree = pc.getConnectedMDCtree()
# conf = pc.generateDefaultConfiguration(mdc_tree)
# conf = {"0x8001": conf["0x8001"], "0x8009": conf["0x8009"] }
# # print(*conf.values(), sep="\n")
# pc.found_all_baselines(conf)
# print(*conf.values(),sep="\n")
```
%% Cell type:code id:psychological-jenny tags:
``` python
pt.printMemory("0x1814")
```
%% Cell type:code id:entitled-nursery tags:
``` python
```
This diff is collapsed.
#!/usr/bin/perl -w
use strict;
use warnings;
use POSIX;
use File::Basename;
# use Data::Dumper;
use Getopt::Long;
my $help=0;
my $verbose=0;
my $yestoall=0;
my $clear=0;
my $info=0;
my $noverify=0;
Getopt::Long::Configure(qw(gnu_getopt));
GetOptions(
'help|h' => \$help,
# 'verbose|v' => \$verbose,
'y' => \$yestoall,
'clear|c' => \$clear,
'info|i' => \$info,
'noverify|v' => \$noverify,
);
my @pages;
my $page;
# my $header_page_addr = 0x7000;
my $header_page_addr = 0x3000; # mdc upgrade
my $trbflash = "/workdir/newtrbnettools/trbnettools/bin/trbflash";
my $FPGA = $ARGV[0];
my $settings_file = (defined($ARGV[1])) ? $ARGV[1] : "/dev/null";
if ($help or not(defined($FPGA)) ) {
help();
}
if ($info) {
# my $infostring ="";
# my $raw_page = qx"$trbflash dumppage $FPGA $header_page_addr";
# for my $line (split("\n",$raw_page)) {
# if ($line =~ m/^0x\S\S (\S\S ){16} ((\S){16})/){
# $infostring.=$2;
# }
# }
my $infostring = get_page($FPGA,$header_page_addr);
unless ( substr($infostring,0,8) eq "SLOWCTRL" ) {
print "found no default slow control settings in FPGA $FPGA\n";
exit;
}
my $filename = substr($infostring,32,32);
my $flash_date = substr($infostring,96,32);
my $setfile_moddate = substr($infostring,64,32);
my $no_pages = unpack("l",reverse(split("",substr($infostring,12,4))));
my $no_registers = unpack("l",reverse(split("",substr($infostring,8,4))));
$filename =~ s/\.+$//;
$flash_date =~ s/\.+$//;
$setfile_moddate =~ s/\.+$//;
print "found default slow control settings in FPGA $FPGA\n";
print " from settings file $filename\n";
print " last modified at $setfile_moddate\n";
print " flashed at $flash_date\n";
print " number of pages $no_pages\n";
print " number of registers $no_registers\n";
exit;
}
my $epoch_timestamp = (stat($settings_file))[9];
my $settings_file_mod_date = strftime("%Y-%m-%d_%H:%M:%S\n",localtime($epoch_timestamp)); # modification date
my $flash_timestamp = strftime("%Y-%m-%d_%H:%M:%S\n",localtime()); # now
my $registers_per_page = 42;
my $sc_data = {};
if (defined($settings_file) and not($settings_file eq "/dev/null") ) {
# load settings from settings file
open(FH,$settings_file) or die "could not open settings file $settings_file\n";
my @lines = <FH>;
close(FH);
for my $line (@lines) {
next unless $line =~ m/(^[xXa-fA-F0-9]+)\s+([xXa-fA-F0-9]+)/;
$sc_data->{eval($1)} = eval($2); # convert hex/binary/decimal strings to numbers
}
} elsif ($clear) {
print "clearing the settings in FPGA $FPGA\n";
} else {
help();
}
# write slow control data to pages
my $registers_to_read = 0;
my $register_counter_on_page = 0;
$page = chr(0) x 256; # initialize empty page;
my @addresses = sort { $a <=> $b } keys %{$sc_data};
for my $addr (@addresses) {
insert_at(\$page,6*$register_counter_on_page, my_uint($addr, 2) );
insert_at(\$page,6*$register_counter_on_page+2, my_uint($sc_data->{$addr}, 4) );
$registers_to_read++;
$register_counter_on_page = ($registers_to_read)%($registers_per_page);
if ( ($register_counter_on_page == 0) or ($registers_to_read == scalar(@addresses)) ) {
push(@pages,$page);
$page = chr(0) x 256; # initialize empty page;
}
}
# compose header page
$page = chr(0) x 256; # initialize empty page;
my $pages_to_read = ceil($registers_to_read/42);
unless($clear) {
insert_at(\$page,0, "SLOWCTRL" );
insert_at(\$page,8, my_uint($registers_to_read, 4) );
insert_at(\$page,12, my_uint($pages_to_read, 4) );
insert_at(\$page,32,(fileparse($settings_file))[0]); # filename only
insert_at(\$page,64,$settings_file_mod_date); # modification date timestamp
insert_at(\$page,96,$flash_timestamp); # flash timestamp
}
unshift(@pages,substr($page,0,256)); # push current page to the pages array,
my $trbflash_options = "";
$trbflash_options.= " -y " if $yestoall;
my $temp_file = qx%mktemp%;
open(FILE,"> $temp_file") or die "could not open temporary file $temp_file for writing!\n";
binmode(FILE);
print FILE join("",@pages);
close(FILE);
system("$trbflash $trbflash_options flash_at_page $FPGA $header_page_addr $temp_file");
system("rm $temp_file");
unless ($noverify) {
#read header page
# my $raw_page = qx"$trbflash dumppage $FPGA $header_page_addr";
my $header_page = get_page($FPGA, $header_page_addr);
my $no_pages = unpack("l",reverse(split("",substr($header_page,12,4))));
# print "number of pages : $no_pages\n";
my $mismatch = 0;
if ($no_pages == $pages_to_read) {
for (my $i = 0; $i le $no_pages; $i++) {
my $cur_page;
if($i == 0) {
$cur_page = $header_page;
} else {
$cur_page = get_page($FPGA,$header_page_addr+$i);
}
if ($cur_page eq $pages[$i]) {
print "page $i/$no_pages verified\n";
} else {
print "page $i/$no_pages mismatch!\n";
$mismatch++;
}
}
} else {
print "number of pages mismatch!";
$mismatch++;
}
die "Memory verification failed! To ensure a safe FPGA behaviour, try again, or at least issue\n".
"flash_settings.pl $FPGA --clear\nto clear the corrupted default settings\n" if $mismatch;
}
# system("xxd $temp_file");
# print "$temp_file\n";
sub get_page {
my $FPGA = shift;
my $page = shift;
my $raw_page = qx"$trbflash dumppage $FPGA $page 2>&1";
my $data;
for my $line (split("\n",$raw_page)) {
if ($line =~ m/^0x\S\S ((\S\S ){16}) ((.){16})/){
my $hex_nibbles = $1;
$hex_nibbles =~ s/\s//g;
$data .= pack("H*",$hex_nibbles);
# print "$line \n LEN:";
# print length $line;
# print "\n";
}
}
return $data if (length($data) == 256);
die "could not read page $page from flash with $trbflash dumppage $FPGA $page";
}
sub insert_at {
my $pageRef = shift;
my $pos = shift;
my $string = shift;
substr($$pageRef,$pos,length($string)) = $string;
}
sub my_uint {
my $number = floor(shift);
my $bytes = shift;
my @out = ();
for my $i (1..$bytes) {
push(@out,chr($number & 0xFF));
$number = floor($number/256);
}
return join("",reverse @out);
}
sub help {
print <<EOF;
usage:
flash_settings.pl [options] <FPGA addr> [settings file]
options:
--help|-h show help message
-y pass "yes to all" option to trbflash
--clear|-c clear settings in given FPGA
--noverify|-v do not verify the written memory area
--info|-i show information summary about settings
in the flash
settings file format:
<sc addr> <value>
<sc addr> <value>
<sc addr> <value>
...
2015 by Michael Wiebusch (m.wiebusch\@gsi.de)
EOF
exit;
}
OEP | | FPGA1 | FPGA2 | FPGA3
0x8012 | -- | 0x1820 | 0x1821 |
| CH | PT1 PT2 PT3 PT4 | PT1 PT2 PT3 PT4 | PT1 PT2 PT3 PT4
| GA | 1.00 1.00 4.00 4.00 | 4.00 4.00 4.00 4.00 |
| TH | 0x7F 0x00 0x08 0x00 | 0x00 0x00 0x00 0x00 |
| PT | 0010 0015 0010 0010 | 0010 0010 0010 0010 |
| B0 | 0x15 0x1F 0x16 0x10 | 0x0F 0x0F 0x0F 0x0F |
| B1 | 0x17 0x17 0x11 0x16 | 0x0F 0x0F 0x0F 0x0F |
| B2 | 0x0E 0x13 0x11 0x18 | 0x0F 0x0F 0x0F 0x0F |
| B3 | 0x17 0x16 0x15 0x10 | 0x0F 0x0F 0x0F 0x0F |
| B4 | 0x16 0x16 0x15 0x11 | 0x0F 0x0F 0x0F 0x0F |
| B5 | 0x1A 0x16 0x13 0x16 | 0x0F 0x0F 0x0F 0x0F |
| B6 | 0x11 0x18 0x1B 0x12 | 0x0F 0x0F 0x0F 0x0F |
| B7 | 0x1A 0x1A 0x14 0x12 | 0x0F 0x0F 0x0F 0x0F |
OEP | | FPGA1 | FPGA2 | FPGA3
0x8001 | -- | 0x1800 |
| CH | PT1 PT2 PT3 PT4 | PT1 PT2 PT3 PT4 | PT1 PT2 PT3 PT4
| GA | 4.00 4.00 4.00 4.00 |
| TH | 0x08 0x08 0x08 0x08 |
| PT | 0010 0010 0010 0010 |
| B0 | 0x0F 0x0F 0x0F 0x0F |
| B1 | 0x0F 0x0F 0x0F 0x0F |
| B2 | 0x0F 0x0F 0x0F 0x0F |
| B3 | 0x0F 0x0F 0x0F 0x0F |
| B4 | 0x0F 0x0F 0x0F 0x0F |
| B5 | 0x0F 0x0F 0x0F 0x0F |
| B6 | 0x0F 0x0F 0x0F 0x0F |
| B7 | 0x0F 0x0F 0x0F 0x0F |
OEP | | FPGA1 | FPGA2 | FPGA3
0x8011 | -- | 0x1818 | 0x1819 |
| CH | PT1 PT2 PT3 PT4 | PT1 PT2 PT3 PT4 | PT1 PT2 PT3 PT4
| GA | 4.00 4.00 4.00 4.00 | 4.00 4.00 4.00 4.00 |
| TH | 0x08 0x08 0x08 0x08 | 0x08 0x08 0x08 0x08 |
| PT | 0010 0010 0010 0010 | 0010 0010 0010 0010 |
| B0 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B1 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B2 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B3 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B4 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B5 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B6 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B7 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
OEP | | FPGA1 | FPGA2 | FPGA3
0x8008 | -- | 0x1812 | 0x1813 |
| CH | PT1 PT2 PT3 PT4 | PT1 PT2 PT3 PT4 | PT1 PT2 PT3 PT4
| GA | 4.00 4.00 4.00 4.00 | 4.00 4.00 4.00 4.00 |
| TH | 0x08 0x08 0x08 0x08 | 0x08 0x08 0x08 0x08 |
| PT | 0010 0010 0010 0010 | 0010 0010 0010 0010 |
| B0 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B1 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B2 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B3 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B4 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B5 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B6 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B7 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
OEP | | FPGA1 | FPGA2 | FPGA3
0x8010 | -- | 0x1816 | 0x1817 |
| CH | PT1 PT2 PT3 PT4 | PT1 PT2 PT3 PT4 | PT1 PT2 PT3 PT4
| GA | 4.00 4.00 4.00 4.00 | 4.00 4.00 4.00 4.00 |
| TH | 0x08 0x08 0x08 0x08 | 0x08 0x08 0x08 0x08 |
| PT | 0010 0010 0010 0010 | 0010 0010 0010 0010 |
| B0 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B1 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B2 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B3 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B4 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B5 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B6 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B7 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
OEP | | FPGA1 | FPGA2 | FPGA3
0x8002 | -- | 0x1802 | 0x1803 |
| CH | PT1 PT2 PT3 PT4 | PT1 PT2 PT3 PT4 | PT1 PT2 PT3 PT4
| GA | 4.00 4.00 4.00 4.00 | 4.00 4.00 4.00 4.00 |
| TH | 0x08 0x08 0x08 0x08 | 0x08 0x08 0x08 0x08 |
| PT | 0010 0010 0010 0010 | 0010 0010 0010 0010 |
| B0 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B1 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B2 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B3 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B4 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B5 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B6 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
| B7 | 0x0F 0x0F 0x0F 0x0F | 0x0F 0x0F 0x0F 0x0F |
0xA0C0 0x00050018
0xA0C1 0x0005011E
0xA0C2 0x00050215
0xA0C3 0x0005037F
0xA0C4 0x0005040F
0xA0C5 0x0005050F
0xA0C6 0x0005060F
0xA0C7 0x0005070F
0xA0C8 0x0005080F
0xA0C9 0x0005090F
0xA0CA 0x00050A0F
0xA0CB 0x00050B0F
0xA0D0 0x0005001A
0xA0D1 0x0005011E
0xA0D2 0x00050215
0xA0D3 0x0005037F
0xA0D4 0x0005040F
0xA0D5 0x0005050F
0xA0D6 0x0005060F
0xA0D7 0x0005070F
0xA0D8 0x0005080F
0xA0D9 0x0005090F
0xA0DA 0x00050A0F
0xA0DB 0x00050B0F
0xA0E0 0x00050019
0xA0E1 0x0005011E
0xA0E2 0x00050215
0xA0E3 0x0005037F
0xA0E4 0x0005040F
0xA0E5 0x0005050F
0xA0E6 0x0005060F
0xA0E7 0x0005070F
0xA0E8 0x0005080F
0xA0E9 0x0005090F
0xA0EA 0x00050A0F
0xA0EB 0x00050B0F
0xA0F0 0x00051000
0xA0F1 0x00051100
0xA0F2 0x00051200
0xA0F3 0x00051300
0xA0F4 0x00051400
0xA0F5 0x00051500
0xA0F6 0x00051600
0xA0F7 0x00051700
0xA0F8 0x00051800
0xA0F9 0x00051900
0xA0FA 0x00051A00
0xA0FB 0x00051B00
0xA0FC 0x00051C00
0xA0FD 0x00051D00
0xA0FE 0x00051E00
0xA0FF 0x00051F00
0xA010 0x00050010
0xA011 0x0005011E
0xA012 0x0005022A
0xA013 0x00050308
0xA014 0x00050D05
0xA015 0x0005040F
0xA016 0x0005050F
0xA017 0x0005060F
0xA018 0x0005070F
0xA019 0x0005080F
0xA01A 0x0005090F
0xA01B 0x00050A0F
0xA01C 0x00050B0F
0xA01E 0x00050010
0xA01F 0x0005011E
0xA020 0x0005022A
0xA021 0x00050308
0xA022 0x00050D05
0xA023 0x0005040F
0xA024 0x0005050F
0xA025 0x0005060F
0xA026 0x0005070F
0xA027 0x0005080F
0xA028 0x0005090F
0xA029 0x00050A0F
0xA02A 0x00050B0F
0xA02C 0x00050010
0xA02D 0x0005011E
0xA02E 0x0005022A
0xA02F 0x00050308
0xA030 0x00050D05
0xA031 0x0005040F
0xA032 0x0005050F
0xA033 0x0005060F
0xA034 0x0005070F
0xA035 0x0005080F
0xA036 0x0005090F
0xA037 0x00050A0F
0xA038 0x00050B0F
0xA03A 0x00050010
0xA03B 0x0005011E
0xA03C 0x0005022A
0xA03D 0x00050308
0xA03E 0x00050D05
0xA03F 0x0005040F
0xA040 0x0005050F
0xA041 0x0005060F
0xA042 0x0005070F
0xA043 0x0005080F
0xA044 0x0005090F
0xA045 0x00050A0F
0xA046 0x00050B0F
0xA002 0x4D1E4D10
0xA003 0x4D3A4D2C
0xAA00 0x00000000
0xA0C0 0x00050018
0xA0C1 0x0005011E
0xA0C2 0x00050215
0xA0C3 0x0005037F
0xA0C4 0x0005040F
0xA0C5 0x0005050F
0xA0C6 0x0005060F
0xA0C7 0x0005070F
0xA0C8 0x0005080F
0xA0C9 0x0005090F
0xA0CA 0x00050A0F
0xA0CB 0x00050B0F
0xA0D0 0x0005001A
0xA0D1 0x0005011E
0xA0D2 0x00050215
0xA0D3 0x0005037F
0xA0D4 0x0005040F
0xA0D5 0x0005050F
0xA0D6 0x0005060F
0xA0D7 0x0005070F
0xA0D8 0x0005080F
0xA0D9 0x0005090F
0xA0DA 0x00050A0F
0xA0DB 0x00050B0F
0xA0E0 0x00050019
0xA0E1 0x0005011E
0xA0E2 0x00050215
0xA0E3 0x0005037F
0xA0E4 0x0005040F
0xA0E5 0x0005050F
0xA0E6 0x0005060F
0xA0E7 0x0005070F
0xA0E8 0x0005080F
0xA0E9 0x0005090F
0xA0EA 0x00050A0F
0xA0EB 0x00050B0F
0xA0F0 0x00051000
0xA0F1 0x00051100