Skip to content
GitLab
Explore
Sign in
EE-LV
CSPP
TASCA
UTCS
Repository
UTCS
Packages
UTCS
BeamControl
FPGA Bitfiles
UTCS_PXI-7813R_Main.lvbitx
Find file
Blame
History
Permalink
Mirror FPGA Reset(HW or SW or First Call) to FPGA output.
· 9ebd2d4f
Holger Brand
authored
Apr 23, 2018
Recompile FPGA and UTCS.exe.
9ebd2d4f