SFRS_PEAKS1 specs

• 8x 50R SMA analog inputs
  • inputs are for negative polarity detector pulses
• 8x analog channels, each comrising
  • programmable attenuator, 0-31.5 dB
  • inverting amplifier (gain=10) + fast leading edge discriminator
  • amplitude to width converter
• 16x output channels to TDC (TAMEX4)
  • out0 -> ch0 fast out
  • out1 -> ch0 amplitude out
  • out2 -> ch1 fast out
  • out3 -> ch1 amplitude out
  • out4 -> ch2 fast out
  • out5 -> ch2 amplitude out
  • [...]

Control Registers

• SFRS_PEAKS1 control registers are programmed by means of a tiny service python script:

# write argument order:
./pqdc1_spi.py <SFP> <device> <SPI chan> <register> <sub register> w <value>

# read back a value:
./pqdc1_spi.py <SFP> <device> <SPI chan> <register> <sub register> r 0

# example: set the fast discriminator threshold of the third channel (ch02) to 32000
./pqdc1_spi.py 1 0 0 0x00 2 w 32000

# example: set attenuation of the fifth channel (ch04) to 6 dB (factor 1/2)
./pqdc1_spi.py 1 0 0 0x02 4 w 12

note: SPI chan is always 0. There is only one FPGA on SFRS_PEAKS1 to choose from.

• The fast discriminator sees the output of the inverting amplifier, i.e. a signal with positive polarity. Higher threshold numbers means further away from the baseline. A good starting value is thr_FAST = 30000.
• The amplitude to width circuit sees the detector signal directly, i.e. a signal with negative polarity. Lower threshold numbers means further away from the baseline.
  • If the amplitude to width circuit is not used, set thr_AMP to 65000.
  • If the amplitude to width circuit shall be used, a good starting point is thr_AMP = 35000.

Front connector mapping