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Commit e3651e8b authored by al.schwinn's avatar al.schwinn
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Bug 1407 - Remove Plugin specific design validation Rules

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silecs-codegen/src/xml/test/generated_correct/controller/Beckhoff_BC9020.exp
+ 2
− 2
View file @ e3651e8b
......@@ -11,13 +11,13 @@ VAR_GLOBAL
_version_a781_SilecsHeader AT %MW0: STRING(16):= DEV;
(*SilecsHeader/SilecsHeader/hdrBlk *)
_checksum_a781_SilecsHeader AT %MW9: DWORD:= 2843029646;
_checksum_a781_SilecsHeader AT %MW9: DWORD:= 3184721915;
(*SilecsHeader/SilecsHeader/hdrBlk *)
_user_a781_SilecsHeader AT %MW11: STRING(16):= 'schwinn';
(*SilecsHeader/SilecsHeader/hdrBlk *)
_date_a781_SilecsHeader AT %MW20: DT:= DT#2016-7-14-16:7:52;
_date_a781_SilecsHeader AT %MW20: DT:= DT#2017-6-6-16:14:51;
(*AllTypes/testDevice1/MyROBlock *)
RO_int8_a583_testDevice1 AT %MW24: SINT;
......
silecs-codegen/src/xml/test/generated_correct/controller/Beckhoff_CX9020.exp
+ 2
− 2
View file @ e3651e8b
......@@ -11,13 +11,13 @@ VAR_GLOBAL
_version_a781_SilecsHeader AT %MW0: STRING(16):= DEV;
(*SilecsHeader/SilecsHeader/hdrBlk *)
_checksum_a781_SilecsHeader AT %MW20: DWORD:= 427563505;
_checksum_a781_SilecsHeader AT %MW20: DWORD:= 656547166;
(*SilecsHeader/SilecsHeader/hdrBlk *)
_user_a781_SilecsHeader AT %MW24: STRING(16):= 'schwinn';
(*SilecsHeader/SilecsHeader/hdrBlk *)
_date_a781_SilecsHeader AT %MW44: DT:= DT#2016-7-14-16:8:13;
_date_a781_SilecsHeader AT %MW44: DT:= DT#2017-6-6-16:14:51;
(*AllTypes/testDevice1/MyROBlock *)
RO_int8_a583_testDevice1 AT %MW52: SINT;
......
silecs-codegen/src/xml/test/generated_correct/controller/Rabbit_BlockMode.h
+ 2
− 2
View file @ e3651e8b
......@@ -183,13 +183,13 @@ int SILECS_init()
strcpy((unsigned char *)silecsData.data.SilecsHeader_hdrBlk.device[0]._version, "SILECS_DEV");
/* Silecs checksum initialization */
silecsData.data.SilecsHeader_hdrBlk.device[0]._checksum = 3940683809;
silecsData.data.SilecsHeader_hdrBlk.device[0]._checksum = 1525793519;
/* Silecs user initialization */
strcpy((unsigned char *)silecsData.data.SilecsHeader_hdrBlk.device[0]._user, "schwinn");
/* Silecs date initialization */
SILECS_set_dt(3,48,8,16,14,7,2016,&silecsData.data.SilecsHeader_hdrBlk.device[0]._date);
SILECS_set_dt(1,51,14,16,6,6,2017,&silecsData.data.SilecsHeader_hdrBlk.device[0]._date);
}
/*
......
silecs-codegen/src/xml/test/generated_correct/controller/Rabbit_DeviceMode.h
+ 2
− 2
View file @ e3651e8b
......@@ -176,13 +176,13 @@ int SILECS_init()
strcpy((unsigned char *)silecsData.data.SilecsHeader_device[0].hdrBlk._version, "SILECS_DEV");
/* Silecs checksum initialization */
silecsData.data.SilecsHeader_device[0].hdrBlk._checksum = 3940683809;
silecsData.data.SilecsHeader_device[0].hdrBlk._checksum = 1525793519;
/* Silecs user initialization */
strcpy((unsigned char *)silecsData.data.SilecsHeader_device[0].hdrBlk._user, "schwinn");
/* Silecs date initialization */
SILECS_set_dt(3,0,9,16,14,7,2016,&silecsData.data.SilecsHeader_device[0].hdrBlk._date);
SILECS_set_dt(1,51,14,16,6,6,2017,&silecsData.data.SilecsHeader_device[0].hdrBlk._date);
}
/*
......
silecs-codegen/src/xml/test/generated_correct/controller/Schneider_M340.xsy
+ 2
− 2
View file @ e3651e8b
......@@ -5,7 +5,7 @@
<comment>SilecsHeader/SilecsHeader/hdrBlk</comment>
</variables>
<variables name="_checksum_a781_SilecsHeader" typeName="DWORD" topologicalAddress="%MW8">
<variableInit value="3940683809"/>
<variableInit value="1525793519"/>
<comment>SilecsHeader/SilecsHeader/hdrBlk</comment>
</variables>
<variables name="_user_a781_SilecsHeader" typeName="STRING[16]" topologicalAddress="%MW10">
......@@ -13,7 +13,7 @@
<comment>SilecsHeader/SilecsHeader/hdrBlk</comment>
</variables>
<variables name="_date_a781_SilecsHeader" typeName="DT" topologicalAddress="%MW18">
<variableInit value="DT#2016-7-14-16:8:24"/>
<variableInit value="DT#2017-6-6-16:14:51"/>
<comment>SilecsHeader/SilecsHeader/hdrBlk</comment>
</variables>
<variables name="RO_int8_a583_testDevice1" typeName="WORD" topologicalAddress="%MW22">
......
silecs-codegen/src/xml/test/generated_correct/controller/Schneider_PremiumQuantum.xsy
+ 2
− 2
View file @ e3651e8b
......@@ -5,7 +5,7 @@
<comment>SilecsHeader/SilecsHeader/hdrBlk</comment>
</variables>
<variables name="_checksum_a781_SilecsHeader" typeName="DWORD" topologicalAddress="%MW8">
<variableInit value="3940683809"/>
<variableInit value="1525793519"/>
<comment>SilecsHeader/SilecsHeader/hdrBlk</comment>
</variables>
<variables name="_user_a781_SilecsHeader" typeName="STRING[16]" topologicalAddress="%MW10">
......@@ -13,7 +13,7 @@
<comment>SilecsHeader/SilecsHeader/hdrBlk</comment>
</variables>
<variables name="_date_a781_SilecsHeader" typeName="DT" topologicalAddress="%MW18">
<variableInit value="DT#2016-7-14-16:8:40"/>
<variableInit value="DT#2017-6-6-16:14:51"/>
<comment>SilecsHeader/SilecsHeader/hdrBlk</comment>
</variables>
<variables name="RO_int8_a583_testDevice1" typeName="WORD" topologicalAddress="%MW22">
......
silecs-codegen/src/xml/test/generated_correct/controller/Siemens_Step7Block.scl
+ 2
− 2
View file @ e3651e8b
......@@ -8,9 +8,9 @@ FAMILY: SILECS
NAME: UDTB
STRUCT
_version: STRING[16] := 'SILECS_DEV';
_checksum: DWORD := DW#16#eae21021;
_checksum: DWORD := DW#16#5af1c2ef;
_user: STRING[16] := 'schwinn';
_date: DT := DT#2016-7-14-16:7:40;
_date: DT := DT#2017-6-6-16:14:50;
END_STRUCT;
END_TYPE
......
silecs-codegen/src/xml/test/generated_correct/controller/Siemens_Step7Device.scl
+ 2
− 2
View file @ e3651e8b
......@@ -8,9 +8,9 @@ FAMILY: SILECS
NAME: UDTB
STRUCT
_version: STRING[16] := 'SILECS_DEV';
_checksum: DWORD := DW#16#eae21021;
_checksum: DWORD := DW#16#5af1c2ef;
_user: STRING[16] := 'schwinn';
_date: DT := DT#2016-7-14-16:7:24;
_date: DT := DT#2017-6-6-16:14:50;
END_STRUCT;
END_TYPE
......
silecs-codegen/src/xml/test/generated_correct/controller/Siemens_TiaBlock.scl
+ 2
− 2
View file @ e3651e8b
......@@ -8,9 +8,9 @@ FAMILY: SILECS
NAME: UDTB
STRUCT
_version: STRING[16] := 'SILECS_DEV';
_checksum: DWORD := DW#16#eae21021;
_checksum: DWORD := DW#16#5af1c2ef;
_user: STRING[16] := 'schwinn';
_date: DT := DT#2016-7-14-16:7:12;
_date: DT := DT#2017-6-6-16:14:50;
END_STRUCT;
END_TYPE
......
silecs-codegen/src/xml/test/generated_correct/controller/Siemens_TiaDevice.scl
+ 2
− 2
View file @ e3651e8b
......@@ -8,9 +8,9 @@ FAMILY: SILECS
NAME: UDTB
STRUCT
_version: STRING[16] := 'SILECS_DEV';
_checksum: DWORD := DW#16#eae21021;
_checksum: DWORD := DW#16#5af1c2ef;
_user: STRING[16] := 'schwinn';
_date: DT := DT#2016-7-14-16:6:23;
_date: DT := DT#2017-6-6-16:14:50;
END_STRUCT;
END_TYPE
......
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