Commits · ad43a815a41c60854376c094ea31a2e4f1768471 · s.kupiecki / opensilecs

May 06, 2022

rename "multiplexed" to "cycle-bound" for fess 7.3.0 · ad43a815

al.schwinn authored 2 years ago

Support for FESA Version: 7.3.0
- Add unit tests for Fesa 7.3.0
- Run unit-tests only for latest FESA version

ad43a815

May 03, 2022
- fesa xml attributes order changes for unknown reason · 81017cfd
  al.schwinn authored 2 years ago
  
  81017cfd
- fix Beckhof checksum calculation · 0c61517b
  al.schwinn authored 2 years ago
  
  0c61517b
- Port to python3: · cc4a8f1e
  al.schwinn authored 2 years ago
  
  - print needs braces now - type 'long' does not exist any more --> use 'int' - use encode() toget byte string - ignore __pycache__ files - strictly use integer, to prevent float notation
  cc4a8f1e
Jan 20, 2021
- Additional Silecs Include added into Make.specific in class ( #45 ) · 4b1fb761
  al.schwinn authored 7 years ago and al.schwinn committed 4 years ago
  
  4b1fb761
- Additional Silecs Include added into Make.specific in class ( #45 ) · 45d7165a
  al.schwinn authored 7 years ago and al.schwinn committed 4 years ago
  
  45d7165a
Jan 31, 2018
- Bug in c-codegen for FESA-class missing tests, wrong unsigned types, · 8c7293bc
  al.schwinn authored 7 years ago
  
  optional context (#43)
  gsi-2.1.1
  
  8c7293bc
- Fix bugs in FESA codegen for unsigned types, arrays and 2D arrays (#41) · d48b6613
  al.schwinn authored 7 years ago
  
  - fixed tests
  d48b6613
- Fix bugs in FESA codegen for unsigned types, arrays and 2D arrays (#41) · 670156c6
  al.schwinn authored 7 years ago
  
  670156c6
- Dont overwrite all PLC Registers of a Block if only one Register is set · 67cf29a3
  al.schwinn authored 7 years ago
  
  (#2)
  67cf29a3
Jan 30, 2018
- - #2 Dont overwrite all PLC Registers of a Block if only one Register is · 1b852120
  al.schwinn authored 7 years ago
  
  set
  1b852120
Dec 13, 2017
- [SIL-441] Added PSrvEvent to generated userFunction of virtualS7 · 620edeed
  al.schwinn authored 7 years ago
  
  620edeed
Dec 12, 2017
- [SIL-441] Added PSrvEvent to generated userFunction of virtualS7 · 2b81609f
  Andres Rodriguez Perez authored 7 years ago and al.schwinn committed 7 years ago
  
  2b81609f
Oct 10, 2017
- #8 - WRITE-ONLY blocks should result in FESA-Command properties · 9588c066
  al.schwinn authored 7 years ago
  
  9588c066
Oct 09, 2017
- updated integration-tests of siemens virtual controller · 6dfddaa2
  al.schwinn authored 7 years ago
  
  6dfddaa2
- minor fixes on integration-tests · 382d90d5
  al.schwinn authored 7 years ago
  
  382d90d5
- updated integration tests to current codegen · ef367615
  al.schwinn authored 7 years ago
  
  ef367615
Sep 29, 2017
- #1 Add support for direct IO communication, like CERN already does · 7cd415b8
  al.schwinn authored 7 years ago
  
  - Force usage of Command-IO-Block for Siemens PLC's
  7cd415b8
Sep 22, 2017
- #6 - Removed leftover dependency to instance-parameter-file · 90e51e6b
  al.schwinn authored 7 years ago
  
  90e51e6b
- #1 - Add support for direct IO communication, like CERN already does · 403b2bca
  al.schwinn authored 7 years ago
  
  - fixed remaining codegen bugs
  403b2bca
- #1 Add support for direct IO communication, like CERN already does - fix · a61c374e
  al.schwinn authored 7 years ago
  
  migration to support new elements
  a61c374e
Sep 08, 2017
- [SIL-289] Eclipse outline useless with IDs instead of names · 21aada3c
  kochalas authored 7 years ago and al.schwinn committed 7 years ago
  
  21aada3c
- [SIL-309] Clean-up · 14690569
  flocci authored 7 years ago and al.schwinn committed 7 years ago
  
  14690569
- [SIL-324] Generated code for Siemen S7-12xx controller familly · 5c3fe746
  flocci authored 7 years ago and al.schwinn committed 7 years ago
  
  5c3fe746
- [SIL-309] Do not generate any memory segments (Schneider) and DB blocks · f08247ee
  flocci authored 7 years ago and al.schwinn committed 7 years ago
  
  (Siemens) for corresponding IO blocks
  f08247ee
- [SIL-353] Provide support for 64bits registers · 7460e237
  flocci authored 7 years ago and al.schwinn committed 7 years ago
  
  7460e237
- [SIL-353] Provide support for 64bits registers · f274cdf4
  flocci authored 7 years ago and al.schwinn committed 7 years ago
  
  f274cdf4
- [SIL-324] Upgrade S7 code generation for SIMATIC CPU-12xx · 452c5696
  flocci authored 7 years ago and al.schwinn committed 7 years ago
  
  452c5696
Jul 28, 2017
- [SIL-278] RIO Parameter file generation · b1d153ae
  flocci authored 7 years ago and al.schwinn committed 7 years ago
  
  b1d153ae
Jul 26, 2017
- [SIL-278] RIO Parameter file generation · 8d188273
  al.schwinn authored 7 years ago
  
  8d188273
Jul 24, 2017
- Bug 1470 - Add full model for .silecsparam · 631d699b
  al.schwinn authored 7 years ago
  
  631d699b
- [SIL-259] Main skeleton of the VC controller was missing · 93f798fc
  al.schwinn authored 7 years ago
  
  93f798fc
- [SIL-256] Review the hardware definition model of the SILECS DU · bf28ea02
  al.schwinn authored 7 years ago
  
  bf28ea02
- [SIL-231] Generate C++ code for virtual SIMATIC S7 controller · 10a6f0ee
  al.schwinn authored 7 years ago
  
  10a6f0ee
- [SIL-235] Support for Linux S7 virtual controller · 06a3378b
  al.schwinn authored 7 years ago
  
  06a3378b
Jul 20, 2017
- Bug 1441 - Restructurization of silecsdeploy - allow to use only one · 4fb0274e
  al.schwinn authored 7 years ago
  
  controller-file for identical controllers
  4fb0274e
- revert of Bug 1445 - move generated code for fesa-class into "generated" · d86d5937
  al.schwinn authored 7 years ago
  
  d86d5937
- Bug 1452 - Remove path to .silecsparam from instance-file · 3422e3f0
  al.schwinn authored 7 years ago and al.schwinn committed 7 years ago
  
  3422e3f0
- revert of Bug 1445 - move generated code for fesa-class into "generated" · c0a1984d
  al.schwinn authored 7 years ago
  
  folder
  c0a1984d
- Bug 1441 - Restructurization of silecsdeploy - fixed xsd · 02187287
  al.schwinn authored 7 years ago and al.schwinn committed 7 years ago
  
  02187287