[SIL-324] Upgrade S7 code generation for SIMATIC CPU-12xx

silecs-codegen/src/xml/s7template.py

@@ -54,11 +54,12 @@ whichSimaticFormat = {
 #=========================================================================
 # STL Source template (.scl file)
 #=========================================================================
-
-firstBlockUDT = """//---------------------------------------------------------------------\r
-// %s/ v%s\r
-// BLOCK Type definition\r
-//---------------------------------------------------------------------\r
+firstBlockUDT = """\r
+(* ---------------------------------------------------------------------\r
+ * %s/ v%s\r
+ * BLOCK Type definition\r
+ * ---------------------------------------------------------------------\r
+ *)\r
 """
 
 blockUDT = """TYPE _%s_%s\r
@@ -84,10 +85,12 @@ regArray2d =  """        %s: ARRAY[0..%d, 0..%d] OF %s%s;\r
 regFixedStringLen = """		%s: STRING[16]%s;\r
 """
 
-firstBlock = """//---------------------------------------------------------------------\r
-// %s/ v%s\r
-// Block instance definition\r
-//---------------------------------------------------------------------\r
+firstBlock = """\r
+(* ---------------------------------------------------------------------\r
+ * %s/ v%s\r
+ * BLOCK instance definition\r
+ * ---------------------------------------------------------------------\r
+ *)\r
 """
 
 DB_TIAP = """DATA_BLOCK %s_%s\r
@@ -102,7 +105,7 @@ END_DATA_BLOCK\r
 \r
 """
 
-DB_STEP7 = """// %s_%s ...........................................\r
+DB_STEP7 = """(* %s_%s ...........................................*)\r
 DATA_BLOCK DB%s\r
 { S7_Optimized_Access := 'FALSE' }\r
 AUTHOR:    %s\r