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  • UTCS_HB.lvproj
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  • Holger Brand's avatar
    Recompile FPGA with Counter input assigned to Connector1/DIO1 (Connector1/DIO0... · c5ac4015
    Holger Brand authored Mar 06, 2019
    Recompile FPGA with Counter input assigned to Connector1/DIO1 (Connector1/DIO0 is defect due to emergency power break)
    Update description of interlock reason indicator in other VIs.
    c5ac4015

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